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/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
10 - reg : Address and size of L2 cache controller registers
11 - cache-size : Size of the entire L2 cache
12 - interrupts : Error interrupt of L2 controller
13 - cache-line-size : Size of L2 cache lines
17 L2: l2-cache-controller@20000 {
21 cache-size = <0x40000>; // L2,256K
Dcache_sram.txt11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
17 fsl,cache-sram-ctlr-handle = <&L2>;
Dmpc5200.txt180 of three cells; <L1 L2 level>
183 L2 := interrupt number; directly mapped from the value in the
/linux-4.1.27/arch/mips/cavium-octeon/
DKconfig38 bool "Lock often used kernel code in the L2"
41 Enable locking parts of the kernel into the L2 cache.
44 bool "Lock the TLB handler in L2"
48 Lock the low level TLB fast path into L2.
51 bool "Lock the exception handler in L2"
55 Lock the low level exception handler into L2.
58 bool "Lock the interrupt handler in L2"
62 Lock the low level interrupt handler into L2.
65 bool "Lock the 2nd level interrupt handler in L2"
69 Lock the 2nd level interrupt handler in L2.
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/cpufreq/
Darm_big_little_dt.txt31 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
Dcpufreq-dt.txt34 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
62 next-level-cache = <&L2>;
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dl2cc.txt1 * ARM L2 Cache Controller
4 implementations of the L2 cache controller with compatible programming models.
9 The ARM L2 cache representation in the device tree should be done as follows:
19 offset needs to be added to the address before passing down to the L2
23 maintenance operations on L1 are broadcasted to the L2 and L2
59 - wt-override: If present then L2 is forced to Write through mode
73 L2: cache-controller {
/linux-4.1.27/arch/arm/boot/dts/
Dhighbank.dts37 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
74 next-level-cache = <&L2>;
119 L2: l2-cache { label
Dvexpress-v2p-ca9.dts40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
54 next-level-cache = <&L2>;
61 next-level-cache = <&L2>;
169 L2: cache-controller@1e00a000 { label
230 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
275 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
289 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
Dbcm4708.dtsi22 next-level-cache = <&L2>;
29 next-level-cache = <&L2>;
Dvf610.dtsi13 next-level-cache = <&L2>;
17 L2: l2-cache@40006000 { label
Dbcm63138.dtsi27 next-level-cache = <&L2>;
34 next-level-cache = <&L2>;
64 L2: cache-controller@1d000 { label
Dqcom-apq8084.dtsi22 next-level-cache = <&L2>;
33 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
61 L2: l2-cache { label
Dimx6q.dtsi28 next-level-cache = <&L2>;
62 next-level-cache = <&L2>;
69 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
Dqcom-msm8974.dtsi22 next-level-cache = <&L2>;
33 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
61 L2: l2-cache { label
Dmeson8.dtsi62 next-level-cache = <&L2>;
69 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
83 next-level-cache = <&L2>;
Dqcom-msm8660.dtsi23 next-level-cache = <&L2>;
31 next-level-cache = <&L2>;
34 L2: l2-cache { label
Dqcom-apq8064.dtsi23 next-level-cache = <&L2>;
34 next-level-cache = <&L2>;
45 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
62 L2: l2-cache { label
Dvexpress-v2p-ca5s.dts40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
114 L2: cache-controller@2c0f0000 { label
Dimx6dl.dtsi28 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
Dqcom-msm8960.dtsi24 next-level-cache = <&L2>;
34 next-level-cache = <&L2>;
39 L2: l2-cache { label
Dbcm47081.dtsi22 next-level-cache = <&L2>;
Dvf610-colibri.dtsi22 &L2 {
Dmeson6.dtsi63 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
Dspear13xx.dtsi27 next-level-cache = <&L2>;
34 next-level-cache = <&L2>;
52 L2: l2-cache { label
Dqcom-ipq8064.dtsi22 next-level-cache = <&L2>;
32 next-level-cache = <&L2>;
37 L2: l2-cache { label
Dhi3620.dtsi42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
75 L2: l2-cache { label
Drk3188.dtsi32 next-level-cache = <&L2>;
51 next-level-cache = <&L2>;
57 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
Dsocfpga_arria10.dtsi44 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
256 L2: l2-cache@fffff000 { label
Dbcm-cygnus.dtsi50 next-level-cache = <&L2>;
224 L2: l2-cache { label
Dbcm5301x.dtsi77 L2: cache-controller@2000 { label
Dpxa910.dtsi29 L2: l2-cache { label
Dsocfpga.dtsi44 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
621 L2: l2-cache@fffef000 { label
Dkirkwood-b3.dts12 * L2 cache. If your B3 silently fails to boot, u-boot is probably too
Drk3066a.dtsi32 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
Dmeson.dtsi53 L2: l2-cache-controller@c4200000 { label
Dstih415.dtsi16 L2: cache-controller { label
Dmmp2.dtsi30 L2: l2-cache { label
Domap4.dtsi37 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
62 L2: l2-cache-controller@48242000 { label
Dbcm21664.dtsi93 L2: l2-cache { label
Darmada-xp.dtsi78 L2: l2-cache { label
Dzynq-7000.dtsi139 L2: cache-controller@f8f02000 { label
Dimx35.dtsi51 L2: l2-cache@30000000 { label
Dbcm11351.dtsi103 L2: l2-cache { label
Dimx6sl.dtsi44 next-level-cache = <&L2>;
108 L2: l2-cache@00a02000 { label
Drk3xxx.dtsi85 L2: l2-cache-controller@10138000 { label
Darmada-370.dtsi128 L2: l2-cache { label
Darm-realview-pb1176.dts191 L2: l2-cache { label
/linux-4.1.27/drivers/net/ethernet/intel/i40evf/
Di40e_common.c229 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
231 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
235 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
239 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
240 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
242 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/linux-4.1.27/arch/c6x/kernel/
Dhead.S24 SUB .L2 B6,B5,B6 ; bss size
33 ZERO .L2 B13
34 ZERO .L2 B12
38 CMPLT .L2 B0,0,B1
Dentry.S123 MVK .L2 0,B1
221 CMPLTU .L2 B0,B1,B1
327 MVK .L2 1,B2
339 CMPLTU .L2 B0,B1,B1
Dswitch_to.S51 || MV .L2 B6,B14
/linux-4.1.27/arch/c6x/lib/
Dcsum_64plus.S57 || ADD .L2 B8,B9,B9
83 CMPGT .L2 B5,0,B0
193 CMPGT .L2 B0,0,B1
293 CMPGT .L2 B4,0,B0
299 || MV .L2 B4,B3
303 [A0] SUB .L2 B3,1,B3
308 SUB .L2 B3,1,B3
319 SUB .L2 B0,1,B0
347 MVK .L2 2,B0
348 AND .L2 B3,B0,B0
/linux-4.1.27/arch/powerpc/boot/dts/fsl/
Db4860si-pre.dtsi68 next-level-cache = <&L2>;
75 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
89 next-level-cache = <&L2>;
Dp1021si-pre.dtsi62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
Dbsc9132si-pre.dtsi57 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
Dmpc8572si-pre.dtsi64 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
Dp1020si-pre.dtsi62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
Dp1022si-pre.dtsi62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
Db4420si-pre.dtsi68 next-level-cache = <&L2>;
75 next-level-cache = <&L2>;
Dp2020si-pre.dtsi63 next-level-cache = <&L2>;
69 next-level-cache = <&L2>;
Dp1023si-pre.dtsi70 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
Dbsc9131si-post.dtsi96 L2: l2-cache-controller@20000 { label
100 cache-size = <0x40000>; // L2,256K
Dbsc9132si-post.dtsi97 L2: l2-cache-controller@20000 { label
101 cache-size = <0x40000>; // L2,256K
Dmpc8548si-post.dtsi136 L2: l2-cache-controller@20000 { label
140 cache-size = <0x80000>; // L2, 512K
Dc293si-post.dtsi104 L2: l2-cache-controller@20000 { label
108 cache-size = <0x80000>; // L2,512K
Dmpc8544si-post.dtsi167 L2: l2-cache-controller@20000 { label
171 cache-size = <0x40000>; // L2, 256K
Dp2020si-post.dtsi164 L2: l2-cache-controller@20000 { label
168 cache-size = <0x80000>; // L2,512K
Dmpc8572si-post.dtsi168 L2: l2-cache-controller@20000 { label
172 cache-size = <0x100000>; // L2,1M
Dp1020si-post.dtsi136 L2: l2-cache-controller@20000 { label
140 cache-size = <0x40000>; // L2,256K
Dp1010si-post.dtsi148 L2: l2-cache-controller@20000 { label
153 cache-size = <0x40000>; // L2,256K
Dp1021si-post.dtsi136 L2: l2-cache-controller@20000 { label
140 cache-size = <0x40000>; // L2,256K
Dmpc8536si-post.dtsi192 L2: l2-cache-controller@20000 { label
196 cache-size = <0x80000>; // L2, 512K
Dp1023si-post.dtsi163 L2: l2-cache-controller@20000 { label
167 cache-size = <0x40000>; // L2,256K
Dp1022si-post.dtsi197 L2: l2-cache-controller@20000 { label
201 cache-size = <0x40000>; // L2,256K
Dmpc8568si-post.dtsi148 L2: l2-cache-controller@20000 { label
152 cache-size = <0x80000>; // L2, 512K
Dbsc9131si-pre.dtsi59 next-level-cache = <&L2>;
Dmpc8536si-pre.dtsi63 next-level-cache = <&L2>;
Dmpc8544si-pre.dtsi63 next-level-cache = <&L2>;
Dmpc8548si-pre.dtsi64 next-level-cache = <&L2>;
Dc293si-pre.dtsi60 next-level-cache = <&L2>;
Dmpc8569si-pre.dtsi62 next-level-cache = <&L2>;
Dmpc8568si-pre.dtsi63 next-level-cache = <&L2>;
Dp1010si-pre.dtsi64 next-level-cache = <&L2>;
Dmpc8569si-post.dtsi142 L2: l2-cache-controller@20000 { label
146 cache-size = <0x80000>; // L2, 512K
Db4420si-post.dtsi103 L2: l2-cache-controller@c20000 { label
Db4860si-post.dtsi205 L2: l2-cache-controller@c20000 { label
Db4si-post.dtsi351 L2: l2-cache-controller@c20000 { label
/linux-4.1.27/arch/powerpc/boot/dts/
Dmpc8572ds_camp_core1.dts4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
62 cache-size = <0x80000>; // L2, 512K
84 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
Dmpc8572ds_camp_core0.dts4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
45 cache-size = <0x80000>; // L2, 512K
Dp1020rdb-pc_camp_core1.dts4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
106 16 /* ecm, mem, L2, pci0, pci1 */
Dstx_gp3_8560.dts41 next-level-cache = <&L2>;
78 L2: l2-cache-controller@20000 { label
82 cache-size = <0x40000>; // L2, 256K
Dtqm8555.dts42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x40000>; // L2, 256K
Dtqm8540.dts43 next-level-cache = <&L2>;
80 L2: l2-cache-controller@20000 { label
84 cache-size = <0x40000>; // L2, 256K
Dtqm8541.dts42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x40000>; // L2, 256K
Dsocrates.dts43 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x40000>; // L2, 256K
Dsbc8548-pre.dtsi43 next-level-cache = <&L2>;
Dksi8560.dts43 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x40000>; /* L2, 256K */
Dtqm8560.dts44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x40000>; // L2, 256K
Dp1020rdb-pc_camp_core0.dts4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
Dp1020rdb.dts24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
Dp1020rdb_36b.dts24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
Dxpedite5200.dts42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x80000>; // L2, 512K
Dmpc8540ads.dts45 next-level-cache = <&L2>;
82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
Dmpc8555cds.dts45 next-level-cache = <&L2>;
82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
Dstxssa8555.dts44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x40000>; // L2, 256K
Dmpc8541cds.dts45 next-level-cache = <&L2>;
82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
Dxpedite5370.dts42 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
192 L2: l2-cache-controller@20000 { label
196 cache-size = <0x100000>; // L2, 1M
Dxpedite5301.dts44 next-level-cache = <&L2>;
57 next-level-cache = <&L2>;
194 L2: l2-cache-controller@20000 { label
198 cache-size = <0x100000>; // L2, 1M
Dxpedite5200_xmon.dts46 next-level-cache = <&L2>;
83 L2: l2-cache-controller@20000 { label
87 cache-size = <0x80000>; // L2, 512K
Dtqm8548-bigflash.dts44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x80000>; // L2, 512K
Dtqm8548.dts44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x80000>; // L2, 512K
Dmpc8536ds.dts26 next-level-cache = <&L2>;
Dxpedite5330.dts80 next-level-cache = <&L2>;
93 next-level-cache = <&L2>;
230 L2: l2-cache-controller@20000 { label
234 cache-size = <0x100000>; // L2, 1M
Dxcalibur1501.dts43 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
201 L2: l2-cache-controller@20000 { label
205 cache-size = <0x100000>; // L2, 1M
Dmpc8536ds_36b.dts26 next-level-cache = <&L2>;
Dsbc8548-post.dtsi43 L2: l2-cache-controller@20000 { label
47 cache-size = <0x80000>; // L2, 512K
Dp1020mbg-pc_36b.dts47 /* NOR and L2 switch */
Dp1020rdb-pc_32b.dts47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
Dp1020rdb-pc_36b.dts47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
Dp1021rdb-pc_32b.dts47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
Dp1020mbg-pc_32b.dts47 /* NOR and L2 switch */
Darches.dts131 0x030 0x008>; /* L2 cache DCR's */
133 cache-size = <262144>; /* L2, 256K */
Dp1021rdb-pc_36b.dts47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
Dmpc8560ads.dts82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
Dtaishan.dts112 0x030 0x008>; /* L2 cache DCR's */
114 cache-size = <262144>; /* L2, 256K */
Dp1020rdb-pd.dts47 /* NOR, NAND flash, L2 switch and CPLD */
Dglacier.dts113 0x030 0x008>; /* L2 cache DCR's */
115 cache-size = <262144>; /* L2, 256K */
Dcanyonlands.dts120 0x030 0x008>; /* L2 cache DCR's */
122 cache-size = <262144>; /* L2, 256K */
/linux-4.1.27/arch/arc/kernel/
Dentry.S200 ; if L2 IRQ interrupted a L1 ISR, disable preemption
204 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
654 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
673 ; However the context returning might not have taken L2 intr itself
674 ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
675 ; Special considerations needed for the context which took L2 intr
677 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
681 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
684 ; things to what they were, before returning from L2 context
688 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
37 2 = l2clk (L2 Cache clock derived from CPU0 clock)
/linux-4.1.27/Documentation/networking/
Dipvlan.txt10 the master device share the L2 with it's slave devices. I have developed this
31 IPvlan has two modes of operation - L2 and L3. For a given master device,
38 4.1 L2 mode:
47 master device for the L2 processing and routing from that instance will be
61 namespace where L2 on the slave could be changed / misused.
Dswitchdev.txt5 This include devices supporting L2/L3 but also various flow offloading chips,
Dvxge.txt85 are not replicated at the internal L2 switch.
/linux-4.1.27/arch/score/lib/
Dstring.S34 ble .L2
40 beq .L2
54 .L2: label
/linux-4.1.27/arch/m68k/lib/
Ddivsi3.S101 jpl L2
109 L2: movel d1, sp@- label
Dudivsi3.S148 jcs L2 | if no carry,
151 L2: subql IMM (1),d4 label
/linux-4.1.27/arch/alpha/kernel/
Dsetup.c1354 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1377 L2 = external_cache_probe(128*1024, 5); in determine_cpu_caches()
1391 L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1); in determine_cpu_caches()
1405 L2 = CSHAPE (96*1024, width, 3); in determine_cpu_caches()
1439 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); in determine_cpu_caches()
1441 L2 = external_cache_probe(512*1024, 6); in determine_cpu_caches()
1453 L2 = external_cache_probe(1024*1024, 6); in determine_cpu_caches()
1460 L2 = CSHAPE(7*1024*1024/4, 6, 7); in determine_cpu_caches()
1466 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1472 alpha_l2_cacheshape = L2; in determine_cpu_caches()
/linux-4.1.27/Documentation/zh_CN/arm64/
Dmemory.txt89 | | | +-----------> [29:21] L2 索引
104 | | +--------------------------> [41:29] L2 索引
/linux-4.1.27/arch/m68k/fpsp040/
Dsetox.S105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
498 movew L2,L_SCR1(%a6) | ...prefetch L2, no need in CB
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
665 | MOVE.W #$3FDC,L2 ...prefetch L2 in CB mode
672 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
/linux-4.1.27/drivers/cpufreq/
Dexynos4210-cpufreq.c37 {0, L2, 800 * 1000},
165 info->pll_safe_idx = L2; in exynos4210_cpufreq_init()
Ds5pv210-cpufreq.c111 L0, L1, L2, L3, L4, enumerator
128 {0, L2, 400*1000},
154 [L2] = {
Dexynos-cpufreq.h13 L0, L1, L2, L3, L4, enumerator
Dexynos5250-cpufreq.c40 {0, L2, 1500 * 1000},
Dexynos4x12-cpufreq.c38 {0, L2, 1300 * 1000},
Dexynos5440-cpufreq.c93 L0, L1, L2, L3, L4, enumerator
/linux-4.1.27/arch/arm/mach-omap2/
Dsleep44xx.S153 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
315 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
320 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
323 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
Dsleep34xx.S428 cmp r0, #0x1 @ should we disable L2 on 3630?
431 bic r0, r0, #2 @ disable L2 cache
484 mov r12, #0x1 @ set up to invalidate L2
501 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
504 orr r1, r1, #2 @ re-enable L2 cache
/linux-4.1.27/arch/arm/mach-tegra/
DKconfig33 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
44 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
/linux-4.1.27/arch/sh/lib/
D__clear_user.S81 .L2: dt r3 define
83 bf/s .L2
/linux-4.1.27/arch/arm/plat-omap/
DKconfig118 bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
122 Without this option, L2 Auxiliary control register contents are
128 int "Service ID for the support routine to set L2 AUX control"
132 PPA routine service ID for setting L2 auxiliary control register.
/linux-4.1.27/scripts/rt-tester/
Dt5-l4-pi-boost-deboost.tst73 # T2 lock L2
87 # T3 lock L2
Dt5-l4-pi-boost-deboost-setsched.tst73 # T2 lock L2
87 # T3 lock L2
/linux-4.1.27/arch/metag/tbx/
Dtbidspram.S77 $L2:
84 BR $L2
/linux-4.1.27/arch/arm/mm/
Dproc-xsc3.S368 orr r0, r0, #0x18 @ cache the page table in L2
441 orr r1, r1, #0x18 @ cache the page table in L2
457 orr r4, r4, #0x18 @ cache the page table in L2
465 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
472 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
474 orrne r6, r6, #(1 << 26) @ enable L2 if present
Dl2c-l2x0-resume.S34 @ and can be written whether or not the L2 cache is enabled
Dproc-mohawk.S333 orr r0, r0, #0x18 @ cache the page table in L2
378 orr r1, r1, #0x18 @ cache the page table in L2
392 orr r4, r4, #0x18 @ cache the page table in L2
DKconfig871 bool "Enable the Feroceon L2 cache controller"
876 This option enables the Feroceon L2 cache controller.
879 bool "Force Feroceon L2 cache write through"
882 Say Y here to use the Feroceon L2 cache in writethrough mode.
912 The PL310 L2 cache controller implements three types of Clean &
924 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
960 bool "Enable the Tauros2 L2 cache controller"
965 This option enables the Tauros2 L2 cache controller (as
969 bool "Enable the L2 cache on XScale3"
974 This option enables the L2 cache on XScale3.
Dproc-feroceon.S81 mcr p15, 1, r0, c15, c9, 0 @ clean L2
458 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
511 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
Dproc-v7.S375 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
378 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
/linux-4.1.27/arch/blackfin/kernel/cplb-nompu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.1.27/arch/blackfin/kernel/cplb-mpu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.1.27/Documentation/devicetree/bindings/arm/mrvl/
Dferoceon.txt8 - reg : Address of the L2 cache control register. Mandatory for
Dtauros2.txt14 L2: l2-cache {
/linux-4.1.27/Documentation/devicetree/bindings/arm/calxeda/
Dl2ecc.txt1 Calxeda Highbank L2 cache ECC
/linux-4.1.27/Documentation/arm64/
Dmemory.txt69 | | | +-----------> [29:21] L2 index
84 | | +--------------------------> [41:29] L2 index
/linux-4.1.27/drivers/net/ethernet/atheros/
DKconfig22 tristate "Atheros L2 Fast Ethernet support"
27 This driver supports the Atheros L2 fast ethernet adapter.
/linux-4.1.27/net/switchdev/
DKconfig11 meaning of the word "switch". This include devices supporting L2/L3 but
/linux-4.1.27/arch/xtensa/lib/
Dmemset.S85 bbci.l a4, 3, .L2
90 .L2: label
Dusercopy.S178 bbci.l a4, 3, .L2
186 .L2: label
Dmemcopy.S168 bbci.l a4, 3, .L2
176 .L2: label
/linux-4.1.27/Documentation/devicetree/bindings/power/
Dopp.txt18 next-level-cache = <&L2>;
/linux-4.1.27/drivers/staging/fsl-mc/bus/
DKconfig19 or L2 switches.
/linux-4.1.27/Documentation/devicetree/bindings/arm/omap/
Dmpu.txt5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
/linux-4.1.27/Documentation/devicetree/bindings/net/
Dfsl-tsec-phy.txt61 buffer descriptors in the L2.
63 in the L2.
65 buffer to stash in the L2.
/linux-4.1.27/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,l2-intc.txt17 - brcm,irq-can-wake: If present, this means the L2 controller can be used as a
Dst,sti-irq-syscfg.txt5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
Dbrcm,bcm3380-l2-intc.txt28 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
Dbrcm,bcm7120-l2-intc.txt70 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
/linux-4.1.27/arch/metag/mm/
DKconfig73 Press y here to enable support for the Meta Level 2 (L2) cache. This
77 If the bootloader enables the L2 you must press y here to ensure the
/linux-4.1.27/Documentation/locking/
Drt-mutex-design.txt129 Mutexes: L1, L2, L3, L4
133 B owns L2
134 C blocked on L2
142 E->L4->D->L3->C->L2->B->L1->A
156 E->L4->D->L3->C->L2-+
168 blocked on mutex L2:
170 G->L2->B->L1->A
176 +->L2-+
239 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
240 The following shows a locking order of L1->L2->L3, but may not actually
[all …]
Dlockdep-design.txt86 <L1> -> <L2>
87 <L2> -> <L1>
/linux-4.1.27/drivers/net/ethernet/intel/i40e/
Di40e_common.c228 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
229 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
230 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
233 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
234 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
237 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
238 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
239 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/timer/
Dmarvell,armada-370-xp-timer.txt22 "nbclk" (L2/coherency fabric clock),
/linux-4.1.27/Documentation/devicetree/bindings/watchdog/
Dmarvel.txt29 "nbclk" (L2/coherency fabric clock),
/linux-4.1.27/net/l2tp/
DKconfig58 mechanism for tunneling Layer 2 (L2) "circuits" across a
63 L2 protocols, including ATM, Frame Relay, HDLC and even raw
/linux-4.1.27/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt9 such as network interfaces, crypto accelerator instances, L2 switches,
/linux-4.1.27/Documentation/virtual/kvm/
Dnested-vmx.txt31 call L2.
79 The name "vmcs12" refers to the VMCS that L1 builds for L2. In the code we
81 which L0 builds to actually run L2 - how this is done is explained in the
/linux-4.1.27/arch/x86/kernel/cpu/
Dperf_event_intel_ds.c58 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); in precise_store_data()
167 val |= P(TLB, MISS) | P(TLB, L2); in load_latency_data()
169 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); in load_latency_data()
/linux-4.1.27/arch/metag/lib/
Ddiv64.S14 $L2:
/linux-4.1.27/arch/blackfin/mach-bf561/
Dsecondary.S49 L2 = r6; define
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-rt5677.txt50 "DMIC L2", "Internal Mic 2",
/linux-4.1.27/arch/blackfin/mach-common/
Dhead.S58 L2 = r6; define
/linux-4.1.27/Documentation/devicetree/bindings/iommu/
Dsamsung,sysmmu.txt10 another capabilities like L2 TLB or block-fetch buffers to minimize translation
/linux-4.1.27/tools/perf/util/
Dparse-events.l212 LLC|L2 |
/linux-4.1.27/Documentation/mmc/
Dmmc-async-req.txt24 performance gain is 5% for large writes and 10% on large reads on a L2 cache
/linux-4.1.27/Documentation/infiniband/
Dipoib.txt37 and so the interface MTU has is equal to the IB L2 MTU minus the
/linux-4.1.27/Documentation/devicetree/bindings/arm/msm/
Dqcom,idle-state.txt49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
/linux-4.1.27/arch/arm64/
DKconfig298 AXI master interface and an L2 cache.
319 master interface and an L2 cache.
361 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
/linux-4.1.27/drivers/net/
DKconfig156 on packets. All interfaces (including the main interface) share L2
157 making it transparent to the connected L2 switch.

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