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Searched refs:L1D (Results 1 - 39 of 39) sorted by relevance

/linux-4.1.27/arch/arm/kernel/
H A D	perf_event_v7.c	188 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 189 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 190 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 191 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 238 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 239 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 240 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 241 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 275 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 276 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 277 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 278 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 279 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 280 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 322 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, 323 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, 324 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, 325 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, 376 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 377 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 378 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 379 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 420 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, 421 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 422 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, 423 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 481 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 482 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 483 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 484 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 522 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 523 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 524 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 525 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
H A D	perf_event_v6.c	87 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, 88 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, 89 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, 90 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, 150 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS, 151 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS, 152 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS, 153 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
H A D	perf_event_xscale.c	`64 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, 65 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, 66 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, 67 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,`
/linux-4.1.27/arch/tile/lib/
H A D	memcpy_32.S	261 /* Fill second L1D line. / 266 / Load seven words that are L1D hits to cover wh64 L2 usage. / 268 / Load the three remaining words from the last L1D line, which 269 * we know has already filled the L1D. 275 /* Load the three remaining words from the first L1D line, first 282 /* Load second word from the second L1D line, first 292 /* Use two L1D hits to cover the sw L2 access above. / 296 / Fill third L1D line. / 299 / Store first L1D line. / 304 / Store second L1D line. / 314 / Store third L1D line. / 320 / Store rest of fourth L1D line. */
/linux-4.1.27/arch/powerpc/perf/
H A D	e6500-pmu.c	`40 [C(L1D)] = {`
H A D	e500-pmu.c	`43 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	mpc7450-pmu.c	`362 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	power7-pmu.c	`339 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	ppc970-pmu.c	`440 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	power5+-pmu.c	`626 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	power5-pmu.c	`568 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	power6-pmu.c	`489 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	power4-pmu.c	`560 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */`
H A D	power8-pmu.c	`702 [ C(L1D) ] = {`
/linux-4.1.27/arch/c6x/platforms/
H A D	cache.c	`105 #define CCFG_IP 0x200 /* Invalidate L1D bit / 254 L1D global-invalidate all 256 * Warning: this operation causes all updated data in L1D to`
/linux-4.1.27/arch/alpha/kernel/
H A D	setup.c	1354 int L1I, L1D, L2, L3; determine_cpu_caches() local 1364 L1D = L1I; determine_cpu_caches() 1385 L1I = L1D = CSHAPE(81024, 5, 1); determine_cpu_caches() 1400 L1I = L1D = CSHAPE(81024, 5, 1); determine_cpu_caches() 1426 L1D = CSHAPE(81024, 5, 1); determine_cpu_caches() 1429 L1D = CSHAPE(161024, 5, 1); determine_cpu_caches() 1452 L1I = L1D = CSHAPE(641024, 6, 2); determine_cpu_caches() 1459 L1I = L1D = CSHAPE(641024, 6, 2); determine_cpu_caches() 1466 L1I = L1D = L2 = L3 = 0; determine_cpu_caches() 1471 alpha_l1d_cacheshape = L1D; determine_cpu_caches()
/linux-4.1.27/arch/x86/kernel/cpu/
H A D	perf_event_intel.c	78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D / 96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), / L1D / 330 [ C(L1D) ] = { 333 [ C(RESULT_MISS) ] = 0x0151, / L1D.REPLACEMENT / 337 [ C(RESULT_MISS) ] = 0x0851, / L1D.ALL_M_REPLACEMENT / 486 [ C(L1D ) ] = { 489 [ C(RESULT_MISS) ] = 0x151, / L1D.REPLACEMENT / 638 [ C(L1D) ] = { 641 [ C(RESULT_MISS) ] = 0x0151, / L1D.REPL / 645 [ C(RESULT_MISS) ] = 0x0251, / L1D.M_REPL / 821 [ C(L1D) ] = { 824 [ C(RESULT_MISS) ] = 0x0151, / L1D.REPL / 828 [ C(RESULT_MISS) ] = 0x0251, / L1D.M_REPL */ 936 [ C(L1D) ] = { 1027 [ C(L1D) ] = { 1155 [ C(L1D) ] = {
H A D	perf_event_knc.c	`25 [ C(L1D) ] = {`
H A D	perf_event_p6.c	`27 [ C(L1D) ] = {`
H A D	perf_event_amd.c	`15 [ C(L1D) ] = {`
H A D	perf_event_intel_ds.c	`95 * it missed L1D precise_store_data()`
H A D	perf_event_p4.c	`519 [ C(L1D ) ] = {`
/linux-4.1.27/arch/sh/kernel/cpu/sh4/
H A D	perf_event.c	`94 [ C(L1D) ] = {`
/linux-4.1.27/arch/arc/include/asm/
H A D	perf_event.h	`116 [C(L1D)] = {`
/linux-4.1.27/arch/mips/netlogic/common/
H A D	reset.S	`90 * L1D cache has to be flushed before enabling threads in XLP. 215 /* core L1D flush before enable threads */`
/linux-4.1.27/arch/mips/kernel/
H A D	perf_event_mipsxx.c	`866 [C(L1D)] = { 947 [C(L1D)] = { 1022 [C(L1D)] = { 1078 [C(L1D)] = { 1137 [C(L1D)] = { 1177 [C(L1D)] = {`
/linux-4.1.27/arch/c6x/kernel/
H A D	traps.c	`236 { "Oops - CPU memory protection fault in L1D", SIGSEGV, SEGV_ACCERR }, 237 { "Oops - DMA memory protection fault in L1D", SIGSEGV, SEGV_ACCERR },`
/linux-4.1.27/arch/sparc/kernel/
H A D	perf_event.c	`219 [C(L1D)] = { 357 [C(L1D)] = { 492 [C(L1D)] = { 629 [C(L1D)] = {`
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
H A D	perf_event.c	`119 [ C(L1D) ] = {`
/linux-4.1.27/arch/ia64/lib/
H A D	copy_page_mck.S	`34 * into L1D and p[D] is TRUE if a cacheline needs to be copied.`
/linux-4.1.27/arch/tile/kernel/
H A D	perf_event.c	`129 [C(L1D)] = { 219 [C(L1D)] = {`
/linux-4.1.27/arch/tile/include/asm/
H A D	processor.h	`299 /* Bring a value into the L1D, faulting the TLB if necessary. */`
/linux-4.1.27/arch/blackfin/kernel/
H A D	perf_event.c	`87 [C(L1D)] = { /* Data bank A */`
/linux-4.1.27/arch/ia64/kernel/
H A D	perfmon_mckinley.h	`158 * i-side events in L1D and L2 caches pfm_mck_pmc_check()`
H A D	perfmon_montecito.h	`241 * i-side events in L1D and L2 caches pfm_mont_pmc_check()`
H A D	ivt.S	`799 // If any of the above loads miss in L1D, we'll stall here until`
/linux-4.1.27/arch/metag/kernel/perf/
H A D	perf_event.c	`402 [C(L1D)] = {`
/linux-4.1.27/arch/arm64/kernel/
H A D	perf_event.c	`720 [C(L1D)] = {`
/linux-4.1.27/tools/perf/util/
H A D	evsel.c	`406 [C(L1D)] = (CACHE_READ \| CACHE_WRITE \| CACHE_PREFETCH),`

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