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/linux-4.1.27/arch/sparc/kernel/
Dcpu.c53 #define CPU(ver, _name) \ macro
67 CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
69 CPU(4, "Fujitsu MB86904"),
70 CPU(5, "Fujitsu TurboSparc MB86907"),
71 CPU(-1, NULL)
87 CPU(0, "LSI Logic Corporation - L64811"),
89 CPU(1, "Cypress/ROSS CY7C601"),
91 CPU(3, "Cypress/ROSS CY7C611"),
93 CPU(0xf, "ROSS HyperSparc RT620"),
94 CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
[all …]
/linux-4.1.27/Documentation/zh_CN/
Dio_ordering.txt35 CPU A: spin_lock_irqsave(&dev_lock, flags)
36 CPU A: val = readl(my_status);
37 CPU A: ...
38 CPU A: writel(newval, ring_ptr);
39 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
41 CPU B: spin_lock_irqsave(&dev_lock, flags)
42 CPU B: val = readl(my_status);
43 CPU B: ...
44 CPU B: writel(newval2, ring_ptr);
45 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
[all …]
/linux-4.1.27/Documentation/
Dio_ordering.txt14 CPU A: spin_lock_irqsave(&dev_lock, flags)
15 CPU A: val = readl(my_status);
16 CPU A: ...
17 CPU A: writel(newval, ring_ptr);
18 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
20 CPU B: spin_lock_irqsave(&dev_lock, flags)
21 CPU B: val = readl(my_status);
22 CPU B: ...
23 CPU B: writel(newval2, ring_ptr);
24 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
[all …]
Dkernel-per-CPU-kthreads.txt1 REDUCING OS JITTER DUE TO PER-CPU KTHREADS
3 This document lists per-CPU kthreads in the Linux kernel and presents
4 options to control their OS jitter. Note that non-per-CPU kthreads are
5 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
6 them to a "housekeeping" CPU dedicated to such work.
21 o /sys/devices/system/cpu/cpuN/online: Control CPU N's hotplug state,
24 o In order to locate kernel-generated OS jitter on CPU N:
39 that does not require per-CPU kthreads. This will prevent these
45 3. Rework the eHCA driver so that its per-CPU kthreads are
53 some other CPU.
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Dmemory-barriers.txt29 - CPU memory barriers.
39 (*) Inter-CPU locking barrier effects.
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
101 Each CPU executes a program that generates memory access operations. In the
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
109 CPU are perceived by the rest of the system as the operations cross the
110 interface between the CPU and rest of the system (the dotted lines).
115 CPU 1 CPU 2
142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
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Dcpu-hotplug.txt1 CPU hotplug Support in Linux(tm) Kernel
4 CPU Hotplug Core:
24 reporting and correction capabilities in processors. CPU architectures permit
25 partitioning support, where compute resources of a single CPU could be made
28 node insertion and removal require support for CPU hotplug.
31 provisioning reasons, or for RAS purposes to keep an offending CPU off
32 system execution path. Hence the need for CPU hotplug support in the
35 A more novel use of CPU-hotplug support is its use today in suspend
40 General Stuff about CPU Hotplug
74 CPU maps and such
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Dworkqueue.txt38 worker thread per CPU and a single threaded (ST) wq had one worker
41 wq users over the years and with the number of CPU cores continuously
48 worker pool. A MT wq could provide only one execution context per CPU
66 * Use per-CPU unified worker pools shared by all wq to provide
95 for high priority ones, for each possible CPU and some extra
103 things like CPU locality, concurrency limits, priority and more. To
112 is associated to the CPU the issuer is running on.
120 Each worker-pool bound to an actual CPU implements concurrency
124 not expected to hog a CPU and consume many cycles. That means
127 workers on the CPU, the worker-pool doesn't start execution of a new
[all …]
Dlocal_ops.txt20 Local atomic operations are meant to provide fast and highly reentrant per CPU
25 Having fast per CPU atomic counters is interesting in many cases : it does not
31 CPU which owns the data. Therefore, care must taken to make sure that only one
32 CPU writes to the local_t data. This is done by using per cpu data and making
34 permitted to read local_t data from any CPU : it will then appear to be written
35 out of order wrt other memory writes by the owner CPU.
56 - _Only_ the CPU owner of these variables must write to them.
57 - This CPU can use local ops from any context (process, irq, softirq, nmi, ...)
61 different CPU between getting the per-cpu variable and doing the
64 taken on a mainline kernel, since they will run on the local CPU with
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Dcputopology.txt2 Export CPU topology info via sysfs. Items (attributes) are similar
13 the CPU core ID of cpuX. Typically it is the hardware platform's
59 3) thread_siblings: just the given CPU
60 4) core_siblings: just the given CPU
65 Additionally, CPU topology information is provided under
69 kernel_max: the maximum CPU index allowed by the kernel configuration.
101 was manually taken offline (and is the only CPU that can be brought
Dbus-virt-phys-mapping.txt21 - CPU untranslated. This is the "physical" address. Physical address
22 0 is what the CPU sees when it drives zeroes on the memory bus.
24 - CPU translated address. This is the "virtual" address, and is
25 completely internal to the CPU itself with the CPU doing the appropriate
26 translations into "CPU untranslated".
29 not the CPU. Now, in theory there could be many different bus
41 CPU sees a memory map something like this (this is from memory):
51 So when the CPU wants any bus master to write to physical memory 0, it
116 use that from the CPU (the CPU only uses translated virtual addresses), and
124 management layer doesn't know about devices outside the CPU, so it
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Dpadata.txt36 Once an offline CPU in the user supplied cpumask comes online, padata
47 padata cpumask contains no active CPU (flag not set).
61 Changing the CPU masks are expensive operations, though, so it should not be
69 To simply add or remove one CPU from a certain cpumask the functions
70 padata_add_cpu/padata_remove_cpu are used. cpu specifies the CPU to add or
119 specifies which CPU will be used for the final callback when the work is
120 done; it must be in the current instance's CPU mask. The return value from
123 instance's CPU mask, while -EINVAL is a complaint about cb_cpu not being
124 in that CPU mask or about a not running instance.
127 exactly one call to the above-mentioned parallel() function, on one CPU, so
[all …]
DIRQ-affinity.txt19 it to CPU4-7 (this is an 8-CPU SMP box):
34 [root@moon 44]# cat /proc/interrupts | grep 'CPU\|44:'
40 Now lets restrict that IRQ to CPU(4-7).
51 [root@moon 44]# cat /proc/interrupts | 'CPU\|44:'
Dpreempt-locking.txt19 RULE #1: Per-CPU data structures need explicit protection
29 First, since the data is per-CPU, it may not have explicit SMP locking, but
37 RULE #2: CPU state must be protected.
40 Under preemption, the state of the CPU must be protected. This is arch-
41 dependent, but includes CPU structures and state not preserved over a context
94 cpucache_t *cc; /* this is per-CPU */
125 Note in 2.5 interrupt disabling is now only per-CPU (e.g. local).
DDMA-attributes.txt75 buffer from CPU domain to device domain. Some advanced use cases might
80 the buffer sharing. The first call transfers a buffer from 'CPU' domain
81 to 'device' domain, what synchronizes CPU caches for the given region
85 same synchronization operation on the CPU cache. CPU cache synchronization
89 the CPU cache for the given buffer assuming that it has been already
Dcircular-buffers.txt117 but the consumer may still be depleting the buffer on another CPU and
125 producer may still be filling the buffer on another CPU and moving the
182 This will instruct the CPU that the contents of the new item must be written
184 CPU that the revised head index must be written before the consumer is woken.
221 This will instruct the CPU to make sure the index is up to date before reading
222 the new item, and then it shall make sure the CPU has finished reading the item
230 The smp_load_acquire() additionally forces the CPU to order against
Dio-mapping.txt2 efficiently mapping small regions of an I/O device to the CPU. The initial
4 ioremap_wc cannot be used to statically map the entire aperture to the CPU
30 return value points to a single page in CPU address space.
DDMA-API-HOWTO.txt12 CPU and DMA addresses
22 addresses to CPU physical addresses, which are stored as "phys_addr_t" or
31 systems, bus addresses are identical to CPU physical addresses, but in
42 CPU CPU Bus
54 | CPU | | | | RAM | | | | Device |
67 from the BAR and converts it to a CPU physical address (B). The address B
77 cannot because DMA doesn't go through the CPU virtual memory system.
136 (The CPU could write to one word, DMA would write to a different one
317 guarantee that the device and the CPU can access the data
335 The invariant these examples all require is that any CPU store
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/linux-4.1.27/Documentation/zh_CN/arm64/
Dbooting.txt41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
137 - 主 CPU 通用寄存器设置
143 - CPU 模式
146 CPU 必须处于 EL2（推荐，可访问虚拟化扩展）或非安全 EL1 模式下。
159 CNTFRQ 必须设定为计时器的频率，且 CNTVOFF 必须设定为对所有 CPU
164 通过内核启动的所有 CPU 在内核入口地址上必须处于相同的一致性域中。
165 这可能要根据具体实现来定义初始化过程，以使能每个CPU上对维护操作的
180 以上对于 CPU 模式、高速缓存、MMU、架构计时器、一致性、系统寄存器的
181 必要条件描述适用于所有 CPU。所有 CPU 必须在同一异常级别跳入内核。
183 引导装载程序必须在每个 CPU 处于以下状态时跳入内核入口：
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Dlegacy_instructions.txt70 注：为了使能这个特性，系统中的所有 CPU 必须在 EL0 支持混合字节序。
71 如果一个新的 CPU （不支持混合字节序） 在使能这个特性后被热插入系统，
/linux-4.1.27/arch/mips/bcm63xx/
DKconfig1 menu "CPU support"
5 bool "support 3368 CPU"
10 bool "support 6328 CPU"
15 bool "support 6338 CPU"
20 bool "support 6345 CPU"
24 bool "support 6348 CPU"
29 bool "support 6358 CPU"
34 bool "support 6362 CPU"
39 bool "support 6368 CPU"
/linux-4.1.27/drivers/media/pci/cx18/
Dcx18-mailbox.c50 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
51 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
52 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
53 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
56 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
57 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
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/linux-4.1.27/Documentation/RCU/
Dstallwarn.txt1 Using RCU's CPU Stall Detector
3 The rcu_cpu_stall_suppress module parameter enables RCU's CPU stall
5 This module parameter enables CPU stall detection by default, but
14 issues an RCU CPU stall warning. This time period is normally
32 print out additional per-CPU diagnostic information, including
33 information on scheduling-clock ticks and RCU's idle-CPU tracking.
40 giving an RCU CPU stall warning message. (This is a cpp
45 The CPU stall detector tries to make the offending CPU print its
47 However, if the offending CPU does not detect its own stall in
49 some other CPU will complain. This delay is normally set to
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Dtrace.txt68 This file has one line per CPU, or eight for this 8-CPU system.
71 o The number at the beginning of each line is the CPU number.
78 o "c" is the count of grace periods that this CPU believes have
80 quite a ways behind, for example, CPU 4 under "rcu_sched" above,
87 o "g" is the count of grace periods that this CPU believes have
89 may lag behind. If the "c" and "g" values are equal, this CPU
91 period that it is aware of, otherwise, the CPU believes that it
94 o "pq" indicates that this CPU has passed through a quiescent state
97 the CPU has passed through a quiescent state, either (1) this
98 CPU has not yet reported that fact, (2) some other CPU has not
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Drcubarrier.txt199 that RCU callbacks are never reordered once queued on one of the per-CPU
200 queues. His implementation queues an RCU callback on each of the per-CPU
209 4 /* Take cpucontrol mutex to protect against CPU hotplug */
221 6 and 7. Line 8 causes each CPU to invoke rcu_barrier_func(), which is
229 The rcu_barrier_func() runs on each CPU, where it invokes call_rcu()
243 Lines 3 and 4 locate RCU's internal per-CPU rcu_data structure,
248 the current CPU's queue.
260 Quick Quiz #2: What happens if CPU 0's rcu_barrier_func() executes
262 value one), but the other CPU's rcu_barrier_func() invocations
291 Quick Quiz #2: What happens if CPU 0's rcu_barrier_func() executes
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Drcu.txt32 Therefore, as soon as a CPU is seen passing through any of these
33 three states, we know that that CPU has exited any previous RCU
40 same effect, but require that the readers manipulate CPU-local
42 RCU read-side critical sections. SRCU also uses CPU-local
87 needed if you have CPU-bound realtime threads.
Dtorture.txt86 randomly selected CPU-hotplug operation. Defaults to
87 zero, which disables CPU hotplugging. In HOTPLUG_CPU=n
89 CPU-hotplug operations regardless of what value is
92 onoff_holdoff The number of seconds to wait until starting CPU-hotplug
109 stall_cpu The number of seconds that a CPU should be stalled while
114 is zero, which prevents rcutorture from stalling a CPU.
125 before stalling a CPU. Defaults to 10 seconds.
310 srcu-torture: per-CPU(idx=1): 0(0,1) 1(0,1) 2(0,0) 3(0,1)
312 This line shows the per-CPU counter state. The numbers in parentheses are
313 the values of the "old" and "current" counters for the corresponding CPU.
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/linux-4.1.27/Documentation/cpu-freq/
Dcpufreq-stats.txt2 CPU frequency and voltage scaling statistics in the Linux(TM) kernel
20 cpufreq-stats is a driver that provides CPU frequency statistics for each CPU.
23 in /sysfs (<sysfs root>/devices/system/cpu/cpuX/cpufreq/stats/) for each CPU.
27 that may be running on your CPU. So, it will work with any cpufreq_driver.
54 this CPU. The cat output will have "<frequency> <time>" pair in each line, which
55 will mean this CPU spent <time> usertime units of time at <frequency>. Output
70 This gives the total number of frequency transitions on this CPU. The cat
80 This will give a fine grained information about all the CPU frequency
104 CPU Frequency scaling --->
105 [*] CPU Frequency scaling
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Dgovernors.txt1 CPU frequency and voltage scaling code in the Linux(TM) kernel
18 the clock speed, the less power the CPU consumes.
40 cpu frequency scaling algorithms only offer the CPU to be set to one
60 CPU can be set to switch independently | CPU can only be set
87 The CPUfreq governor "performance" sets the CPU statically to the
95 The CPUfreq governor "powersave" sets the CPU statically to the
104 program running with UID "root", to set the CPU to a specific frequency
105 by making a sysfs file "scaling_setspeed" available in the CPU-device
112 The CPUfreq governor "ondemand" sets the CPU depending on the
113 current usage. To do this the CPU must have the capability to
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Dcpu-drivers.txt1 CPU frequency and voltage scaling code in the Linux(TM) kernel
17 the clock speed, the less power the CPU consumes.
24 1.2 Per-CPU Initialization
37 So, you just got a brand-new CPU / chipset with datasheets and want to
38 add cpufreq support for this CPU / chipset? Great. Here are some hints
46 function check whether this kernel runs on the right CPU and the right
54 cpufreq_driver.init - A pointer to the per-CPU initialization
65 cpufreq_driver.exit - A pointer to a per-CPU cleanup
69 cpufreq_driver.stop_cpu - A pointer to a per-CPU stop function
73 cpufreq_driver.resume - A pointer to a per-CPU resume function
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Duser-guide.txt1 CPU frequency and voltage scaling code in the Linux(TM) kernel
15 the clock speed, the less power the CPU consumes.
32 3. How to change the CPU cpufreq policy and/or speed
113 Some CPU frequency scaling-capable processor switch between various
139 3. How to change the CPU cpufreq policy and/or speed
148 (e.g. /sys/devices/system/cpu/cpu0/cpufreq/ for the first CPU).
154 cpuinfo_transition_latency The time it takes on this CPU to
167 used to set the frequency on this CPU
179 cpuinfo_cur_freq : Current frequency of the CPU as obtained from
181 the CPU actually runs at.
[all …]
Dcore.txt1 CPU frequency and voltage scaling code in the Linux(TM) kernel
16 the clock speed, the less power the CPU consumes.
77 policy, policy the new policy, cpu the number of the affected CPU; and
78 max_cpu_freq the maximum supported CPU frequency. This value is given
85 These are notified twice when the CPUfreq driver switches the CPU core
93 cpu - number of the affected CPU
Dindex.txt1 CPU frequency and voltage scaling code in the Linux(TM) kernel
15 the clock speed, the less power the CPU consumes.
36 There is a CPU frequency changing CVS commit and general list where
Dcpufreq-nforce2.txt4 This works better than on other platforms, because the FSB of the CPU
12 If not set, fid is calculated from the current CPU speed and the FSB.
Dboost.txt11 very moment, but only that the CPU _may_ raise the frequency at it's
65 CPU to boost at their discretion. Some implementations take external
75 This switch was instantiated in each CPU's cpufreq directory
77 Though the per CPU existence hints at a more fine grained control, the
79 which was simply reflected into each CPU's file. Writing a 0 or 1 into it
/linux-4.1.27/Documentation/arm/
Dcluster-pm-race-avoidance.txt4 This file documents the algorithm which is used to coordinate CPU and
47 Each cluster and CPU is assigned a state, as follows:
63 DOWN: The CPU or cluster is not coherent, and is either powered off or
66 COMING_UP: The CPU or cluster has committed to moving to the UP state.
70 UP: The CPU or cluster is active and coherent at the hardware
71 level. A CPU in this state is not necessarily being used
74 GOING_DOWN: The CPU or cluster has committed to moving to the DOWN
79 Each CPU has one of these states assigned to it at any point in time.
80 The CPU states are described in the "CPU state" section, below.
88 To help distinguish the CPU states from cluster states in this
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Dmemory.txt10 The ARM CPU is capable of addressing a maximum of 4GB virtual memory
29 ffff0000 ffff0fff CPU vector page.
30 The CPU vectors are mapped here if the
31 CPU supports vector relocation (control
39 DTCM mounted inside the CPU.
42 ITCM mounted inside the CPU.
75 00000000 00000fff CPU vector page / null pointer trap
Dvlocks.txt15 writes to a single memory location. To arbitrate, every CPU "votes for
21 in finite time, a CPU will only enter the election in the first place if
77 will contain only one value that won't change once every CPU has cleared
85 _last_ CPU which attempts to get the lock which will be most likely
89 to pick a unique winner, but it does not matter which CPU actually
175 to cache writebacks from one CPU clobbering values written by other
185 An offset is added to each CPU's ID for the purpose of setting this
186 variable, so that no CPU uses the value 0 for its ID.
DCCN.txt50 "non-CPU related" counters (yet?) so system-wide session ("-a")
52 per each CPU.
Dtcm.txt9 Due to being embedded inside the CPU The TCM has a
16 ARM CPU:s have special registers to read out status, physical
31 CPU so it is usually wise not to overlap any physical RAM with
55 the CPU and then we hang inside ITCM waiting for an
/linux-4.1.27/Documentation/power/
Dsuspend-and-cpuhotplug.txt1 Interaction of Suspend code (S3) with the CPU hotplug infrastructure
6 I. How does the regular CPU hotplug code differ from how the Suspend-to-RAM
12 interactions involving the freezer and CPU hotplug and also tries to explain
16 What happens when regular CPU hotplug and Suspend-to-RAM race with each other
61 Common | before taking down the CPU |
108 Regular CPU hotplug call path
130 Common | before taking down the CPU
140 regular CPU hotplug]
145 regular CPU hotplug and the suspend code path converge at the _cpu_down() and
147 in that during regular CPU hotplug, 0 is passed for the 'tasks_frozen'
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/linux-4.1.27/Documentation/ia64/
DIRQ-redir.txt11 IRQ target is one particular CPU and cannot be a mask of several
17 The target CPU has to be specified as a hexadecimal CPU mask. The
18 first non-zero bit is the selected CPU. This format has been kept for
22 interrupts to CPU #3 (logical CPU number) (2^3=0x08):
25 Set the default route for IRQ number 41 to CPU 6 in lowest priority
31 gives the target CPU mask for the specified interrupt vector. If the CPU
41 IO-SAPIC interrupts are initialized with CPU#0 as their default target
48 - maximal if the CPU is going to be switched off.
49 The IRQ is routed to the CPU with lowest XTP register value, the
50 search begins at the default CPU. Therefore most of the interrupts
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Dfsys.txt24 CPU registers.
29 state remains in the CPU registers and some kernel state may
36 - CPU registers may contain a mixture of user-level and kernel-level
68 pointer belongs to. user_mode() returns TRUE if the CPU state pointed
72 TRUE if the CPU state pointed to by "regs" was executing in fsys-mode.
137 o Fsyscall-handlers need to be careful when accessing per-CPU variables:
139 execution may be pre-empted and resumed on another CPU at any given
185 to ensure the CPU is in little-endian mode before the first
216 taken _after_ restoring the privilege level, the CPU has already
/linux-4.1.27/Documentation/networking/
Dscaling.txt54 for each CPU if the device supports enough queues, or otherwise at least
69 this to notify a CPU when new packets arrive on the given queue. The
71 that can route each interrupt to a particular CPU. The active mapping
73 an IRQ may be handled on any CPU. Because a non-negligible part of packet
88 receive queue overflows due to a saturated CPU, because in default
94 a separate CPU. For interrupt handling, HT has shown no benefit in
95 initial tests, so limit the number of queues to the number of CPU cores
104 Whereas RSS selects the queue and hence CPU that will run the hardware
105 interrupt handler, RPS selects the CPU to perform protocol processing
107 on the desired CPU’s backlog queue and waking up the CPU for processing.
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Dpktgen.txt8 running, pktgen creates a thread for each CPU with affinity to that CPU.
12 On a dual CPU:
36 than the CPU's L1/L2 cache, 2) because it allows more queueing in the
201 pktgen.conf-1-1 # 1 CPU 1 dev
202 pktgen.conf-1-2 # 1 CPU 2 dev
203 pktgen.conf-2-1 # 2 CPU's 1 dev
204 pktgen.conf-2-2 # 2 CPU's 2 dev
205 pktgen.conf-1-1-rdos # 1 CPU 1 dev w. route DoS
206 pktgen.conf-1-1-ip6 # 1 CPU 1 dev ipv6
207 pktgen.conf-1-1-ip6-rdos # 1 CPU 1 dev ipv6 w. route DoS
[all …]
Dswitchdev.txt11 | SOME switch chip | | CPU |
22 and CPU. NIC0 and NIC1 drivers are not aware of a switch presence. They are
30 | SOME switch chip | | CPU |
/linux-4.1.27/drivers/cpufreq/
DKconfig1 menu "CPU Frequency scaling"
4 bool "CPU Frequency scaling"
7 CPU Frequency scaling allows you to change the clock speed of
9 the lower the CPU clock speed, the less power the CPU consumes.
11 Note that this driver doesn't automatically change the CPU
29 tristate "CPU frequency translation statistics"
32 This driver exports CPU frequency statistics information through sysfs
41 bool "CPU frequency translation statistics details"
44 This will show detail CPU frequency translation table in sysfs file
63 the CPU.
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DKconfig.arm2 # ARM CPU Frequency scaling drivers
189 CPU Frequency scaling support for S3C2410
197 CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
200 bool "S3C2416 CPU Frequency scaling support"
207 core voltage of the CPU.
215 Enable CPU voltage scaling when entering the dvs mode.
222 bool "S3C2440/S3C2442 CPU Frequency scaling support"
227 CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
DKconfig.powerpc50 tristate "CPU frequency scaling for IBM POWERNV platform"
54 This adds support for CPU frequency switching on IBM POWERNV
/linux-4.1.27/drivers/cpuidle/
DKconfig.arm2 # ARM CPU Idle drivers
5 bool "Generic ARM/ARM64 CPU idle Driver"
11 initialized by calling the CPU operations init idle hook
22 Select this option to enable CPU idle driver for big.LITTLE based
25 multiple CPU idle drivers infrastructure.
28 bool "CPU Idle Driver for CLPS711X processors"
34 bool "CPU Idle Driver for Calxeda processors"
41 bool "CPU Idle Driver for Marvell Kirkwood SoCs"
44 This adds the CPU Idle driver for Marvell Kirkwood SoCs.
47 bool "CPU Idle Driver for Xilinx Zynq processors"
[all …]
DKconfig1 menu "CPU Idle"
4 bool "CPU idle PM support"
9 CPU idle is a generic framework for supporting software-controlled
31 menu "ARM CPU Idle Drivers"
36 menu "MIPS CPU Idle Drivers"
41 menu "POWERPC CPU Idle Drivers"
DKconfig.mips2 # MIPS CPU Idle Drivers
5 bool "CPU Idle driver for MIPS CPS platforms"
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
Dbf548.h85 # define CPU "BF542" macro
88 # define CPU "BF544" macro
91 # define CPU "BF547" macro
94 # define CPU "BF548" macro
97 # define CPU "BF549" macro
101 #ifndef CPU
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
Dbf527.h209 #define CPU "BF527" macro
213 #define CPU "BF526" macro
217 #define CPU "BF525" macro
221 #define CPU "BF524" macro
225 #define CPU "BF523" macro
229 #define CPU "BF522" macro
233 #ifndef CPU
/linux-4.1.27/Documentation/cgroups/
Dcpuacct.txt1 CPU Accounting Controller
4 The CPU accounting controller is used to group tasks using cgroups and
5 account the CPU usage of these groups of tasks.
7 The CPU accounting controller supports multi-hierarchy groups. An accounting
8 group accumulates the CPU usage of all of its child groups and the tasks
18 /sys/fs/cgroup/cpuacct.usage gives the CPU time (in nanoseconds) obtained
19 by this group which is essentially the CPU time obtained by all the tasks
29 process (bash) into it. CPU time consumed by this bash and its children
34 CPU time obtained by the cgroup into user and system times. Currently
Dcpusets.txt44 Cpusets constrain the CPU and Memory placement of tasks to only
54 include CPUs in its CPU affinity mask, and using the mbind(2) and
58 schedule a task on a CPU that is not allowed in its cpus_allowed
79 the available CPU and Memory resources amongst the requesting tasks.
102 leverages existing CPU and Memory Placement facilities in the Linux
130 of the parents CPU and Memory Node resources.
220 cpu_online_mask using a CPU hotplug notifier, and the mems file
377 tasks. If one CPU is underutilized, kernel code running on that
378 CPU will look for tasks on other more overloaded CPUs and move those
413 from any CPU in that cpuset to any other.
[all …]
D00-INDEX8 - CPU Accounting Controller; account CPU usage for groups of tasks.
/linux-4.1.27/Documentation/devicetree/bindings/nios2/
Dnios2.txt12 - reg: Contains CPU index.
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
26 - altr,has-mul: Specifies CPU hardware multipy support, should be 1.
27 - altr,has-mmu: Specifies CPU support MMU support, should be 1.
28 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
29 - altr,reset-addr: Specifies CPU reset address
30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
31 - altr,exception-addr: Specifies CPU exception address
34 - altr,has-div: Specifies CPU hardware divide support
/linux-4.1.27/Documentation/arm/sunxi/
Dclocks.txt21 \_ CPU Mux
23 [CPU]
25 When you are about to suspend, you switch the CPU Mux to the 32kHz
32 CPU Mux _/
34 [CPU]
42 CPU Mux _/
44 [CPU]
/linux-4.1.27/Documentation/devicetree/bindings/regmap/
Dregmap.txt3 The endianness mode of CPU & Device scenarios:
15 meaning that the CPU and the Device are in the same endianness mode,
19 Scenario 1 : CPU in LE mode & device in LE mode.
26 Scenario 2 : CPU in LE mode & device in BE mode.
34 Scenario 3 : CPU in BE mode & device in BE mode.
41 Scenario 4 : CPU in BE mode & device in LE mode.
/linux-4.1.27/arch/mn10300/proc-mn2ws0050/include/proc/
Dsmp-regs.h31 #define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ argument
32 ((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16)
33 #define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ argument
34 (((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8)
/linux-4.1.27/Documentation/x86/x86_64/
Dcpu-hotplug-spec1 Firmware support for CPU hotplug under Linux/x86-64
4 Linux/x86-64 supports CPU hotplug now. For various reasons Linux wants to
9 In ACPI each CPU needs an LAPIC object in the MADT table (5.2.11.5 in the
13 For CPU hotplug Linux/x86-64 expects now that any possible future hotpluggable
14 CPU is already available in the MADT. If the CPU is not available yet
Dmachinecheck5 by the CPU. Uncorrected errors typically cause a machine check
10 of the banks and subevent is CPU specific.
18 Each CPU has a directory in /sys/devices/system/machinecheck/machinecheckN
19 (N = CPU number)
34 The following entries appear for each CPU, but they are truly shared
65 Note this only makes a difference if the CPU allows recovery
Dkernel-stacks12 associated with each CPU. These stacks are only used while the kernel
13 is in control on that CPU; when a CPU returns to user space the
14 specialized stacks contain no useful data. The main CPU stacks are:
28 per CPU interrupt nest counter. This is needed because x86-64 "IST"
35 (IST). There can be up to 7 IST entries per CPU. The IST code is an
63 This allows the CPU to recover from invalid stack segments. Rarely
/linux-4.1.27/tools/power/cpupower/po/
Dit.po103 msgid "\t -t: show CPU topology/hierarchy\n"
108 msgid "\t -l: list available CPU sleep monitors (for use with -m)\n"
113 msgid "\t -m: show specific CPU sleep monitors only (in same order)\n"
230 msgstr "Impossibile determinare il numero di CPU (%s: %s), assumo sia 1\n"
235 " minimum CPU frequency - maximum CPU frequency - governor\n"
237 " frequenza minima CPU - frequenza massima CPU - gestore\n"
241 msgid "Error while evaluating Boost Capabilities on CPU %d -- are you root?\n"
294 msgid " no or unknown cpufreq driver is active on this CPU\n"
295 msgstr " nessun modulo o modulo cpufreq sconosciuto per questa CPU\n"
305 msgstr " CPU che operano alla stessa frequenza hardware: "
[all …]
Dcs.po106 msgid "\t -t: show CPU topology/hierarchy\n"
111 msgid "\t -l: list available CPU sleep monitors (for use with -m)\n"
116 msgid "\t -m: show specific CPU sleep monitors only (in same order)\n"
235 msgstr "Nelze zjistit počet CPU (%s: %s), předpokládá se 1.\n"
240 " minimum CPU frequency - maximum CPU frequency - governor\n"
242 " minimální frekvence CPU - maximální frekvence CPU - regulátor\n"
246 msgid "Error while evaluating Boost Capabilities on CPU %d -- are you root?\n"
299 msgid " no or unknown cpufreq driver is active on this CPU\n"
300 msgstr " pro tento CPU není aktivní žádný známý ovladač cpufreq\n"
310 msgstr " CPU, které musí měnit frekvenci zároveň: "
[all …]
Dfr.po103 msgid "\t -t: show CPU topology/hierarchy\n"
108 msgid "\t -l: list available CPU sleep monitors (for use with -m)\n"
113 msgid "\t -m: show specific CPU sleep monitors only (in same order)\n"
235 " minimum CPU frequency - maximum CPU frequency - governor\n"
237 " Fr�quence CPU minimale - Fr�quence CPU maximale - r�gulateur\n"
241 msgid "Error while evaluating Boost Capabilities on CPU %d -- are you root?\n"
294 msgid " no or unknown cpufreq driver is active on this CPU\n"
295 msgstr " pas de pilotes cpufreq reconnu pour ce CPU\n"
353 msgid " current CPU frequency is "
354 msgstr " la fr�quence actuelle de ce CPU est "
[all …]
Dpt.po101 msgid "\t -t: show CPU topology/hierarchy\n"
106 msgid "\t -l: list available CPU sleep monitors (for use with -m)\n"
111 msgid "\t -m: show specific CPU sleep monitors only (in same order)\n"
233 " minimum CPU frequency - maximum CPU frequency - governor\n"
235 " frequência mínina do CPU - frequência máxima do CPU - "
240 msgid "Error while evaluating Boost Capabilities on CPU %d -- are you root?\n"
293 msgid " no or unknown cpufreq driver is active on this CPU\n"
294 msgstr " nenhum ou driver do cpufreq deconhecido está ativo nesse CPU\n"
352 msgid " current CPU frequency is "
353 msgstr " frequência atual do CPU é "
[all …]
Dde.po103 msgid "\t -t: show CPU topology/hierarchy\n"
108 msgid "\t -l: list available CPU sleep monitors (for use with -m)\n"
113 msgid "\t -m: show specific CPU sleep monitors only (in same order)\n"
236 " minimum CPU frequency - maximum CPU frequency - governor\n"
238 " minimale CPU-Taktfreq. - maximale CPU-Taktfreq. - Regler \n"
242 msgid "Error while evaluating Boost Capabilities on CPU %d -- are you root?\n"
295 msgid " no or unknown cpufreq driver is active on this CPU\n"
355 msgid " current CPU frequency is "
389 " -f, --freq Get frequency the CPU currently runs at, according\n"
392 " -f, --freq Findet die momentane CPU-Taktfrquenz heraus (nach\n"
[all …]
/linux-4.1.27/Documentation/thermal/
Dintel_powerclamp.txt36 Currently, P-states, T-states (clock modulation), and CPU offlining
37 are used for CPU throttling.
42 idle injection across all online CPU threads was introduced. The goal
47 shown over taking the CPU offline or modulating the CPU clock.
75 each online CPU.
78 clamping actions of controlled duty ratio and duration. Each per-CPU
81 effect. Threads are also bound to the CPU such that they cannot be
82 migrated, unless the CPU is taken offline. In this case, threads
91 for a given "duration", then relinquishes the CPU to other tasks,
113 Only one CPU is allowed to collect statistics and update global
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/mips/img/
Dpistachio.txt8 CPU nodes:
13 A CPU sub-node is also required for at least CPU 0. Since the topology may
18 - reg: CPU number.
19 - clocks: Must include the CPU clock. See ../../clock/clock-bindings.txt for
/linux-4.1.27/Documentation/zh_CN/arm/
DBooting154 - CPU 寄存器配置
160 - CPU 模式
162 CPU 必须处于 SVC 模式。(对于 Angel 调试有特例存在)
171 对于支持 ARM 指令集的 CPU，跳入内核入口时必须处在 ARM 状态，即使
174 对于仅支持 Thumb 指令集的 CPU，比如 Cortex-M 系列的 CPU，跳入
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
Dbf537.h92 #define CPU "BF537" macro
96 #define CPU "BF536" macro
100 #define CPU "BF534" macro
104 #ifndef CPU
/linux-4.1.27/Documentation/timers/
DNO_HZ.txt37 that use short bursts of CPU, where there are very frequent idle
41 will frequently be multiple runnable tasks per CPU. In these cases,
64 If a CPU is idle, there is little point in sending it a scheduling-clock
66 is to force a busy CPU to shift its attention among multiple duties,
67 and an idle CPU has no duties to shift its attention among.
75 1,500 OS instances might find that half of its CPU time was consumed by
90 An idle CPU that is not receiving scheduling-clock interrupts is said to
102 If a CPU has only one runnable task, there is little point in sending it
113 computationally intensive short-iteration workloads: If any CPU is
115 wait idle while the delayed CPU finishes. Thus, the delay is multiplied
[all …]
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
Dbf518.h194 #define CPU "BF518" macro
198 #define CPU "BF516" macro
202 #define CPU "BF514" macro
206 #define CPU "BF512" macro
210 #ifndef CPU
/linux-4.1.27/Documentation/scheduler/
Dsched-domains.txt1 Each CPU has a "base" scheduling domain (struct sched_domain). The domain
3 MUST be NULL terminated, and domain structures should be per-CPU as they are
8 be relaxed if the need arises), and a base domain for CPU i MUST span at least
9 i. The top domain for each CPU will generally span all CPUs in the system
15 Each scheduling domain must have one or more CPU groups (struct sched_group)
20 contain the CPU to which the domain belongs. Groups may be shared among
28 In kernel/sched/core.c, trigger_load_balance() is run periodically on each CPU
34 The latter function takes two arguments: the current CPU and whether it was idle
36 our CPU is on, starting from its base domain and going up the ->parent chain.
45 CPU's runqueue and the newly found busiest one and starts moving tasks from it
[all …]
Dsched-bwc.txt4 [ This document only discusses CPU bandwidth control for SCHED_NORMAL.
8 specification of the maximum CPU bandwidth available to a group or hierarchy.
12 "quota" microseconds of CPU time. When the CPU bandwidth consumption of a
53 For efficiency run-time is transferred between the global pool and CPU local
95 1. Limit a group to 1 CPU worth of runtime.
98 1 CPU worth of runtime every 250ms.
103 2. Limit a group to 2 CPUs worth of runtime on a multi-CPU machine.
113 3. Limit a group to 20% of 1 CPU.
115 With 50ms period, 10ms quota will be equivalent to 20% of 1 CPU.
Dsched-nice-design.txt5 pestered us to make nice +19 tasks use up much less CPU time.
40 HZ=1000 it caused 1 jiffy to be 1 msec, which meant 0.1% CPU usage which
42 a CPU utilization, but because it causes too frequent (once per
48 right minimal granularity - and this translates to 5% CPU utilization.
51 terms of CPU utilization, we only got complaints about it (still) being
74 and another task with +2, the CPU split between the two tasks would
76 CPU split was different than if it was at +5 or +10.
95 the new scheduler makes nice(1) have the same CPU utilization effect on
97 scheduler, running a nice +10 and a nice 11 task has the same CPU
99 task. (one will get 55% of the CPU, the other 45%.) That is why nice
Dsched-design-CFS.txt14 an "ideal, precise multi-tasking CPU" on real hardware.
16 "Ideal multi-tasking CPU" is a (non-existent :-)) CPU that has 100% physical
24 multi-tasking CPU described above. In practice, the virtual runtime of a task
33 timestamp and measure the "expected CPU time" a task should have gotten.
37 would ever get "out of balance" from the "ideal" share of CPU time. ]
42 up CPU time between runnable tasks as close to "ideal multitasking hardware" as
72 to become the "leftmost task" and thus get on the CPU within a deterministic
76 schedules (or a scheduler tick happens) the task's CPU usage is "accounted
77 for": the (small) time it just spent using the physical CPU is added to
202 fair CPU time to each task. Sometimes, it may be desirable to group tasks and
[all …]
Dsched-rt-group.txt43 the amount of bandwidth (eg. CPU time) being constant. In order to schedule
45 of the CPU time available. Without a minimum guarantee a realtime group can
52 CPU time is divided by means of specifying how much time can be spent running
62 have to play some music and respond to input, leaving it with around 80% CPU
68 needs only about 3% CPU time to do so, it can do with a 0.03 * 0.005s =
72 The remaining CPU time will be used for user input and other tasks. Because
73 realtime tasks have explicitly allocated the CPU time they need to perform
90 The scheduling period that is equivalent to 100% CPU bandwidth
119 Realtime group scheduling means you have to assign a portion of total CPU
130 CPU bandwidth to task groups.
[all …]
Dsched-arch.txt1 CPU Scheduler implementation hints for architecture specific code
20 CPU idle
52 a low CPU priority.
/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
Dbf533.h122 #define CPU "BF533" macro
126 #define CPU "BF532" macro
130 #define CPU "BF531" macro
134 #ifndef CPU
/linux-4.1.27/Documentation/fault-injection/
Dnotifier-error-inject.txt9 * CPU notifier
14 CPU notifier error injection module
16 This feature can be used to test the error handling of the CPU notifiers by
17 injecting artificial errors to CPU notifier chain callbacks.
23 Possible CPU notifier events to be failed are:
30 Example1: Inject CPU offline error (-1 == -EPERM)
37 Example2: inject CPU online error (-2 == -ENOENT)
93 for CPU and memory notifiers.
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-devices-system-cpu5 A collection of both global and individual CPU attributes
7 Individual CPU attributes are contained in subdirectories
8 named by the kernel's logical CPU number, e.g.:
19 Description: CPU topology files that describe kernel limits related to
44 Description: Dynamic addition and removal of CPU's. This is not hotplug
45 removal, this is meant complete removal/addition of the CPU
48 probe: writes to this file will dynamically add a CPU to the
49 system. Information written to the file to add CPU's is
52 release: writes to this file dynamically remove a CPU from
53 the system. Information writtento the file to remove CPU's
[all …]
Dsysfs-class-net-queues6 Mask of the CPU(s) currently enabled to participate into the
9 of available CPU(s) in the system.
40 Mask of the CPU(s) currently enabled to participate into the
43 number of available CPU(s) in the system.
Dsysfs-kernel-uids10 shares, then they will get equal CPU bandwidth. Another
12 B has shares = 2048, User B will get twice the CPU
Dsysfs-driver-sunxi-sid6 and A20 CPU's. The earlier A1x series of SoCs exports 16 bytes,
22 Allwinner's A-series of CPU's.
/linux-4.1.27/Documentation/hwmon/
Dk8temp24 There can be up to four temperature sensors inside single CPU. The driver
36 1 degree C. It is expected that future CPU will have better resolution. The
41 This temperature is defined as temperature between heat-spreader and CPU
42 case, so the internal CPU temperature supplied by this driver can be higher.
46 For newer revisions of CPU (rev F, socket AM2) there is a mathematically
54 70 degrees C. The rule of the thumb -> CPU temperature should not cross
Dsmsc47m19225 as well as CPU voltage VID input.
41 bit 4 of the encoded CPU voltage. This means that you either get
42 a +12V voltage measurement or a 5 bit CPU VID, but not both.
56 in1_input - CPU voltage input (nominal 2.25V)
75 typically be wired to the diode inside the CPU)
98 cpu0_vid - CPU voltage as received from the CPU
100 vrm - CPU VID standard used for decoding CPU voltage
Dnct790418 internal temperature sensor, Intel PECI and AMD SB-TSI CPU temperature
35 temp[2-9]_input CPU temperatures (1/1000 degree,
/linux-4.1.27/Documentation/frv/
Dconfiguring.txt20 (*) "CPU"
25 CPU boards, and with the MB93093 PDK board.
80 Default configuration for the MB93091-VDK with both CPU board and
86 Default configuration for the MB93091-VDK with CPU board,
98 Default configuration for the MB93091-VDK with only CB70 CPU board
104 Default configuration for the MB93091-VDK with both CB451 CPU board and
109 Default configuration for the MB93091-VDK with CB451 CPU board, DAV
115 Default configuration for the MB93091-VDK with CB451 CPU board, DAV
121 Default configuration for the MB93091-VDK with only CB451 CPU board
Dclock.txt22 On the boards with FR405 CPU (i.e. CB60 and CB70), the 'cmode' file is also
23 writable, allowing the CPU core speed (and other clock speeds) to be
34 CPU-Series: fr400
35 CPU-Core: fr405, gr0-31, BE, CCCR
36 CPU: mb93405
Dfeatures.txt13 (*) CPU support
18 In normal (MMU) Linux mode, only the FR451 CPU will work as that is the
19 only one with a suitably featured CPU.
79 0xF1000000 - 0xF1FFFFFF CS7# [CB70/CB451] CPU-card PCMCIA port space
81 0xFC100000 - 0xFC1FFFFF CS6# [CB70/CB451] CPU-card DM9000 NIC space
84 0xFD000000 - 0xFDFFFFFF CS4# [CB70/CB451] CPU-card extra flash space
85 0xFE000000 - 0xFEFFFFFF Internal CPU peripherals
101 three quarters are left unoccupied so that an FR-V CPU with an MMU can use
182 CPU's own multiplexor, and those on off-CPU peripherals.
189 but the CPU sees it in big-endian form. The macros in asm/io.h try to get
[all …]
DREADME.txt5 This directory contains documentation for the Fujitsu FR-V CPU architecture
46 A description of the CPU clock scaling interface.
/linux-4.1.27/arch/arm/common/
Dmcpm_head.S60 mla r4, r3, r10, r9 @ r4 = canonical CPU index
92 @ Signal that this CPU is coming UP:
99 @ state, because there is at least one active CPU (this CPU).
127 @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
180 @ If a platform-specific CPU setup hook is needed, it is
184 mov r0, #0 @ first (CPU) affinity level
188 @ Mark the CPU as up:
196 ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
/linux-4.1.27/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-cpucfg.txt1 Freescale Vybrid Miscellaneous System Control - CPU Configuration
4 block of registers which contains CPU configuration information.
8 - reg: the register range of the MSCM CPU configuration registers
Dfsl,vf610-mscm-ir.txt13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
14 to get the current CPU ID
22 the CPU the device tree is intended to be used on. This
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Drenesas,rsrc-card.txt15 - cpu : CPU sub-node
20 - format : CPU/CODEC common audio format.
33 Required CPU/CODEC subnodes properties:
35 - sound-dai : phandle and port of CPU/CODEC
37 Optional CPU/CODEC subnodes properties:
Dsimple-card.txt28 properties and the CPU and CODEC
42 - cpu : CPU sub-node
47 - format : CPU/CODEC common audio format.
66 Required CPU/CODEC subnodes properties:
68 - sound-dai : phandle and port of CPU/CODEC
70 Optional CPU/CODEC subnodes properties:
/linux-4.1.27/Documentation/cpuidle/
Ddriver.txt3 Supporting multiple CPU idle levels in kernel
11 architecture/platform dependent part of CPU idle states. Driver
13 has mechanisms in place to support actual entry-exit into CPU idle states.
15 cpuidle driver initializes the cpuidle_device structure for each CPU device
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
Dbf538.h91 #define CPU "BF538" macro
95 #define CPU "BF539" macro
99 #ifndef CPU
/linux-4.1.27/Documentation/sound/alsa/soc/
Dclocking.txt13 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
16 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
25 between the codec and CPU.
43 This relationship depends on the codec or SoC CPU in particular. In general
48 audio clocks as it usually gives more accurate sample rates than the CPU.
Dmachine.txt31 /* CPU <--> Codec DAI links */
52 The machine DAI configuration glues all the codec and CPU DAIs together. It can
59 /* corgi digital audio interface glue - connects codec <--> CPU */
/linux-4.1.27/Documentation/devicetree/bindings/
Dcommon-properties.txt19 register endianness based on the CPU's configured endianness.
30 Scenario 1 : CPU in LE mode & device in LE mode.
38 Scenario 2 : CPU in LE mode & device in BE mode.
46 Scenario 3 : CPU in BE mode & device in BE mode.
54 Scenario 4 : CPU in BE mode & device in LE mode.
/linux-4.1.27/arch/x86/
DKconfig.cpu1 # Put here option for CPU selection and depending optimization
11 This is the processor type of your CPU. This information is
13 that can run on all supported x86 CPU types (albeit not
193 stores for this CPU, which can increase performance of some
221 treat this chip as a generic 586. Whilst the CPU is 686 class,
226 incarnations of the CPU.
233 of SSE and tells gcc to treat the CPU as a 686.
241 shift and tells gcc to treat the CPU as a 686.
259 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
276 Generic x86-64 CPU.
[all …]
/linux-4.1.27/Documentation/trace/
Devents-kmem.txt9 o Per-CPU Allocator Activity
48 the per-CPU allocator (high performance) or the buddy allocator.
66 4. Per-CPU Allocator Activity
75 When a per-CPU list is empty or pages of the wrong type are allocated,
76 the zone->lock will be taken once and the per-CPU list refilled. The event
80 When the per-CPU list is too full, a number of pages are freed, each one
85 consecutively imply the zone->lock being taken once. Large amounts of per-CPU
87 is being concentrated in one place. It could also indicate that the per-CPU
88 lists should be a larger size. Finally, large amounts of refills on one CPU
91 can be allocated and freed on the same CPU through some algorithm change.
Dftrace.txt147 This sets or displays the number of kilobytes each CPU
149 for each CPU. The displayed number is the size of the
150 CPU buffer and not total size of all buffers. The
416 buffer for each CPU to allow writes to be done atomically,
420 specific CPU. (here cpu0).
425 the data specific for the CPU. If written to, it only clears
426 the specific CPU buffer.
432 for the CPU.
449 snapshot the current CPU (if supported). It only displays
450 the content of the snapshot for a given CPU, and if
[all …]
Devents-nmi.txt12 NMI handlers are hogging large amounts of CPU time. The kernel
28 really hogging a lot of CPU time, like a millisecond at a time.
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dal,alpine.txt18 * CPU node:
56 * Alpine CPU resume registers
58 The CPU resume register are used to define required resume address after
74 The System-Fabric Service Registers allow various operation on CPU and
Dcoherency-fabric.txt22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
Darmada-cpu-reset.txt1 Marvell Armada CPU reset controller
9 datasheet for the CPU reset registers
Didle-states.txt11 wfi to power gating) according to OS PM policies. The CPU states representing
17 power states an ARM CPU can be put into are identified by the following list:
25 The power states described in the SBSA document define the basic CPU states on
46 The following diagram depicts the CPU execution phases and related timing
59 Diagram 1: CPU idle state execution phases
61 EXEC: Normal CPU execution.
66 (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
76 EXIT: Period during which the CPU is brought back to operational
86 CPU being able to execute normal code again. If not specified, this is assumed
91 An idle CPU requires the expected min-residency time to select the most
[all …]
Dcpus.txt9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
49 scheme for processors that do not have a HW CPU
67 Description: Describes a CPU in an ARM based system
86 bits [11:0] in CPU ID register.
91 required and matches the CPU MPIDR[23:0] register
216 Definition: Specifies the SAW[1] node associated with this CPU.
223 Definition: Specifies the ACC[2] node associated with this CPU.
/linux-4.1.27/arch/arm/mach-tegra/
DKconfig33 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
44 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
55 ARM CortexA15MP CPU
65 ARM CortexA15MP CPU
Dreset-handler.S66 @ & ext flags for CPU power mgnt
155 and r10, r10, #0x3 @ R10 = CPU number
157 mov r11, r11, lsl r10 @ R11 = CPU mask
164 bleq __die @ CPU not present (to OS)
265 wfi @ CPU should be power gated here
/linux-4.1.27/tools/perf/tests/
Dhists_output.c118 #define CPU(he) (he->cpu) macro
266 CPU(he) == 1 && PID(he) == 100 && he->stat.period == 300); in test2()
271 CPU(he) == 0 && PID(he) == 100 && he->stat.period == 100); in test2()
502 CPU(he) == 0 && PID(he) == 100 && in test5()
509 CPU(he) == 2 && PID(he) == 200 && in test5()
516 CPU(he) == 1 && PID(he) == 300 && in test5()
523 CPU(he) == 0 && PID(he) == 300 && in test5()
530 CPU(he) == 3 && PID(he) == 300 && in test5()
537 CPU(he) == 1 && PID(he) == 100 && in test5()
544 CPU(he) == 2 && PID(he) == 100 && in test5()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/arm/msm/
Dqcom,kpss-acc.txt3 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
4 There is one ACC register region per CPU within the KPSS remapped region as
6 with the CPU accessing the region.
/linux-4.1.27/tools/perf/Documentation/
Dperf-sched.txt29 threads can then replay the timings (CPU runtime and sleep patterns)
36 are running on a CPU. A '*' denotes the CPU that had the event, and
37 a dot signals an idle CPU.
Dperf-timechart.txt19 and CPU events (task switches, running times, CPU power states, etc),
46 Only output the CPU power section of the diagram
/linux-4.1.27/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.txt5 modes. It provides power-gating controllers for SoC and CPU power-islands.
29 0 (LP0): CPU + Core voltage off and DRAM in self-refresh
30 1 (LP1): CPU voltage off and DRAM in self-refresh
31 2 (LP2): CPU voltage off
34 - nvidia,combined-power-req : Boolean, combined power request for CPU & Core
35 - nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
39 - nvidia,cpu-pwr-good-time : CPU power good time in uS.
40 - nvidia,cpu-pwr-off-time : CPU power off time in uS.
/linux-4.1.27/Documentation/arm/Samsung-S3C24XX/
DCPUfreq.txt13 There are two forms of the driver depending on the specific CPU and
24 The code core manages the CPU specific drivers, any data that they
26 system. Each CPU registers a driver to control the PLL, clock dividers
34 CPU support
37 The support for each CPU depends on the facilities provided by the
DSuspend.txt11 at the relevant CPU datasheet from Samsung.
30 The S3C2410 user manual defines the process of sending the CPU to
119 Note, the time to calculate the CRC is dependent on the CPU speed
/linux-4.1.27/arch/sh/
DKconfig316 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
322 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
329 if you have a 100 Mhz SH-3 HD6417708R CPU.
335 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
342 Select SH7710 if you have a SH3-DSP SH7710 CPU.
349 Select SH7712 if you have a SH3-DSP SH7712 CPU.
360 Select SH7720 if you have a SH3-DSP SH7720 CPU.
369 Select SH7721 if you have a SH3-DSP SH7721 CPU.
377 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
398 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
[all …]
/linux-4.1.27/Documentation/mn10300/
Dcompartmentalisation.txt9 The "processor level" is a CPU core plus the other on-silicon
13 way to the CPU level:
17 Support for the AM33v2 CPU core.
29 to the CPU level; not only that, but specific sources may also be
/linux-4.1.27/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,bcm11351-cpu-method.txt1 Broadcom Kona Family CPU Enable Method
14 code release a secondary CPU. The value written to the register is
15 formed by encoding the target CPU id into the low bits of the
Dbrcm,brcmstb.txt58 of certain CPU power-on registers.
62 o offset to the base CPU power zone register
63 o offset to the base CPU reset register
66 A phandle pointing to the syscon node which describes the CPU boot
/linux-4.1.27/tools/power/cpupower/bench/
DREADME-BENCH9 - Identify average reaction time of a governor to CPU load changes
34 You can specify load (100% CPU load) and sleep (0% CPU load) times in us which
55 First it is calibrated how long a specific CPU intensive calculation
69 100% CPU load (load) | 0 % CPU load (sleep) | round
113 -c, --cpu=<unsigned int> CPU Number to use, starting at 0
/linux-4.1.27/arch/frv/
DKconfig157 prompt "CPU Caching mode"
178 Note that not all CPUs support Write-Behind caching. If the CPU on
196 menu "CPU core support"
210 This enables support for the FR405 CPU
216 This enables support for the FR451 CPU
224 optimise for the FR451 CPU
231 This enables support for the FR555 CPU
239 optimise for the FR555 CPU
253 bool "MB93091 CPU board with or without motherboard"
268 Select this option if the MB93091 CPU board is going to be used with
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/c6x/
Dclocks.txt24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
/linux-4.1.27/Documentation/ABI/stable/
Dsysfs-devices-system-cpu9 all per-CPU defaults at the same time.
17 a CPU.
22 on any CPU where it executes (overriding the value described
/linux-4.1.27/kernel/time/
DKconfig76 rate, even when the CPU doesn't need it.
93 # We need at least one periodic CPU for timekeeping
106 the CPU is running tasks. Typically this requires running a single
107 task on the CPU. Chances for running tickless are maximized when
122 bool "Full dynticks system on all CPUs by default (except CPU 0)"
128 Note the boot CPU will still be kept outside the range to
136 At least one CPU must keep the scheduling-clock tick running for
137 timekeeping purposes whenever there is a non-idle CPU, where
142 underlying support simply ensures that there is always a CPU
/linux-4.1.27/arch/m68k/
DKconfig.cpu4 prompt "CPU family support"
21 bool "Classic M68K CPU family support"
24 bool "Coldfire CPU family support"
44 The Freescale (was Motorola) 68000 CPU is the first generation of
45 the well known M68K family of processors. The CPU core as well as
46 being available as a stand alone CPU was also used in many
55 The Freescale (was then Motorola) CPU32 is a CPU core that is
334 This gives you access to some advanced options for the CPU. The
433 Define the CPU clock frequency in use. This is the core clock
439 specific to the exact CPU that you are using.
[all …]
/linux-4.1.27/tools/perf/
Ddesign.txt10 thus be used to profile the code that runs on that CPU.
13 hardware capabilities. It provides per task and per CPU counters, counter
115 If a CPU is not able to count the selected event, then the system call
118 More hw_event_types are supported as well, but they are CPU-specific
206 on the CPU if at all possible. It only applies to hardware counters
208 CPU (e.g. because there are not enough hardware counters or because of
214 is on the CPU, it should be the only group using the CPU's counters.
217 advanced features of the CPU's Performance Monitor Unit (PMU) that are
223 CPU is in user, kernel and/or hypervisor mode.
244 The 'cpu' parameter allows a counter to be made specific to a CPU:
[all …]
/linux-4.1.27/Documentation/powerpc/
Dcpu_features.txt8 Early in the boot process the ppc32 kernel detects the current CPU type and
10 split instruction and data caches, and if the CPU supports the DOZE and NAP
26 performance penalty but still allow for runtime (rather than compile-time) CPU
28 based on CPU 0's capabilities, so a multi-processor system with non-identical
44 If CPU 0 supports Altivec, the code is left untouched. If it doesn't, both
/linux-4.1.27/drivers/crypto/vmx/
DKconfig2 tristate "Encryption acceleration support on P8 CPU"
6 Support for VMX cryptographic acceleration instructions on Power8 CPU.
/linux-4.1.27/arch/mips/jazz/
DKconfig7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
19 This is a machine with a R4000 100 MHz CPU. To compile a Linux
30 This is a machine with a R4000 100 MHz CPU. To compile a Linux
/linux-4.1.27/arch/mn10300/kernel/
Dhead.S41 # If this is a secondary CPU (AP), then deal with that elsewhere
52 # Set up the Boot IPI for each secondary CPU
255 # mark the primary CPU in cpu_boot_map
260 # signal each secondary CPU to begin booting
261 mov 0x1,d2 # CPU ID
265 # send SMP_BOOT_IPI to secondary CPU
396 btst CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer)
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Dcpus.txt2 Power Architecture CPU Binding
9 present on CPU nodes.
31 these registers should be set if the coresponding CPU should be
/linux-4.1.27/arch/arm/kernel/
Dhyp-stub.S58 cmp \mode, \reg1 @ matches primary CPU boot mode?
85 @ Call this from the primary CPU
114 retne lr @ give up if the CPU is not in HYP mode
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
Dbf609.h85 # define CPU "BF609" macro
89 #ifndef CPU
/linux-4.1.27/Documentation/block/
Dnull_blk.txt33 Selects what CPU node the data structures are allocated from.
49 1: Soft-irq. Uses IPI to complete IOs across CPU nodes. Simulates the overhead
50 when IOs are issued from another CPU node than the home the device is
72 queue for each CPU node in the system.
/linux-4.1.27/Documentation/arm64/
Dbooting.txt16 simply to define all software that executes on the CPU(s) before control
130 - Primary CPU general-purpose register settings
136 - CPU mode
139 The CPU must be in either EL2 (RECOMMENDED in order to have access to
164 each CPU.
179 The requirements described above for CPU mode, caches, MMUs, architected
183 The boot loader is expected to enter the kernel on each CPU in the
186 - The primary CPU must jump directly to the first instruction of the
187 kernel image. The device tree blob passed by this CPU must contain
203 the primary CPU. When a read of the location pointed to by the
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-spear.txt4 SPEAr SoC cpufreq driver for CPU frequency scaling.
9 - cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the
Dcpufreq-exynos5440.txt5 Exynos5440 SoC cpufreq driver for CPU frequency scaling.
9 - operating-points: Table of frequencies and voltage CPU could be transitioned into,
/linux-4.1.27/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.txt4 global timer and CPU local timers. The global timer is a 64-bit free running
6 four preset counter values. The CPU local timers are 32-bit free running
8 one CPU local timer instantiated in MCT for every CPU in the system.
/linux-4.1.27/drivers/clk/mxs/
Dclk-imx23.c30 #define CPU (CLKCTRL + 0x0020) macro
56 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
132 clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); in mx23_clocks_init()
133 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); in mx23_clocks_init()
Dclk-imx28.c29 #define CPU (CLKCTRL + 0x0050) macro
90 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
196 clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); in mx28_clocks_init()
197 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); in mx28_clocks_init()
/linux-4.1.27/arch/mn10300/mm/
DKconfig.cache2 # MN10300 CPU cache options
6 prompt "CPU Caching mode"
53 prompt "CPU cache flush/invalidate method"
58 This determines the method by which CPU cache flushing and
88 bool "Use CPU Cache Snooping"
/linux-4.1.27/drivers/platform/mips/
DKconfig23 tristate "Loongson CPU HWMon Driver"
28 Loongson-3A/3B CPU Hwmon (temperature sensor) driver.
/linux-4.1.27/arch/powerpc/boot/dts/
Diss4xx-mpic.dts36 model = "PowerPC,4xx"; // real CPU changed in sim
50 model = "PowerPC,4xx"; // real CPU changed in sim
66 model = "PowerPC,4xx"; // real CPU changed in sim
82 model = "PowerPC,4xx"; // real CPU changed in sim
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt9 1 = cpuclk (CPU clock)
16 1 = cpuclk (CPU clock)
22 1 = cpuclk (CPU clock)
28 1 = cpuclk (CPU clock)
/linux-4.1.27/Documentation/devicetree/bindings/interrupt-controller/
Dmips-gic.txt6 global timer, per-CPU count/compare timers, and a watchdog.
23 - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
25 This property is ignored if the CPU is started in EIC mode.
Dbrcm,bcm7038-l1-intc.txt4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
13 - A separate instance of the register set for each CPU, allowing individual
14 peripheral IRQs to be routed to any CPU
Dmarvell,armada-370-xp-mpic.txt13 for the main interrupt registers, second pair for the per-CPU
17 current CPU)
/linux-4.1.27/Documentation/filesystems/nfs/
Dknfsd-stats.txt57 of how much CPU load is being placed on the sunrpc server layer
73 or because the NFS workload needs more CPU time than is available in
74 the thread pool (the workload is CPU-limited). In the former case,
95 enough CPU time to actually run.
98 heuristically avoids overloading the CPU scheduler with too many
101 is CPU limited. Usually this is associated with heavy CPU usage
106 pattern of CPU usage on all the CPUs associated with the given
/linux-4.1.27/arch/arm/mach-sa1100/
Dsleep.S50 @ Adjust memory timing before lowering CPU clock
53 @ delay 90us and set CPU PLL to lowest speed
137 @ about 7 ns out of the entire time that the CPU is running!
/linux-4.1.27/Documentation/devicetree/bindings/watchdog/
Datmel-wdt.txt30 watchdog not counting when the CPU is in idle state, therefore the
31 watchdog reset time depends on mean CPU usage and will not reset at all
32 if the CPU stop working while it is in idle state, which is probably
/linux-4.1.27/Documentation/locking/
Dlglock.txt17 as per_cpu elements but can be mostly handled by CPU local actions
26 CPU
40 is fast. Taking the local lock on a different CPU will be more
105 access to protected per_cpu object on this CPU
109 access to protected per_cpu object on other CPU cpu
119 CPUs rather than the actually present CPUs or a CPU could go off-line
129 * suitable for code that can do most operations on the CPU local
Dspinlocks.txt39 to do locking across CPU's, which implies that EVERYTHING that
99 several CPU's and you want to use spinlocks you can potentially use
121 the other interrupt happens on another CPU, but it is _not_ ok if the
122 interrupt happens on the same CPU that already holds the lock, because the
129 on other CPU's, because an interrupt on another CPU doesn't interrupt the
130 CPU that holds the lock, so the lock-holder can continue and eventually
Dlocktorture.txt71 randomly selected CPU-hotplug operation. Defaults
72 to zero, which disables CPU hotplugging. In
74 refuse to do any CPU-hotplug operations regardless of
77 onoff_holdoff The number of seconds to wait until starting CPU-hotplug
145 were no locking failures, CPU-hotplug problems were detected.
/linux-4.1.27/arch/mips/bmips/
DKconfig17 bool "BCM93384WVG Zephyr CPU"
21 bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
/linux-4.1.27/arch/arc/plat-arcfpga/
DKconfig30 -XTL (To enable CPU start/stop/set-PC for another CPU)
/linux-4.1.27/Documentation/devicetree/bindings/mips/
Dcpu_irq.txt1 MIPS CPU interrupt controller
3 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
/linux-4.1.27/arch/arm/mach-mvebu/
Dpmsu_ll.S18 orr r1, r1, #0x8 @ SCU CPU Power Status Register
19 mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
/linux-4.1.27/Documentation/misc-devices/
Dics932s40117 This chip has 4 clock outputs--a base clock for the CPU (which is likely
18 multiplied to get the real CPU clock), a system clock, a PCI clock, a USB
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
Dbf561.h192 #define CPU "BF561" macro
196 #ifndef CPU
/linux-4.1.27/Documentation/scsi/
Dhptiop.txt75 0x10400 PCIe Function 0 to CPU Message A
76 0x10420 CPU to PCIe Function 0 Message A
77 0x10480 CPU to PCIe Function 0 Doorbell
78 0x10484 CPU to PCIe Function 0 Doorbell Enable
161 Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
/linux-4.1.27/Documentation/devicetree/bindings/x86/
Dce4100.txt10 The CPU node
19 The reg property describes the CPU number. The lapic property points to
/linux-4.1.27/Documentation/accounting/
Ddelay-accounting.txt6 runnable task may wait for a free CPU to run on.
11 a) waiting for a CPU (while being runnable)
94 CPU count real total virtual total delay total
110 CPU count real total virtual total delay total
Dtaskstats-struct.txt73 /* The user CPU time of a task, in [usec]. */
74 __u64 ac_utime; /* User CPU time [usec] */
76 /* The system CPU time of a task, in [usec]. */
77 __u64 ac_stime; /* System CPU time [usec] */
/linux-4.1.27/init/
DKconfig330 menu "CPU/Task time and stats accounting"
352 bool "Deterministic task and CPU time accounting"
356 Select this option to enable more accurate task and CPU time
357 accounting. This is done by reading a CPU counter on each
365 bool "Full dynticks CPU time accounting"
371 Select this option to enable task and CPU time accounting on full
464 endmenu # "CPU/Task time and stats accounting"
525 This option enables RCU CPU stall code that is common between
527 the tiny variants to disable RCU CPU stall warnings, while
539 puts RCU in extended quiescent state when the CPU runs in
[all …]
/linux-4.1.27/arch/arm/boot/dts/
Dsh73a0-kzm9g.dts226 regulator-name = "1.315V CPU";
247 regulator-name = "2.8V CPU";
254 regulator-name = "3.0V CPU";
275 regulator-name = "1.15V CPU";
282 regulator-name = "1.15V CPU #2";
Dkirkwood-blackarmor-nas220.dts98 * pin 1 - TX (CPU's TX)
99 * pin 4 - RX (CPU's RX)
/linux-4.1.27/Documentation/vm/
Dnuma25 to and accessible from any CPU attached to any cell and cache coherency
29 away the cell containing the CPU or IO bus making the memory access is from the
89 node to which the CPU that executes the request is assigned. Specifically,
108 to improve NUMA locality using various CPU affinity command line interfaces,
120 node the "local memory node"--the node of the first zone in CPU's node's
131 a subsystem allocates per CPU memory resources, for example.
134 node to which the "current CPU" is attached using one of the kernel's
148 specified CPU. Again, this is the same node from which default, local page
/linux-4.1.27/arch/arm64/
DKconfig228 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
229 but contains an NVIDIA Denver CPU complex in place of
230 Tegra124's "4+1" Cortex-A15 CPU complex.
309 the kernel if an affected CPU is detected.
330 the kernel if an affected CPU is detected.
352 only patch the kernel if an affected CPU is detected.
373 the kernel if an affected CPU is detected.
391 the kernel if an affected CPU is detected.
412 the kernel if an affected CPU is detected.
492 This enables support for systems with more than one CPU. If
[all …]
/linux-4.1.27/arch/powerpc/platforms/82xx/
DKconfig60 The MPC8260 is a typical embedded CPU made by Freescale. Selecting
62 an 8260 class CPU.
/linux-4.1.27/arch/m32r/
DKconfig237 # Define implied options from the CPU selection here
279 This enables support for systems with more than one CPU. If you have
280 a system with only one CPU, say N. If you have a system with more
281 than one CPU, say Y.
284 machines, but will use only one CPU of a multiprocessor machine. If
313 This is purely to save memory - each supported CPU adds
338 bus system, i.e. the way the CPU talks to the other stuff inside
/linux-4.1.27/arch/metag/
DKconfig.soc9 This is a Meta 1.2 FPGA bitstream, just a bare CPU.
15 This is a Meta 2.1 FPGA bitstream, just a bare CPU.
/linux-4.1.27/arch/alpha/
DKconfig218 CPU.
319 name of a bus system, i.e. the way the CPU talks to the other stuff
335 bus system, i.e. the way the CPU talks to the other stuff inside
390 bool "EV5 CPU(s) (model 5/xxx)?" if ALPHA_LYNX
403 bool "EV56 CPU (speed >= 366MHz)?" if ALPHA_ALCOR
407 prompt "EV56 CPU (speed >= 333MHz)?"
411 prompt "EV56 CPU (speed >= 400MHz)?"
415 bool "EV5 CPU daughtercard (model 5/xxx)?"
421 bool "EV5 CPU(s) (model 5/xxx)?"
452 bool "EV67 (or later) CPU (speed > 600MHz)?" if ALPHA_DP264 || ALPHA_EIGER
[all …]
/linux-4.1.27/fs/squashfs/
DKconfig62 decompression performance and CPU and memory usage.
71 one time. This limits CPU and memory usage to a minimum.
77 poor performance on parallel I/O workloads when using multiple CPU
91 poor performance on parallel I/O workloads when using multiple CPU
118 achieved and the amount of CPU time and memory necessary to
160 the default zlib compression, at the expense of greater CPU and
/linux-4.1.27/arch/parisc/
DKconfig125 This is the processor type of your CPU. This information is
161 # Define implied options from the CPU selection here
237 This enables support for systems with more than one CPU. If you have
238 a system with only one CPU, say N. If you have a system with more
239 than one CPU, say Y.
242 machines, but will use only one CPU of a multiprocessor machine. If
/linux-4.1.27/arch/sparc/
DKconfig162 This enables support for systems with more than one CPU. If you have
163 a system with only one CPU, say N. If you have a system with more
164 than one CPU, say Y.
167 machines, but will use only one CPU of a multiprocessor machine. If
259 Say N if you want to disable CPU hotplug.
322 SMT scheduler support improves the CPU scheduler's decision making
331 Multi-core scheduler support improves the CPU scheduler's decision
332 making when dealing with multi-core CPU chips at a cost of slightly
358 Enable power management and CPU standby features on supported
462 a bus system, i.e. the way the CPU talks to the other stuff inside
/linux-4.1.27/arch/mn10300/boot/compressed/
Dhead.S28 # Must save primary CPU's D0-D2 registers as they hold boot parameters
/linux-4.1.27/tools/testing/selftests/rcutorture/configs/lock/
Dver_functions.sh29 echo CPU-hotplug kernel, adding locktorture onoff. 1>&2
/linux-4.1.27/arch/arm/vfp/
Dvfphw.S78 @ r11 = CPU number
137 @ However, it may have been migrated to another CPU, in which
139 @ Check this by looking at the CPU number which the state was
/linux-4.1.27/arch/powerpc/platforms/85xx/
DKconfig111 P1010RDB contains P1010Si, which provides CPU performance up to 800
261 Unlike most e500 boards that target a specific CPU, this
262 platform works with any e500-family CPU that QEMU supports.
264 unset based on the emulated CPU (or actual host CPU in the case
/linux-4.1.27/tools/perf/tests/attr/
Dtest-record-C08 # no enable on exec for CPU attached
/linux-4.1.27/arch/ia64/
DKconfig335 This enables support for systems with more than one CPU. If you have
336 a system with only one CPU, say N. If you have a system with more
337 than one CPU, say Y.
340 systems, but will use only one CPU of a multiprocessor system. If
358 only use 2 CPUs on a >2 CPU system. Setting this to a value larger
359 than 64 will cause the use of a CPU mask array, causing a small
369 Say N if you want to disable CPU hotplug.
381 Improves the CPU scheduler's decision making when dealing with
400 Tiger4 systems are capable of re-directing CPEI to any CPU other than BSP.
577 menu "CPU Frequency scaling"
/linux-4.1.27/tools/testing/selftests/rcutorture/configs/rcu/
Dver_functions.sh41 echo CPU-hotplug kernel, adding rcutorture onoff. 1>&2
/linux-4.1.27/arch/arm/mach-vexpress/
Ddcscb_setup.S33 2: @ Implementation-specific local CPU setup operations should go here,
/linux-4.1.27/arch/arm/mach-nspire/
DKconfig11 This enables support for systems using the TI-NSPIRE CPU
/linux-4.1.27/tools/testing/selftests/rcutorture/bin/
Dkvm-test-1-run.sh147 echo CPU count limited from $cpu_count to $vcpus
149 echo CPU count limited from $cpu_count to $vcpus >> $resdir/Warnings
/linux-4.1.27/net/caif/
DKconfig10 The "Communication CPU to Application CPU Interface" (CAIF) is a packet
/linux-4.1.27/Documentation/virtual/kvm/
Dnested-vmx.txt52 emulated CPU type (qemu64) does not list the "VMX" CPU feature, so it must be
55 -cpu host (emulated CPU has all features of the real CPU)
57 -cpu qemu64,+vmx (add just the vmx feature to a named CPU type)
/linux-4.1.27/Documentation/arm/sti/
Dstih416-overview.txt11 - ARM Cortex-A9 1.2 GHz dual core CPU
Dstih415-overview.txt11 - ARM Cortex-A9 1.0 GHz, dual-core CPU
/linux-4.1.27/Documentation/devicetree/bindings/arm/hisilicon/
Dhisilicon.txt65 Hisilicon CPU controller
72 in CPU controller, especially in HIX5HD2 SoC.
/linux-4.1.27/arch/arm/
DKconfig-nommu47 If your CPU provides a remap facility which allows the exception
63 If your CPU has an MPU then you should choose 'y' here unless you
/linux-4.1.27/drivers/thermal/
DKconfig216 (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
228 bound cpufreq cooling device turns active to set CPU frequency low to
229 cool down the CPU.
247 Enable this to register CPU digital sensor for package temperature as
258 addition to DTSs on CPU cores. Each DTS will be registered as a
273 CPU/SOC, for thermal safety reasons.
/linux-4.1.27/arch/arc/
DKconfig90 menu "ARC CPU Configuration"
118 Build kernel for Big Endian Mode of ARC CPU
128 This enables support for systems with more than one CPU. If you have
129 a system with only one CPU, say N. If you have a system with more
130 than one CPU, say Y.
332 endmenu # "ARC CPU Configuration"
/linux-4.1.27/Documentation/devicetree/bindings/arm/rockchip/
Dpmu.txt5 This includes the power to the CPU cores.

1234