1Freescale Vybrid Miscellaneous System Control - Interrupt Router
2
3The MSCM IP contains multiple sub modules, this binding describes the second
4block of registers which control the interrupt router. The interrupt router
5allows to configure the recipient of each peripheral interrupt. Furthermore
6it controls the directed processor interrupts. The module is available in all
7Vybrid SoC's but is only really useful in dual core configurations (VF6xx
8which comes with a Cortex-A5/Cortex-M4 combination).
9
10Required properties:
11- compatible:		"fsl,vf610-mscm-ir"
12- reg:			the register range of the MSCM Interrupt Router
13- fsl,cpucfg:		The handle to the MSCM CPU configuration node, required
14			to get the current CPU ID
15- interrupt-controller:	Identifies the node as an interrupt controller
16- #interrupt-cells:	Two cells, interrupt number and cells.
17			The hardware interrupt number according to interrupt
18			assignment of the interrupt router is required.
19			Flags get passed only when using GIC as parent. Flags
20			encoding as documented by the GIC bindings.
21- interrupt-parent:	Should be the phandle for the interrupt controller of
22			the CPU the device tree is intended to be used on. This
23			is either the node of the GIC or NVIC controller.
24
25Example:
26	mscm_ir: interrupt-controller@40001800 {
27		compatible = "fsl,vf610-mscm-ir";
28		reg = <0x40001800 0x400>;
29		fsl,cpucfg = <&mscm_cpucfg>;
30		interrupt-controller;
31		#interrupt-cells = <2>;
32		interrupt-parent = <&intc>;
33	}
34