Searched refs:PWM (Results 1 - 200 of 292) sorted by relevance

12

/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/pwm/
H A Dpwm.h2 * This header provides constants for most PWM bindings.
4 * Most PWM bindings can include a flags cell as part of the PWM specifier.
/linux-4.4.14/include/dt-bindings/pwm/
H A Dpwm.h2 * This header provides constants for most PWM bindings.
4 * Most PWM bindings can include a flags cell as part of the PWM specifier.
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/pwm/
H A Dpwm.h2 * This header provides constants for most PWM bindings.
4 * Most PWM bindings can include a flags cell as part of the PWM specifier.
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/pwm/
H A Dpwm.h2 * This header provides constants for most PWM bindings.
4 * Most PWM bindings can include a flags cell as part of the PWM specifier.
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/pwm/
H A Dpwm.h2 * This header provides constants for most PWM bindings.
4 * Most PWM bindings can include a flags cell as part of the PWM specifier.
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/pwm/
H A Dpwm.h2 * This header provides constants for most PWM bindings.
4 * Most PWM bindings can include a flags cell as part of the PWM specifier.
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/pwm/
H A Dpwm.h2 * This header provides constants for most PWM bindings.
4 * Most PWM bindings can include a flags cell as part of the PWM specifier.
/linux-4.4.14/include/linux/
H A Dpwm.h13 * pwm_request - request a PWM device
18 * pwm_free - free a PWM device
23 * pwm_config - change a PWM device configuration
28 * pwm_enable - start a PWM output toggling
33 * pwm_disable - stop a PWM output toggling
64 * enum pwm_polarity - polarity of a PWM signal
84 * struct pwm_device - PWM channel object
85 * @label: name of the PWM device
86 * @flags: flags associated with the PWM device
87 * @hwpwm: per-chip relative index of the PWM device
88 * @pwm: global index of the PWM device
89 * @chip: PWM chip providing this PWM device
90 * @chip_data: chip-private data associated with the PWM device
91 * @lock: used to serialize accesses to the PWM device where necessary
92 * @period: period of the PWM signal (in nanoseconds)
93 * @duty_cycle: duty cycle of the PWM signal (in nanoseconds)
94 * @polarity: polarity of the PWM signal
138 * pwm_set_polarity - configure the polarity of a PWM signal
148 * struct pwm_ops - PWM controller operations
149 * @request: optional hook for requesting a PWM
150 * @free: optional hook for freeing a PWM
151 * @config: configure duty cycles and period length for this PWM
152 * @set_polarity: configure the polarity of this PWM
153 * @enable: enable PWM output toggling
154 * @disable: disable PWM output toggling
174 * struct pwm_chip - abstract a PWM controller
177 * @ops: callbacks for this PWM controller
178 * @base: number of first PWM controlled by this chip
180 * @pwms: array of PWM devices allocated by the framework
181 * @of_xlate: request a PWM device given a device tree PWM specifier
182 * @of_pwm_n_cells: number of cells expected in the device tree PWM specifier
H A Dleds_pwm.h2 * PWM LED driver data - see drivers/leds/leds-pwm.c
H A Dpwm_backlight.h2 * Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c
H A Dled-lm3530.h75 /* PWM Platform Specific Data */
83 * @mode: mode of operation i.e. Manual, ALS or PWM
86 * @pwm_pol_hi: PWM input polarity - active high/active low
96 * @pwm_data: PWM control functions (only valid when the mode is PWM)
H A Datmel_tc.h23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
124 * generation mode (including PWM) or "capture" mode (to time events). In
128 * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
/linux-4.4.14/drivers/pwm/
H A Dcore.c200 * pwm_set_chip_data() - set private chip data for a PWM
201 * @pwm: PWM device
218 * pwm_get_chip_data() - get private chip data for a PWM
219 * @pwm: PWM device
221 * Returns: A pointer to the chip-private data for the PWM device.
230 * pwmchip_add_with_polarity() - register a new PWM chip
231 * @chip: the PWM chip to add
232 * @polarity: initial polarity of PWM channels
234 * Register a new PWM chip. If chip->base < 0 then a dynamically assigned base
296 * pwmchip_add() - register a new PWM chip
297 * @chip: the PWM chip to add
299 * Register a new PWM chip. If chip->base < 0 then a dynamically assigned base
311 * pwmchip_remove() - remove a PWM chip
312 * @chip: the PWM chip to remove
314 * Removes a PWM chip. This function may return busy if the PWM chip provides
315 * a PWM device that is still requested.
351 * pwm_request() - request a PWM device
352 * @pwm: global PWM device index
353 * @label: PWM device label
357 * Returns: A pointer to a PWM device or an ERR_PTR()-encoded error code on
388 * pwm_request_from_chip() - request a PWM device relative to a PWM chip
389 * @chip: PWM chip
390 * @index: per-chip index of the PWM to request
391 * @label: a literal description string of this PWM
393 * Returns: A pointer to the PWM device at the given index of the given PWM
395 * specified PWM chip or if the PWM device cannot be requested.
420 * pwm_free() - free a PWM device
421 * @pwm: PWM device
432 * pwm_config() - change a PWM device configuration
433 * @pwm: PWM device
458 * pwm_set_polarity() - configure the polarity of a PWM signal
459 * @pwm: PWM device
460 * @polarity: new polarity of the PWM signal
462 * Note that the polarity cannot be configured while the PWM device is
497 * pwm_enable() - start a PWM output toggling
498 * @pwm: PWM device
524 * pwm_disable() - stop a PWM output toggling
525 * @pwm: PWM device
552 * of_pwm_get() - request a PWM via the PWM framework
553 * @np: device node to get the PWM from
556 * Returns the PWM device parsed from the phandle and index specified in the
558 * Values parsed from the device tree are stored in the returned PWM device
561 * If con_id is NULL, the first PWM device listed in the "pwms" property will
563 * lookup of the PWM index. This also means that the "pwm-names" property
564 * becomes mandatory for devices that look up the PWM device via the con_id
567 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded
593 pr_debug("%s(): PWM chip not found\n", __func__); of_pwm_get()
631 * pwm_add_table() - register PWM device consumers
648 * pwm_remove_table() - unregister PWM device consumers
665 * pwm_get() - look up and request a PWM device
666 * @dev: device for PWM consumer
670 * a device tree, a PWM chip and a relative index is looked up via a table
673 * Once a PWM chip has been found the specified PWM device will be requested
676 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded
699 * If a match is found, the provider PWM chip is looked up by name pwm_get()
700 * and a PWM device is requested using the PWM device per-chip index. pwm_get()
764 * pwm_put() - release a PWM device
765 * @pwm: PWM device
775 pr_warn("PWM device already freed\n"); pwm_put()
797 * @dev: device for PWM consumer
800 * This function performs like pwm_get() but the acquired PWM device will
803 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded
828 * @dev: device for PWM consumer
829 * @np: device node to get the PWM from
832 * This function performs like of_pwm_get() but the acquired PWM device will
835 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded
871 * @dev: device for PWM consumer
872 * @pwm: PWM device
874 * Release a PWM previously allocated using devm_pwm_get(). Calling this
885 * pwm_can_sleep() - report whether PWM access will sleep
886 * @pwm: PWM device
888 * Returns: True if accessing the PWM can sleep, false otherwise.
940 seq_printf(s, "%s%s/%s, %d PWM device%s\n", (char *)s->private, pwm_seq_show()
H A Dpwm-imx.c2 * simple driver for PWM (Pulse Width Modulator) controller
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
23 /* i.MX1 and i.MX21 share the same PWM function block: */
25 #define MX1_PWMC 0x00 /* PWM Control Register */
26 #define MX1_PWMS 0x04 /* PWM Sample Register */
27 #define MX1_PWMP 0x08 /* PWM Period Register */
31 /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
33 #define MX3_PWMCR 0x00 /* PWM Control Register */
34 #define MX3_PWMSR 0x04 /* PWM Status Register */
35 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
36 #define MX3_PWMPR 0x10 /* PWM Period Register */
71 * The PWM subsystem allows for exact frequencies. However, imx_pwm_config_v1()
72 * I cannot connect a scope on my device to the PWM line and imx_pwm_config_v1()
73 * thus cannot provide the program the PWM controller imx_pwm_config_v1()
75 * Bootloader (u-boot or WinCE+haret) has programmed the PWM imx_pwm_config_v1()
76 * function group already. So I'll just modify the PWM sample imx_pwm_config_v1()
125 * wait for a full PWM cycle to get a relinquished FIFO slot imx_pwm_config_v2()
H A Dpwm-twl.c87 * When on cycle == off cycle the PWM will be always on twl_pwm_config()
100 dev_err(chip->dev, "%s: Failed to configure PWM\n", pwm->label); twl_pwm_config()
122 dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label); twl4030_pwm_enable()
128 dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label); twl4030_pwm_enable()
152 dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label); twl4030_pwm_disable()
158 dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label); twl4030_pwm_disable()
185 /* Save the current MUX configuration for the PWM */ twl4030_pwm_request()
189 /* Select PWM functionality */ twl4030_pwm_request()
195 dev_err(chip->dev, "%s: Failed to request PWM\n", pwm->label); twl4030_pwm_request()
220 /* Restore the MUX configuration for the PWM */ twl4030_pwm_free()
226 dev_err(chip->dev, "%s: Failed to free PWM\n", pwm->label); twl4030_pwm_free()
245 dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label); twl6030_pwm_enable()
268 dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label); twl6030_pwm_disable()
350 MODULE_DESCRIPTION("PWM driver for TWL4030 and TWL6030");
H A Dpwm-lpss.c2 * Intel Low Power Subsystem PWM controller driver
23 #define PWM 0x00000000 macro
33 /* Size of each PWM register space if multiple */
72 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); pwm_lpss_read()
79 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); pwm_lpss_write()
115 /* request PWM to update on next cycle */ pwm_lpss_config()
167 dev_err(dev, "failed to add PWM chip: %d\n", ret); pwm_lpss_probe()
181 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
H A Dpwm-tipwmss.h2 * TI PWM Subsystem driver
21 /* PWM substem clock gating */
H A Dpwm-atmel.c22 /* The following is global registers for PWM controller */
30 /* The following register is PWM channel related registers */
40 /* The following registers for PWM v1 */
45 /* The following registers for PWM v2 */
118 dev_err(chip->dev, "cannot change PWM period while enabled\n"); atmel_pwm_config()
144 dev_err(chip->dev, "failed to enable PWM clock\n"); atmel_pwm_config()
176 * If the PWM channel is enabled, only update CDTY by using the update atmel_pwm_config_v1()
182 * If the PWM channel is disabled, write value to duty and period atmel_pwm_config_v1()
196 * If the PWM channel is enabled, using the duty update register atmel_pwm_config_v2()
202 * If the PWM channel is disabled, write value to duty and atmel_pwm_config_v2()
226 dev_err(chip->dev, "failed to enable PWM clock\n"); atmel_pwm_set_polarity()
244 dev_err(chip->dev, "failed to enable PWM clock\n"); atmel_pwm_enable()
370 dev_err(&pdev->dev, "failed to prepare PWM clock\n"); atmel_pwm_probe()
391 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret); atmel_pwm_probe()
427 MODULE_DESCRIPTION("Atmel PWM driver");
H A Dpwm-twl-led.c31 * This driver handles the PWM driven LED terminals of TWL4030 and TWL6030.
85 * When on cycle == off cycle the PWM will be always on twl4030_pwmled_config()
98 dev_err(chip->dev, "%s: Failed to configure PWM\n", pwm->label); twl4030_pwmled_config()
120 dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label); twl4030_pwmled_enable()
145 dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label); twl4030_pwmled_disable()
163 dev_err(chip->dev, "%s: Failed to configure PWM\n", pwm->label); twl6030_pwmled_config()
187 dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label); twl6030_pwmled_enable()
214 dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label); twl6030_pwmled_disable()
239 dev_err(chip->dev, "%s: Failed to request PWM\n", pwm->label); twl6030_pwmled_request()
265 dev_err(chip->dev, "%s: Failed to free PWM\n", pwm->label); twl6030_pwmled_free()
346 MODULE_DESCRIPTION("PWM driver for TWL4030 and TWL6030 LED outputs");
H A Dpwm-atmel-tcb.c34 enum pwm_polarity polarity; /* PWM polarity */
35 unsigned div; /* PWM clock divider */
36 unsigned duty; /* PWM duty expressed in clk cycles */
37 unsigned period; /* PWM period expressed in clk cycles */
95 * Timer Counter is already configured as a PWM generator. atmel_tcb_pwm_request()
176 * If both PWM devices in this group are disabled we stop the clock. atmel_tcb_pwm_disable()
326 * PWM devices provided by TCB driver are grouped by 2: atmel_tcb_pwm_config()
327 * - group 0: PWM 0 & 1 atmel_tcb_pwm_config()
328 * - group 1: PWM 2 & 3 atmel_tcb_pwm_config()
329 * - group 2: PWM 4 & 5 atmel_tcb_pwm_config()
331 * PWM devices in a given group must be configured with the atmel_tcb_pwm_config()
334 * We're checking the period value of the second PWM device atmel_tcb_pwm_config()
341 "failed to configure period_ns: PWM group already configured with a different value\n"); atmel_tcb_pwm_config()
349 /* If the PWM is enabled, call enable to apply the new conf */ atmel_tcb_pwm_config()
H A Dpwm-tiecap.c2 * ECAP PWM driver
107 * compare values. This helps current PWM period to ecap_pwm_config()
134 /* Duty cycle defines LOW period of PWM */ ecap_pwm_set_polarity()
137 /* Duty cycle defines HIGH period of PWM */ ecap_pwm_set_polarity()
150 /* Leave clock enabled on enabling PWM */ ecap_pwm_enable()
176 /* Disable clock on PWM disable */ ecap_pwm_disable()
183 dev_warn(chip->dev, "Removing PWM device without disabling\n"); ecap_pwm_free()
308 /* Disable explicitly if PWM is running */ ecap_pwm_suspend()
320 /* Enable explicitly if PWM was running */ ecap_pwm_resume()
343 MODULE_DESCRIPTION("ECAP PWM driver");
H A Dpwm-sti.c2 * PWM device driver for ST SoCs.
107 * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles.
108 * The only way to change the period (apart from changing the PWM input clock)
109 * is to change the PWM clock prescaler.
146 /* Enable clock before writing to PWM registers. */ sti_pwm_config()
170 * When PWMVal == 0, PWM pulse = 1 local clock cycle. sti_pwm_config()
172 * PWM pulse = (max_pwm_count + 1) local cycles, sti_pwm_config()
204 * Since we have a common enable for all PWM channels, sti_pwm_enable()
215 dev_err(dev, "failed to enable PWM device:%d\n", sti_pwm_enable()
327 * Setup PWM data with default values: some values could be replaced sti_pwm_probe()
346 dev_err(dev, "failed to get PWM clock\n"); sti_pwm_probe()
409 MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
H A Dpwm-ep93xx.c2 * PWM framework driver for Cirrus Logic EP93xx
82 * The clock needs to be enabled to access the PWM registers. ep93xx_pwm_config()
104 /* Order is important if PWM is running */ ep93xx_pwm_config()
129 * The clock needs to be enabled to access the PWM registers. ep93xx_pwm_polarity()
130 * Polarity can only be changed when the PWM is disabled. ep93xx_pwm_polarity()
226 MODULE_DESCRIPTION("Cirrus Logic EP93xx PWM driver");
H A Dpwm-lpss.h2 * Intel Low Power Subsystem PWM controller driver
H A Dpwm-tiehrpwm.c2 * EHRPWM PWM driver
205 * Configure PWM output to HIGH/LOW level on counter configure_polarity()
264 * Period values should be same for multiple PWM channels as IP uses ehrpwm_pwm_config()
285 /* Configure clock prescaler to support Low frequency PWM wave */ ehrpwm_pwm_config()
339 /* Leave clock enabled on enabling PWM */ ehrpwm_pwm_enable()
342 /* Disabling Action Qualifier on PWM output */ ehrpwm_pwm_enable()
360 /* Enable TBCLK before enabling PWM device */ ehrpwm_pwm_enable()
378 /* Action Qualifier puts PWM output low forcefully */ ehrpwm_pwm_disable()
389 * Action Qualifier control on PWM output from next TBCLK ehrpwm_pwm_disable()
396 /* Disabling TBCLK on PWM disable */ ehrpwm_pwm_disable()
402 /* Disable clock on PWM disable */ ehrpwm_pwm_disable()
411 dev_warn(chip->dev, "Removing PWM device without disabling\n"); ehrpwm_pwm_free()
571 /* Disable explicitly if PWM is running */ ehrpwm_pwm_suspend()
588 /* Enable explicitly if PWM was running */ ehrpwm_pwm_resume()
611 MODULE_DESCRIPTION("EHRPWM PWM driver");
H A Dpwm-lpss-platform.c2 * Intel Low Power Subsystem PWM controller driver
73 MODULE_DESCRIPTION("PWM platform driver for Intel LPSS");
H A Dpwm-pxa.c4 * simple driver for PWM (Pulse Width Modulator) controller
29 /* PWM has_secondary_pwm? */
38 /* PWM registers and bits definitions */
92 /* NOTE: the clock to PWM has to be enabled first pxa_pwm_config()
130 * Device tree users must create one device instance for each PWM channel.
H A Dpwm-ab8500.c16 * PWM Out generators
65 dev_err(chip->dev, "%s: Failed to enable PWM, Error %d\n", ab8500_pwm_enable()
78 dev_err(chip->dev, "%s: Failed to disable PWM, Error %d\n", ab8500_pwm_disable()
H A Dpwm-samsung.c7 * PWM driver for Samsung SoCs
61 * struct samsung_pwm_channel - private data of PWM channel
73 * struct samsung_pwm_chip - private data of PWM chip
74 * @chip: generic PWM chip
77 * @base: base address of mapped PWM registers
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
101 * because all the supported SoCs contain only one instance of the PWM
185 "tclk of PWM %d is inoperational, using tdiv\n", chan); pwm_samsung_calc_tin()
192 * Compare minimum PWM frequency that can be achieved with possible pwm_samsung_calc_tin()
212 "tried to request PWM channel %d without output\n", pwm_samsung_request()
315 /* Check to see if we are changing the clock rate of the PWM. */ pwm_samsung_config()
354 /* Update PWM registers. */ pwm_samsung_config()
359 * In case the PWM is currently at 100% duty cycle, force a manual pwm_samsung_config()
360 * update to prevent the signal staying high if the PWM is disabled pwm_samsung_config()
558 dev_err(dev, "failed to register PWM chip\n"); pwm_samsung_probe()
593 * Otherwise driver leaves PWM unconfigured if same values are pwm_samsung_suspend()
H A Dpwm-lpss-pci.c2 * Intel Low Power Subsystem PWM controller PCI driver
98 MODULE_DESCRIPTION("PWM PCI driver for Intel LPSS");
H A Dpwm-renesas-tpu.c2 * R-Mobile TPU PWM driver
71 TPU_PIN_PWM, /* Pin is driven by PWM */
111 static const char * const states[] = { "inactive", "PWM", "active" }; tpu_pwm_set_pin()
181 * - PWM mode tpu_pwm_timer_start()
215 * PWM API
428 dev_err(&pdev->dev, "failed to register PWM chip\n"); tpu_probe()
432 dev_info(&pdev->dev, "TPU PWM %d registered\n", tpu->pdev->id); tpu_probe()
478 MODULE_DESCRIPTION("Renesas TPU PWM Driver");
H A Dpwm-lp3943.c2 * TI/National Semiconductor LP3943 PWM driver
168 * Each PWM generator is set to control any of outputs of LP3943. lp3943_pwm_enable()
169 * To enable/disable the PWM, these output pins should be configured. lp3943_pwm_enable()
182 * when the PWM is disabled. lp3943_pwm_disable()
217 * Each of the two PWM generators can drive zero or more outputs. lp3943_pwm_parse_dt()
313 MODULE_DESCRIPTION("LP3943 PWM driver");
H A Dpwm-sun4i.c150 dev_err(chip->dev, "failed to enable PWM clock\n"); sun4i_pwm_config()
198 dev_err(chip->dev, "failed to enable PWM clock\n"); sun4i_pwm_set_polarity()
226 dev_err(chip->dev, "failed to enable PWM clock\n"); sun4i_pwm_enable()
342 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); sun4i_pwm_probe()
350 dev_err(&pdev->dev, "failed to enable PWM clock\n"); sun4i_pwm_probe()
386 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
H A Dpwm-brcmstb.c2 * Broadcom BCM7038 PWM driver
50 * Maximum control word value allowed when variable-frequency PWM is used as a
103 * The PWM core framework specifies that the "duty_ns" parameter is in fact the
284 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); brcmstb_pwm_probe()
341 MODULE_DESCRIPTION("Broadcom STB PWM driver");
H A Dpwm-img.c25 /* PWM registers */
43 * PWM period is specified with a timebase register,
44 * in number of step periods. The PWM duty cycle is also
49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
300 MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
H A Dpwm-bcm2835.c20 #define PWM_MODE 0x80 /* set timer in PWM mode */
27 #define MIN_PERIOD 108 /* 9.2 MHz max. PWM clock */
204 MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
H A Dpwm-berlin.c2 * Marvell Berlin PWM driver
186 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); berlin_pwm_probe()
218 MODULE_DESCRIPTION("Marvell Berlin PWM driver");
H A Dpwm-jz4740.c3 * JZ4740 platform PWM support
64 dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n", jz4740_pwm_request()
204 MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
H A Dpwm-mxs.c77 * If the PWM channel is disabled, make sure to turn on the clock mxs_pwm_config()
93 * If the PWM is not enabled, turn the clock off again to save power. mxs_pwm_config()
205 MODULE_DESCRIPTION("Freescale MXS PWM Driver");
H A Dpwm-lpc32xx.c142 dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret); lpc32xx_pwm_probe()
180 MODULE_DESCRIPTION("LPC32XX PWM Driver");
H A Dpwm-puv3.c68 * NOTE: the clock to PWM has to be enabled first puv3_pwm_config()
148 .name = "PKUnity-v3-PWM",
H A Dpwm-tipwmss.c2 * TI PWM Subsystem driver
131 MODULE_DESCRIPTION("PWM Subsystem driver");
H A Dpwm-rcar.c2 * R-Car PWM Timer driver
180 /* Don't enable the PWM device if CYC0 or PH0 is 0 */ rcar_pwm_enable()
237 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret); rcar_pwm_probe()
272 MODULE_DESCRIPTION("Renesas PWM Timer Driver");
H A Dpwm-tegra.c87 * cycles at the PWM clock rate will take period_ns nanoseconds. tegra_pwm_config()
95 * Since the actual PWM divider is the register's frequency divider tegra_pwm_config()
112 * If the PWM channel is disabled, make sure to turn on the clock tegra_pwm_config()
125 * If the PWM is not enabled, turn the clock off again to save power. tegra_pwm_config()
H A Dpwm-bcm-kona.c28 * The Kona PWM has some unusual characteristics. Here are the main points.
44 * 5) When the external clock that feeds the PWM is disabled, output is pegged
93 * it. Failing to do this may result in no PWM signal. kona_pwmc_prepare_for_settings()
309 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); kona_pwmc_probe()
344 MODULE_DESCRIPTION("Broadcom Kona PWM driver");
H A Dpwm-lpc18xx-sct.c21 * global to all the channels, thus PWM driver will refuse setting different
202 * The PWM supports only a single period for all PWM channels. lpc18xx_pwm_config()
208 dev_err(chip->dev, "conflicting period requested for PWM %u\n", lpc18xx_pwm_config()
464 MODULE_DESCRIPTION("NXP LPC18xx PWM driver");
H A Dpwm-pca9685.c2 * Driver for PCA9685 16-channel 12-bit PWM LED controller
34 * one channel affects the period of all 16 PWM outputs!
122 * If the duty cycle did not change, restart PWM with pca9685_pwm_config()
211 * The PWM subsystem does not support a pre-delay. pca9685_pwm_enable()
397 MODULE_DESCRIPTION("PWM driver for PCA9685");
H A Dpwm-fsl-ftm.c2 * Freescale FlexTimer Module (FTM) PWM Driver
243 * all PWM channels, therefore incompatible changes need to be fsl_pwm_config()
248 "conflicting period requested for PWM %u\n", fsl_pwm_config()
349 /* no users left, disable PWM counter clock */ fsl_counter_clock_disable()
475 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); fsl_pwm_probe()
553 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
H A Dpwm-clps711x.c2 * Cirrus Logic CLPS711X PWM driver
174 MODULE_DESCRIPTION("Cirrus Logic CLPS711X PWM driver");
H A Dpwm-atmel-hlcdc.c123 * The PWM duty cycle is configurable from 0/256 to 255/256 of the atmel_hlcdc_pwm_config()
222 /* 9n12 has same errata as 9x5 HLCDC PWM */
317 MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
H A Dpwm-rockchip.c2 * PWM driver for Rockchip SoCs
143 * and the core will only change polarity when the PWM is not enabled. rockchip_pwm_set_polarity()
302 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
H A Dpwm-spear.c27 /* PWM registers and bits definitions */
121 * NOTE: the clock to PWM has to be enabled first before writing to the spear_pwm_config()
212 * Following enables PWM chip, channels would still be spear_pwm_probe()
H A Dpwm-bfin.c2 * Blackfin Pulse Width Modulation (PWM) core
H A Dpwm-crc.c36 * struct crystalcove_pwm - Crystal Cove PWM controller
H A Dpwm-vt8500.c243 dev_err(&pdev->dev, "failed to add PWM chip\n"); vt8500_pwm_probe()
274 MODULE_DESCRIPTION("VT8500 PWM Driver");
H A Dpwm-mtk-disp.c242 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
H A Dsysfs.c2 * A simple sysfs interface for the generic PWM framework
/linux-4.4.14/arch/mips/include/asm/mach-loongson32/
H A Dregs-pwm.h4 * Loongson 1 PWM Register Definitions.
15 /* Loongson 1 PWM Timer Register Definitions */
21 /* PWM Control Register Bits */
/linux-4.4.14/arch/arm/mach-s3c64xx/
H A Dbacklight.h13 /* samsung_bl_gpio_info - GPIO info for PWM Backlight control
14 * @no: GPIO number for PWM timer out
15 * @func: Special function of GPIO line for PWM timer
H A Ddev-backlight.c5 * Common infrastructure for PWM Backlight for Samsung boards
42 /* Configure GPIO pin with specific GPIO function for PWM timer */ samsung_bl_init()
83 * PWM Backlight control and register specific PWM and backlight device.
84 * @gpio_info: structure containing GPIO info for PWM timer
/linux-4.4.14/drivers/mfd/
H A Dlm3533-ctrlbank.c133 * PWM-input control mask:
135 * bit 5 - PWM-input enabled in Zone 4
136 * bit 4 - PWM-input enabled in Zone 3
137 * bit 3 - PWM-input enabled in Zone 2
138 * bit 2 - PWM-input enabled in Zone 1
139 * bit 1 - PWM-input enabled in Zone 0
140 * bit 0 - PWM-input enabled
142 lm3533_ctrlbank_set(pwm, PWM);
143 lm3533_ctrlbank_get(pwm, PWM);
H A Dlp3943.c14 * It can be used for a GPIO expander and PWM generators.
21 * --- PWM generator leds-pwm eg) PWM input
23 * Internal two PWM channels are used for LED dimming effect.
28 * Alternatively, it can be used for generic GPIO and PWM controller.
30 * A PWM is input pin of a backlight device.
H A Dintel_soc_pmic_core.c42 /* PWM consumed by the Intel GFX */
H A Dwm8997-tables.c168 { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
169 { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
170 { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dgpio.h33 /* so far, "param" seems to only have an influence on PWM-related
35 * if param equals 1, hardware PWM is available
H A Dvolt.h19 /* PWM mode */
/linux-4.4.14/arch/unicore32/include/mach/
H A Dregs-ost.h38 * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
87 * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE
/linux-4.4.14/include/sound/
H A Dmax9768.h14 * @flags: configuration flags, e.g. set classic PWM mode (check datasheet
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A Dpwm-core.h4 * Samsung PWM controller platform data helpers.
/linux-4.4.14/include/linux/regulator/
H A Dtps51632-regulator.h34 * @enable_pwm_dvfs: Enable PWM DVFS or not.
36 * @max_voltage_uV: Maximum possible voltage in PWM-DVFS mode.
37 * @base_voltage_uV: Base voltage when PWM-DVFS enabled.
/linux-4.4.14/drivers/scsi/ufs/
H A Dunipro.h130 UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
131 UFS_PWM_G2, /* PWM Gear 2 */
132 UFS_PWM_G3, /* PWM Gear 3 */
133 UFS_PWM_G4, /* PWM Gear 4 */
134 UFS_PWM_G5, /* PWM Gear 5 */
135 UFS_PWM_G6, /* PWM Gear 6 */
136 UFS_PWM_G7, /* PWM Gear 7 */
H A Dufs-qcom.c645 * here qcom_param->desired_working_mode is PWM. ufs_qcom_get_pwr_dev_param()
646 * it doesn't matter whether device supports HS or PWM, ufs_qcom_get_pwr_dev_param()
669 * both HS or both PWM then set the minimum gear to be the chosen ufs_qcom_get_pwr_dev_param()
671 * if one is PWM and one is HS then the one that is PWM get to decide ufs_qcom_get_pwr_dev_param()
720 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */ ufs_qcom_get_speed_mode()
738 "PWM", gear, lanes); ufs_qcom_get_speed_mode()
/linux-4.4.14/drivers/video/backlight/
H A Dpandora_bl.c71 * set PWM duty cycle to max. TPS61161 seems to use this pandora_backlight_update_status()
72 * to calibrate it's PWM sensitivity when it starts. pandora_backlight_update_status()
86 * it often triggers unintentionally and disabes PWM control, pandora_backlight_update_status()
133 /* enable PWM function in pin mux */ pandora_backlight_probe()
H A Dpwm_bl.c4 * simple PWM based backlight control, board code has to setup
5 * 1) pin configuration so PWM waveforms can output
276 dev_err(&pdev->dev, "unable to request PWM, trying legacy API\n"); pwm_backlight_probe()
284 dev_err(&pdev->dev, "unable to request PWM\n"); pwm_backlight_probe()
292 * period, parsed from the DT, in the PWM device. For the non-DT case, pwm_backlight_probe()
294 * via the PWM lookup table. pwm_backlight_probe()
407 MODULE_DESCRIPTION("PWM based Backlight Driver");
H A Dlp8788_bl.c139 /* request PWM device with the consumer name */ lp8788_pwm_ctrl()
143 dev_err(dev, "can not get PWM device\n"); lp8788_pwm_ctrl()
235 strmode = "PWM based"; lp8788_get_bl_ctl_mode()
H A Dot200_bl.c52 /* enable or disable PWM timer */ ot200_backlight_update_status()
H A Dtps65217_bl.c166 /* set PWM frequency */ tps65217_bl_hw_init()
174 "failed to select PWM dimming frequency: %d\n", tps65217_bl_hw_init()
/linux-4.4.14/drivers/clk/
H A Dclk-pwm.c8 * PWM (mis)used as clock output
75 dev_err(&pdev->dev, "invalid PWM period\n"); clk_pwm_probe()
85 "clock-frequency does not match PWM period\n"); clk_pwm_probe()
135 MODULE_DESCRIPTION("PWM clock driver");
/linux-4.4.14/drivers/hwmon/
H A Dabituguru3.c215 { "PWM", 26, 1, 1, 1, 0 },
266 { "PWM", 26, 1, 1, 1, 0 },
288 { "PWM", 26, 1, 1, 1, 0 },
308 { "PWM", 26, 1, 1, 1, 0 },
334 { "PWM", 27, 1, 1, 1, 0 },
358 { "PWM", 26, 1, 1, 1, 0 },
409 { "PWM", 26, 1, 1, 1, 0 },
430 { "PWM", 26, 1, 1, 1, 0 },
484 { "PWM", 27, 1, 1, 1, 0 },
507 { "PWM Phase1", 26, 1, 1, 1, 0 },
508 { "PWM Phase2", 27, 1, 1, 1, 0 },
509 { "PWM Phase3", 28, 1, 1, 1, 0 },
510 { "PWM Phase4", 29, 1, 1, 1, 0 },
511 { "PWM Phase5", 30, 1, 1, 1, 0 },
534 { "PWM Phase1", 26, 1, 1, 1, 0 },
535 { "PWM Phase2", 27, 1, 1, 1, 0 },
536 { "PWM Phase3", 28, 1, 1, 1, 0 },
537 { "PWM Phase4", 29, 1, 1, 1, 0 },
538 { "PWM Phase5", 30, 1, 1, 1, 0 },
561 { "PWM", 26, 1, 1, 1, 0 },
562 { "PWM Phase2", 27, 1, 1, 1, 0 },
563 { "PWM Phase3", 28, 1, 1, 1, 0 },
564 { "PWM Phase4", 29, 1, 1, 1, 0 },
565 { "PWM Phase5", 30, 1, 1, 1, 0 },
589 { "PWM Phase1", 26, 1, 1, 1, 0 },
590 { "PWM Phase2", 27, 1, 1, 1, 0 },
591 { "PWM Phase3", 28, 1, 1, 1, 0 },
592 { "PWM Phase4", 29, 1, 1, 1, 0 },
593 { "PWM Phase5", 30, 1, 1, 1, 0 },
616 { "PWM Phase1", 26, 1, 1, 1, 0 },
617 { "PWM Phase2", 27, 1, 1, 1, 0 },
618 { "PWM Phase3", 28, 1, 1, 1, 0 },
619 { "PWM Phase4", 29, 1, 1, 1, 0 },
620 { "PWM Phase5", 30, 1, 1, 1, 0 },
H A Dpwm-fan.c2 * pwm-fan.c - Hwmon driver for fans connected to PWM lines.
203 dev_err(dev, "PWM fan state[%d]:%d > %d\n", i, pwm_fan_of_get_cooling_data()
230 dev_err(&pdev->dev, "Could not get PWM\n"); pwm_fan_probe()
242 dev_err(&pdev->dev, "Failed to configure PWM\n"); pwm_fan_probe()
246 /* Enbale PWM output */ pwm_fan_probe()
249 dev_err(&pdev->dev, "Failed to enable PWM\n"); pwm_fan_probe()
342 MODULE_DESCRIPTION("PWM FAN driver");
H A Dlm85.c177 * PWM value at limit/low temp, 1 count
178 * PWM Frequency, 1. Hz
179 * PWM is Min or OFF below limit, flag
180 * Invert PWM output, flag
198 /* These are the PWM frequency encodings */
221 * 1 -- PWM responds to Zone 1
222 * 2 -- PWM responds to Zone 2
223 * 3 -- PWM responds to Zone 3
224 * 23 -- PWM responds to the higher temp of Zone 2 or 3
225 * 123 -- PWM responds to highest of Zone 1, 2, or 3
226 * 0 -- PWM is always at 0% (ie, off)
227 * -1 -- PWM is always at 100%
228 * -2 -- PWM responds to manual control
258 * given the automatic PWM fan control that is possible. There
285 u8 min_pwm; /* Minimum PWM value, encoded */
286 u8 min_off; /* Min PWM or OFF below "limit", flag */
726 case -1: /* PWM is always at 100% */ show_pwm_enable()
729 case 0: /* PWM is always at 0% */ show_pwm_enable()
730 case -2: /* PWM responds to manual control */ show_pwm_enable()
733 default: /* PWM in automatic mode */ show_pwm_enable()
812 * The ADT7468 has a special high-frequency PWM output mode, set_pwm_freq()
813 * where all PWM outputs are driven by a 22.5 kHz clock. set_pwm_freq()
1016 /* Automatic PWM control */
1125 /* Temperature settings for automatic PWM control */
H A Dg760a.c3 * fan speed PWM controller chip
51 u8 set_cnt; /* PWM (period) count number; 0xff stops fan */
H A Dmax6639.c4 * 2-Channel Temperature Monitor with Dual PWM Fan-Speed Controller
456 /* Fans config PWM, RPM */ max6639_init_client()
463 /* Fans PWM polarity high by default */ max6639_init_client()
475 * PWM frequency 25kHz, see also GCONFIG below max6639_init_client()
502 /* PWM 120/120 (i.e. 100%) */ max6639_init_client()
H A Dw83791d.c124 0x81, /* PWM 1 duty cycle register in DataSheet */
125 0x83, /* PWM 2 duty cycle register in DataSheet */
126 0x94, /* PWM 3 duty cycle register in DataSheet */
127 0xA0, /* PWM 4 duty cycle register in DataSheet */
128 0xA1, /* PWM 5 duty cycle register in DataSheet */
132 0x85, /* PWM 1 target temperature for temp 1 */
133 0x86, /* PWM 2 target temperature for temp 2 */
134 0x96, /* PWM 3 target temperature for temp 3 */
138 0x87, /* PWM 1/2 temperature tolerance */
139 0x97, /* PWM 3 temperature tolerance */
1571 /* Update PWM duty cycle */ w83791d_update_device()
1577 /* Update PWM enable status */ w83791d_update_device()
1586 /* Update PWM target temperature */ w83791d_update_device()
1592 /* Update PWM temperature tolerance */ w83791d_update_device()
H A Ddme1737.c418 * PWM enable
444 * PWM auto channels zone
470 /* PWM frequency */
499 * PWM ramp rate
525 /* PWM ramp rate enable */ PWM_RR_EN_FROM_REG()
539 * PWM min/off
540 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
712 /* PWM registers */ dme1737_update_device()
1192 * PWM sysfs attributes
1300 "PWM enable %ld not supported. Choose one of 0, 1, or 2.\n", set_pwm()
1329 /* Set the new PWM mode */ set_pwm()
1364 /* Enable PWM ramp rate if previously enabled */ set_pwm()
1389 * Enable/disable the feature only if the associated PWM set_pwm()
1405 "PWM auto channels zone %ld not supported. Choose one of 1, 2, 4, 6, " set_pwm()
1414 * PWM is already in auto mode so update the temp set_pwm()
1423 * PWM is not in auto mode so we save the temp set_pwm()
1803 * The following structs hold the PWM attributes, some of which are optional.
1860 * The following struct holds auto PWM min attributes, which are not available
1962 * The permissions of the following PWM attributes are changed to read-
1963 * writeable if the chip is *not* locked and the respective PWM is available.
2165 /* Create PWM sysfs attributes */ dme1737_create_files()
2207 /* Change permissions of PWM sysfs attributes */ dme1737_create_files()
2373 /* Initialize the default PWM auto channels zone (acz) assignments */ dme1737_init_device()
H A Dpc87427.c219 * PWM registers and conversions
234 * Dedicated function to read all registers related to a given PWM output.
366 /* PWM outputs */ pc87427_update_device()
631 "Can't set PWM%d duty cycle while not in manual mode\n", set_pwm()
642 dev_dbg(dev, "Switching PWM%d from %s to %s\n", nr + 1, set_pwm()
648 dev_dbg(dev, "Switching PWM%d from %s to %s\n", nr + 1, set_pwm()
1018 /* Check which PWM outputs are enabled */ pc87427_init_device()
1033 dev_dbg(dev, "PWM%d is in automatic control mode\n", pc87427_init_device()
H A Dg762.c3 * PWM controller chips from G762 family, i.e. G762 and G763
79 #define G762_REG_FAN_CMD1_OUT_MODE 0x20 /* out mode: PWM or DC */
83 #define G762_REG_FAN_CMD1_PWM_POLARITY 0x02 /* PWM polarity */
164 * 5: OUT_MODE 1:PWM, 0:DC
281 /* Set pwm mode. Accepts either 0 (PWM mode) or 1 (DC mode) */ do_set_pwm_mode()
437 * only in PWM mode). To workaround this bug, we give SET_CNT do_set_pwm_enable()
458 /* Set PWM polarity. Accepts either 0 (positive duty) or 1 (negative duty) */ do_set_pwm_polarity()
762 * control mode i.e. PWM (1) or DC (0).
H A Dit87.c181 /* Not all BIOSes properly configure the PWM registers */
476 * Starting with the IT8721F, the manual PWM duty cycles are stored
482 u8 pwm_duty[3]; /* Manual PWM value set by user */
483 u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */
568 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
569 * depending on the chip type, to calculate the actual PWM frequency.
572 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
573 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
1094 * If we are in automatic mode, the PWM duty cycle register set_pwm()
2291 /* Check PWM configuration */ it87_probe()
2481 /* Return 1 if and only if the PWM interface is safe to use */ it87_check_pwm()
2509 * PWM interface). it87_check_pwm()
2513 "Reconfiguring PWM to active high polarity\n"); it87_check_pwm()
2524 "PWM configuration is too broken to be fixed\n"); it87_check_pwm()
2528 "Detected broken BIOS defaults, disabling PWM interface\n"); it87_check_pwm()
2532 "PWM configuration looks sane, won't touch\n"); it87_check_pwm()
2547 * For each PWM channel: it87_init_device()
2856 "Force PWM polarity to active high (DANGEROUS)");
H A Dsmsc47m1.c212 * This chip (stupidly) stops monitoring fan speed if PWM is get_fan()
805 dev_dbg(dev, "PWM 1 not enabled by hardware, skipping\n"); smsc47m1_probe()
813 dev_dbg(dev, "PWM 2 not enabled by hardware, skipping\n"); smsc47m1_probe()
821 dev_dbg(dev, "PWM 3 not enabled by hardware, skipping\n"); smsc47m1_probe()
H A Dadt7475.c731 /* Remote1 controls PWM */ hw_set_pwm()
735 /* local controls PWM */ hw_set_pwm()
739 /* remote2 controls PWM */ hw_set_pwm()
743 /* local/remote2 control PWM */ hw_set_pwm()
747 /* All three control PWM */ hw_set_pwm()
783 /* Read Modify Write PWM values */ set_pwmchan()
806 /* Read Modify Write PWM values */ set_pwmctrl()
816 /* List of frequencies for the PWM */
H A Dabituguru.c67 /* uGuru fan PWM (speed control) flags */
258 /* Fan PWM (speed control) 5 bytes per PWM */
627 * memory storing the PWM settings when reading/writing to a PWM which is not
628 * there. Notice even if we detect a PWM which doesn't exist we normally won't
704 ABIT_UGURU_DEBUG(2, "assuming %d PWM outputs because of " abituguru_detect_no_pwms()
709 ABIT_UGURU_DEBUG(2, "detecting number of PWM outputs\n"); abituguru_detect_no_pwms()
790 ABIT_UGURU_DEBUG(2, " found: %d PWM outputs\n", (int)data->pwms); abituguru_detect_no_pwms()
1032 /* Fan PWM (speed control) */ show_pwm_setting()
H A Dvt1211.c594 * PWM sysfs interfaces
666 * disable SmartGuardian if both PWM outputs are set_pwm()
734 * PWM auto point definitions
742 * PWM controllers. We still create 2 sets of sysfs files to make it look
806 * Note that the PWM auto points 0 & 3 are hard-wired in the VT1211 and can't
H A Dadm1031.c56 #define ADM1031_CONF1_PWM_INVERT 0x08 /* PWM Invert */
374 * Save PWM registers set_fan_auto_channel()
375 * Set PWM registers to 33% Both set_fan_auto_channel()
384 /* Restore PWM registers */ set_fan_auto_channel()
507 /* In automatic mode, the only PWM accepted is 33% */ set_pwm()
H A Df71882fg.c359 /* PWM and Auto point control */
593 /* Fan / PWM attr common to all models */
661 * PWM attr for the f71862fg, fewer pwms and fewer zones per pwm than the
733 * PWM attr for the f71808e/f71869, almost identical to the f71862fg, but the
814 /* PWM attr for the standard models */
987 * PWM attr for the f8000, zones mapped to temp instead of to pwm!
1808 /* PWM mode */ show_pwm()
1841 /* PWM mode */ store_pwm()
1935 /* Special case for F8000 auto PWM mode / Thermostat mode */ store_pwm_enable()
1985 /* PWM mode */ show_pwm_auto_point_pwm()
2014 /* PWM mode */ store_pwm_auto_point_pwm()
H A Dlm63.c316 * temperatures and PWM output values.
1075 * For LM96163, check if high resolution PWM lm63_init_client()
1096 dev_dbg(dev, "PWM clock %s kHz, output frequency %u Hz\n", lm63_init_client()
1099 dev_dbg(dev, "PWM output active %s, %s mode\n", lm63_init_client()
H A Df71805f.c738 if (val > 1) { /* Automatic mode, user can't set PWM value */ set_pwm_enable()
762 if (val == 1) { /* Manual mode, user can set PWM value */ set_pwm_enable()
1322 * created conditionally (only if pwm_mode is 1 == PWM)
1453 /* If control mode is PWM, create pwm_freq file */ f71805f_probe()
1460 /* If PWM is in manual mode, add write permission */ f71805f_probe()
H A Dlm93.c122 /* #PROCHOT & #VRDHOT PWM ramp control */
292 /* Temperature Zone Min. PWM & Hysteresis (register format) */
295 /* #PROCHOT & #VRDHOT PWM Ramp Control */
304 * The two PWM CTL2 registers can read something other than what was
561 * PWM: 0-255 per sensors documentation
632 * PWM FREQ: HZ
991 /* Temperature Zone Min. PWM & Hysteresis registers */ lm93_update_client_common()
997 /* #PROCHOT & #VRDHOT PWM Ramp Control register */ lm93_update_client_common()
1946 ctl2 |= 0xF1; /* enable manual override, set PWM to max */ store_pwm_enable()
H A Dthmc50.c168 /* There is only one PWM mode = DC */ show_pwm_mode()
H A Dasb100.c162 * PWM: 0 - 255 per sensors documentation
552 /* 1 PWM */ show_pwm1()
1003 /* PWM */ asb100_update_device()
H A Dnct7904.c382 /* PWM ATTR */ store_pwm()
/linux-4.4.14/drivers/regulator/
H A Dpwm-regulator.c2 * Regulator driver for PWM Regulators
66 dev_err(&rdev->dev, "Failed to configure PWM\n"); pwm_regulator_set_voltage_sel()
142 dev_err(&rdev->dev, "Failed to configure PWM\n"); pwm_regulator_set_voltage()
148 dev_err(&rdev->dev, "Failed to enable PWM\n"); pwm_regulator_set_voltage()
153 /* Delay required by PWM regulator to settle to the new voltage */ pwm_regulator_set_voltage()
267 dev_err(&pdev->dev, "Failed to get PWM\n"); pwm_regulator_probe()
300 MODULE_DESCRIPTION("PWM Regulator Driver");
H A Dwm8400-regulator.c57 /* Datasheet: active with or without force PWM */ wm8400_dcdc_get_mode()
72 /* Datasheet: active with force PWM */ wm8400_dcdc_set_mode()
H A Dtps62360-regulator.c182 /* Enable force PWM mode in FAST mode only. */ tps62360_set_mode()
/linux-4.4.14/drivers/leds/
H A Dleds-pwm.c4 * simple PWM based LED control
119 dev_err(dev, "unable to request PWM for %s: %d\n", led_pwm_add()
136 dev_err(dev, "failed to register PWM led for %s: %d\n", led_pwm_add()
239 MODULE_DESCRIPTION("PWM LED driver for PXA");
H A Dleds-pca955x.c31 * NUM_INPUT_REGS + 1 PWM register 0
33 * NUM_INPUT_REGS + 3 PWM register 1
144 * period of the PWM output. period = (PSCx + 1) / 38
156 * Write to PWM register, which determines the duty cycle of the
H A Dleds-lp3944.c42 #define LP3944_REG_PWM0 0x03 /* PWM Register 0 (R/W) */
44 #define LP3944_REG_PWM1 0x05 /* PWM Register 1 (R/W) */
153 /* Convert duty cycle to PWM value */ lp3944_dim_set_dutycycle()
H A Dleds-da903x.c61 val |= (0x7 - (led->new_brightness >> 5)) & 0x7; /* PWM<2:0> */ da903x_led_work()
H A Dleds-lp5521.c64 #define LP5521_LOGARITHMIC_PWM 0x80 /* Logarithmic PWM adjustment */
72 #define LP5521_PWM_HF 0x40 /* PWM: 0 = 256Hz, 1 = 558Hz */
330 /* Initialize all channels PWM to zero -> leds off */ lp5521_post_init_device()
H A Dleds-lp5562.c35 #define LP5562_LOGARITHMIC_PWM 0x80 /* Logarithmic PWM adjustment */
302 /* Initialize all channels PWM to zero -> leds off */ lp5562_post_init_device()
308 /* Set LED map as register PWM by default */ lp5562_post_init_device()
H A Dleds-pca963x.c43 #define PCA963X_LED_PWM 0x2 /* Controlled through PWM */
44 #define PCA963X_LED_GRP_PWM 0x3 /* Controlled through PWM/GRPPWM */
H A Dleds-lm3530.c101 * @mode: mode of operation - manual, ALS, PWM
H A Dleds-pca9532.c196 /* Thecus specific: only use PSC/PWM 0 */ pca9532_set_blink()
/linux-4.4.14/include/linux/mfd/
H A Dlp8788-isink.h30 /* 6 bits used for PWM code : Addr 9C ~ 9Eh */
H A Dmax8997.h126 * @pwm_channel_id: channel number of PWM device
128 * @pwm_period: period in nano second for PWM device
132 * MAX8997_EXTERNAL_MODE: external PWM device is used to control motor
134 * @pwm_divisor: divisor for external PWM device
H A Dlm3533.h45 unsigned pwm_mode:1; /* PWM input mode (default analog) */
46 u8 r_select; /* 1 - 127 (ignored in PWM-mode) */
H A Dlp3943.h63 * @output: Output pins which are mapped to each PWM channel
73 * @pwms: Output channel definitions for PWM channel 0 and 1
H A Dlp8788.h97 LP8788_BL_COMB_PWM_BASED, /* PWM + I2C, changed by PWM input */
98 LP8788_BL_COMB_REGISTER_BASED, /* PWM + I2C, changed by I2C */
272 * @pwm_code : PWM code value (Addr 9Ch ~ 9Eh)
H A D88pm80x.h113 /* PWM register */
/linux-4.4.14/drivers/input/misc/
H A Dpwm-beeper.c3 * PWM beeper driver
108 dev_dbg(&pdev->dev, "unable to request PWM, trying legacy API\n"); pwm_beeper_probe()
218 MODULE_DESCRIPTION("PWM beeper driver");
H A Dtwl4030-vibra.c59 /* Disable LEDA & LEDB, cannot be used with vibra (PWM) */ vibra_disable_leds()
125 /* set PWM, 1 = max, 255 = min */ vibra_play_work()
H A Dmax8997_haptic.c193 dev_err(chip->dev, "Failed to enable PWM\n"); max8997_haptic_enable()
305 "unable to request PWM for haptic, error: %d\n", max8997_haptic_probe()
/linux-4.4.14/include/linux/platform_data/
H A Dlp855x.h107 LP8555_COMBINED1, /* Brightness register with shaped PWM */
108 LP8555_COMBINED2, /* PWM with shaped brightness register */
/linux-4.4.14/drivers/media/dvb-frontends/
H A Dves1x93.h39 /* should PWM be inverted? */
H A Ddibx000_common.h253 * used to do the PWM. Direction gives the PWModulator to be used.
254 * Value gives the PWM value in device-dependent scale.
H A Dts2020.h65 * AGC PWM tuner input as theoretically output by the demodulator.
H A Datbm8830.c402 dprintk("AGC PWM = 0x%02X\n", pwm); atbm8830_read_signal_strength()
H A Dves1820.c443 MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
/linux-4.4.14/drivers/input/keyboard/
H A Dlm8323.c57 #define LM8323_CMD_PWM_WRITE 0x95 /* Write PWM script. */
58 #define LM8323_CMD_START_PWM 0x96 /* Start PWM engine. */
59 #define LM8323_CMD_STOP_PWM 0x97 /* Stop PWM engine. */
99 /* Commands for PWM engine; feed in with PWM_WRITE. */
435 * Write a script into a given PWM engine, concluding with PWM_END.
438 * will be kept running at the final PWM level indefinitely.
465 * case we will be called again when the previous PWM script lm8323_pwm_work()
523 * Schedule PWM work as usual unless we are going into suspend lm8323_pwm_set_brightness()
591 dev_err(dev, "couldn't register PWM %d\n", id); init_pwm()
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A Dirq.h66 #define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
67 #define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
H A DdefBF512.h1187 /* Motor Control PWM Registers */
1189 #define PWM_CTRL 0xffc03700 /* PWM Control Register */
1190 #define PWM_STAT 0xffc03704 /* PWM Status Register */
1191 #define PWM_TM 0xffc03708 /* PWM Period Register */
1192 #define PWM_DT 0xffc0370c /* PWM Dead Time Register */
1193 #define PWM_GATE 0xffc03710 /* PWM Chopping Control */
1194 #define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
1195 #define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
1196 #define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
1197 #define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
1198 #define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
1199 #define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
1200 #define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
1201 #define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
1202 #define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
1203 #define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
H A Dportmux.h172 /* PWM */
/linux-4.4.14/drivers/clocksource/
H A Dsamsung_pwm_timer.c381 * PWM master driver
391 panic("failed to find PWM channel for clocksource"); _samsung_pwm_clocksource_init()
397 panic("failed to find PWM channel for clock event"); _samsung_pwm_clocksource_init()
443 pr_err("%s: failed to map PWM registers\n", __func__); samsung_pwm_alloc()
/linux-4.4.14/arch/unicore32/kernel/
H A Dpuv3-nb0916.c54 PWM_LOOKUP("PKUnity-v3-PWM", 0, "pwm-backlight", NULL, 70 * 1024,
H A Dpuv3-core.c268 platform_device_register_simple("PKUnity-v3-PWM", -1, puv3_core_init()
/linux-4.4.14/arch/avr32/mach-at32ap/include/mach/
H A Dboard.h64 /* mask says which PWM channels to mux */
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Dusbdux.c68 * 1.1: moved EP4 transfers to EP1 to make space for a PWM output on EP4
69 * 1.2: added PWM support via EP4
70 * 2.0: PWM seems to be stable and is not interfering with the other functions
71 * 2.1: changed PWM API
110 /* 300Hz max frequ under PWM */
113 /* Default PWM frequency */
187 /* PWM period */
189 /* PWM internal delay for the GPIF in the FX2 */
191 /* size of the PWM buffer which holds the bit pattern */
1291 char pwm_mask = (1 << chan); /* DIO bit for the PWM data */ usbdux_pwm_pattern()
1320 * because it would just overwrite the PWM buffer. usbdux_pwm_write()
1345 * if not zero the PWM is limited to a certain time which is usbdux_pwm_config()
1669 /* PWM subdevice */ usbdux_auto_attach()
H A Dc6xdigio.c173 * There are only 2 PWM channels and they have a maxdata of 500. c6xdigio_pwm_insn_write()
222 /* Initialize the PWM */ c6xdigio_init()
H A Dusbduxsigma.c68 /* 300Hz max frequ under PWM */
71 /* Default PWM frequency */
150 /* PWM period */
152 /* PWM internal delay for the GPIF in the FX2 */
154 /* size of the PWM buffer which holds the bit pattern */
1133 char pwm_mask = (1 << chan); /* DIO bit for the PWM data */ usbduxsigma_pwm_pattern()
1162 * because it would just overwrite the PWM buffer. usbduxsigma_pwm_write()
1187 * if not zero the PWM is limited to a certain time which is usbduxsigma_pwm_config()
H A Ds526.c31 * PWM output works
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_panel.c570 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); intel_panel_get_backlight()
656 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); intel_panel_actually_set_backlight()
736 * Although we don't support or enable CPU PWM with LPT/SPT based lpt_disable_backlight()
740 * This needs rework if we need to add support for CPU PWM on PCH split lpt_disable_backlight()
1054 * enabled with PWM mode. bxt_enable_backlight()
1267 * SPT: This value represents the period of the PWM stream in clock periods
1269 * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
1288 * LPT: This value represents the period of the PWM stream in clock periods
1312 * ILK/SNB/IVB: This value represents the period of the PWM stream in PCH
1346 * Gen4: This value represents the period of the PWM stream in display core
1359 * VLV: This value represents the period of the PWM stream in display core
1657 /* Get the PWM chip for backlight control */ pwm_setup_backlight()
H A Dintel_opregion.c115 u32 pfmb; /* PWM freq and min brightness */
168 /* PWM frequency and minimum brightness */
458 DRM_DEBUG_DRIVER("PWM freq is not supported\n"); asle_set_pwm_freq()
/linux-4.4.14/drivers/macintosh/
H A Drack-meter.c11 * TODO: Implement PWM to do variable intensity and provide userland
233 * we'll do better once we have actual PWM implemented rackmeter_do_timer()
311 /* XXX FIXME: No PWM yet, this is 0/1 */ rackmeter_calc_sample()
358 * into the PWM bitmap for each LED. rackmeter_irq()
H A Dwindfarm_smu_controls.c288 /* Look for PWM fans */ smu_controls_init()
299 "PWM fan %s\n", fan->name); smu_controls_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dfanpwm.c105 fan->base.type = "PWM"; nvkm_fanpwm_create()
H A Dgf119.c48 nvkm_error(subdev, "GPIO %d unknown PWM: %08x\n", line, gpio); pwm_info()
H A Dnv50.c101 /* determine the PWM source clock */ nv50_fan_pwm_clock()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dgk104.c114 mode = "PWM"; gk104_volt_new()
/linux-4.4.14/include/linux/mfd/wm8350/
H A Dpmic.h580 * R248 (0xF8) - DCDC1 Force PWM
585 * R250 (0xFA) - DCDC3 Force PWM
590 * R251 (0xFB) - DCDC4 Force PWM
595 * R253 (0xFD) - DCDC1 Force PWM
/linux-4.4.14/arch/arm/mach-pxa/
H A Dpalmt5.c94 /* PWM */
H A Dcolibri-pxa270.c118 /* PWM */
H A Dpalmld.c88 /* PWM */
H A Dmagician.c72 /* PWM 0 - LCD backlight */
399 * LCD PWM backlight (main)
H A Dmxm8x10.c165 PWM - Leave unconfigured for now...
H A Dpalmtc.c80 /* PWM */
H A Dpalmte2.c64 /* PWM */
H A Dpalmtx.c82 /* PWM */
H A Dpalmz72.c87 /* PWM */
H A Draumfeld.c540 /* PWM controlled backlight */
618 * by an LT3593, earlier and later devices use PWM for that. */ raumfeld_lcd_init()
H A Dpalmtreo.c79 /* PWM */
H A Dpcm990-baseboard.c176 * - GPIO16 is output for back light on/off with PWM
H A Dz2.c78 /* PWM */
/linux-4.4.14/arch/arm/mach-w90x900/include/mach/
H A Dmap.h127 /* Pulse Width Modulation(PWM) Registers */
/linux-4.4.14/drivers/gpio/
H A Dgpio-twl4030.c136 * external pullup is needed. We could also expose the integrated PWM
225 /* initialize PWM to always-drive */ twl_request()
226 /* Configure PWM OFF register first */ twl_request()
231 /* Followed by PWM ON register */ twl_request()
/linux-4.4.14/include/linux/i2c/
H A Dadp8870.h110 u8 pwm_assign; /* 1 = Enables PWM mode */
/linux-4.4.14/arch/m68k/include/asm/
H A DMC68328.h642 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
647 * PWM Control Register
654 #define PWMC_PWMEN 0x0010 /* Enable PWM */
655 #define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
656 #define PWMC_PIN 0x0080 /* Current PWM output pin status */
665 * PWM Period Register
671 * PWM Width Register
677 * PWM Counter Register
H A DMC68EZ328.h506 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
511 * PWM Control Register
520 #define PWMC_EN 0x0010 /* Enable PWM */
532 * PWM Sample Register
538 * PWM Period Register
544 * PWM Counter Register
997 * PWM Contrast Control Register
H A Dmac_via.h83 * on Macs which had the PWM sound hardware. Reserved on newer models.
91 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
100 * PWM hardware) 0=enabled.
H A DMC68VZ328.h599 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
604 * PWM Control Register
613 #define PWMC_EN 0x0010 /* Enable PWM */
625 * PWM Sample Register
631 * PWM Period Register
637 * PWM Counter Register
1093 * PWM Contrast Control Register
/linux-4.4.14/arch/avr32/boards/atngw100/
H A Dmrmt.c158 /* PWM LEDs: LCD Backlight, etc */
334 /* Use PWM for Backlight controls */ mrmt1_init()
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A Dpxa3xx-regs.h189 #define CKEN_PWM0 32 /* < PWM[0] clock enable */
190 #define CKEN_PWM1 33 /* < PWM[1] clock enable */
H A Dmfp-pxa25x.h90 /* PWM 0/1 */
/linux-4.4.14/drivers/hwmon/pmbus/
H A Ducd9200.c2 * Hardware monitoring driver for ucd9200 series Digital PWM System Controllers
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dpptable.h85 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
88 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments).
89 USHORT usPWMMed; // The PWM value (in percent) at TMed.
90 USHORT usPWMHigh; // The PWM value at THigh.
H A Datombios.h2795 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2796 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2798 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2799 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2801 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2802 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2805 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2806 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2870 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2919 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2921 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2922 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2924 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2927 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3525 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
4890 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4891 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4897 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5114 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5115 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5121 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5207 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
5315 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5316 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5322 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5412 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
/linux-4.4.14/drivers/gpu/drm/amd/include/
H A Dpptable.h85 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
88 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments).
89 USHORT usPWMMed; // The PWM value (in percent) at TMed.
90 USHORT usPWMHigh; // The PWM value at THigh.
H A Datombios.h2878 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2879 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2881 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2882 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2884 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2885 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2888 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2889 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2953 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
3002 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
3004 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
3005 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
3007 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
3010 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3646 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
5149 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5150 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5156 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5378 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5379 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5385 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5471 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
5580 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5581 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5587 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5677 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
/linux-4.4.14/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c224 /* [6]PWM function control by DPCD0040f[7], default is PWM block */ ps8622_send_config()
291 /* DPCD720, internal PWM */ ps8622_send_config()
302 /* DPCD720, external PWM */ ps8622_send_config()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dsmu.h56 * arg=0x11: read PWM fans status
57 * arg=0x12: read PWM fans setpoint
67 * first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the
246 * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
/linux-4.4.14/arch/mips/jz4740/
H A Dplatform.c298 /* PWM */
/linux-4.4.14/arch/mips/loongson32/common/
H A Dtime.c222 /* setup LS1X PWM timer */ plat_time_init()
/linux-4.4.14/arch/powerpc/boot/
H A Dcuboot-acadia.c39 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Dopregion.c95 u32 pfmb; /* PWM freq and min brightness */
138 /* PWM frequency and minimum brightness */
H A Dtc35876x-dsi-lvds.c447 /* Make sure the PWM reference is the 19.2 MHz system clock. Read first tc35876x_brightness_init()
448 * instead of setting directly to catch potential conflicts between PWM tc35876x_brightness_init()
485 /* PWM duty cycle 0x00...0x63 corresponds to 0...99% */ tc35876x_brightness_control()
H A Dcdv_device.c94 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n"); cdv_get_max_backlight()
96 * smash PWM control as firmware will take control of it. */ cdv_get_max_backlight()
H A Dcdv_intel_lvds.c153 * Set LVDS backlight level either by I2C or PWM
762 /* setup PWM */ cdv_intel_lvds_init()
H A Doaktrail_lvds.c34 /* The max/min PWM frequency in BPCR[31:17] - */
/linux-4.4.14/sound/soc/codecs/
H A Dtas5086.c19 * - implement non-default PWM start
83 #define TAS5086_PWM_START 0x18 /* PWM start register */
498 * configure 'part 1' of the PWM starts to use Mid-Z, and tell tas5086_init()
703 /* Channel muxes -> PWM muxes */
746 /* The PWM muxes are directly connected to the PWM outputs */
H A Dsta529.c151 SOC_ENUM("PWM Select", pwm_src),
H A Dab8500-codec.c355 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
882 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
883 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
1698 SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1702 SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
/linux-4.4.14/drivers/staging/comedi/
H A Dcomedi.h220 /* re recycle these flags for PWM */
221 #define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */
222 #define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */
239 COMEDI_SUBD_PWM /* PWM */
290 /* PWM */
/linux-4.4.14/drivers/video/fbdev/
H A Dssd1307fb.c293 dev_err(&par->client->dev, "Could not get PWM from device tree!\n"); ssd1307fb_init()
298 /* Enable the PWM */ ssd1307fb_init()
302 dev_dbg(&par->client->dev, "Using PWM%d with a %dns period.\n", ssd1307fb_init()
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A Dmach-rx1950.c480 /* Warm up backlight for one period of PWM. rx1950_bl_power()
495 dev_err(dev, "Unable to request PWM for LCD power!\n"); rx1950_backlight_init()
/linux-4.4.14/drivers/staging/fbtft/
H A Dfb_ra8875.c170 /* PWM clock */ init_display()
/linux-4.4.14/drivers/video/fbdev/mbx/
H A Dregs.h51 /* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
/linux-4.4.14/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-mt6397.h311 PINCTRL_PIN(30, "PWM3(PWM)"),
/linux-4.4.14/arch/arm/mach-mmp/include/mach/
H A Dmfp-pxa910.h161 /* PWM */
/linux-4.4.14/arch/arm/mach-clps711x/
H A Dboard-p720t.c69 #define PLD_PWR_MODE (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-tegra20.c2076 MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
2133 MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
2134 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
2135 MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
2156 MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
H A Dpinctrl-palmas.c313 FUNCTION_GROUP(pwm, PWM), \
477 PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
478 PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
/linux-4.4.14/arch/arm/mach-davinci/include/mach/
H A Dmux.h251 /* PWM */

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