1/*
2 * PKUnity Operating System Timer (OST) Registers
3 */
4/*
5 * Match Reg 0 OST_OSMR0
6 */
7#define OST_OSMR0	(PKUNITY_OST_BASE + 0x0000)
8/*
9 * Match Reg 1 OST_OSMR1
10 */
11#define OST_OSMR1	(PKUNITY_OST_BASE + 0x0004)
12/*
13 * Match Reg 2 OST_OSMR2
14 */
15#define OST_OSMR2	(PKUNITY_OST_BASE + 0x0008)
16/*
17 * Match Reg 3 OST_OSMR3
18 */
19#define OST_OSMR3	(PKUNITY_OST_BASE + 0x000C)
20/*
21 * Counter Reg OST_OSCR
22 */
23#define OST_OSCR	(PKUNITY_OST_BASE + 0x0010)
24/*
25 * Status Reg OST_OSSR
26 */
27#define OST_OSSR	(PKUNITY_OST_BASE + 0x0014)
28/*
29 * Watchdog Enable Reg OST_OWER
30 */
31#define OST_OWER	(PKUNITY_OST_BASE + 0x0018)
32/*
33 * Interrupt Enable Reg OST_OIER
34 */
35#define OST_OIER	(PKUNITY_OST_BASE + 0x001C)
36
37/*
38 * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
39 *      PWCR: Pulse Width Control Reg
40 *      DCCR: Duty Cycle Control Reg
41 *      PCR: Period Control Reg
42 */
43#define OST_PWM_PWCR	(0x00)
44#define OST_PWM_DCCR	(0x04)
45#define OST_PWM_PCR 	(0x08)
46
47/*
48 * Match detected 0 OST_OSSR_M0
49 */
50#define OST_OSSR_M0		FIELD(1, 1, 0)
51/*
52 * Match detected 1 OST_OSSR_M1
53 */
54#define OST_OSSR_M1		FIELD(1, 1, 1)
55/*
56 * Match detected 2 OST_OSSR_M2
57 */
58#define OST_OSSR_M2		FIELD(1, 1, 2)
59/*
60 * Match detected 3 OST_OSSR_M3
61 */
62#define OST_OSSR_M3		FIELD(1, 1, 3)
63
64/*
65 * Interrupt enable 0 OST_OIER_E0
66 */
67#define OST_OIER_E0		FIELD(1, 1, 0)
68/*
69 * Interrupt enable 1 OST_OIER_E1
70 */
71#define OST_OIER_E1		FIELD(1, 1, 1)
72/*
73 * Interrupt enable 2 OST_OIER_E2
74 */
75#define OST_OIER_E2		FIELD(1, 1, 2)
76/*
77 * Interrupt enable 3 OST_OIER_E3
78 */
79#define OST_OIER_E3		FIELD(1, 1, 3)
80
81/*
82 * Watchdog Match Enable OST_OWER_WME
83 */
84#define OST_OWER_WME		FIELD(1, 1, 0)
85
86/*
87 * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE
88 */
89#define OST_PWMDCCR_FDCYCLE	FIELD(1, 1, 10)
90
91