1/*
2 * arch/arm/mach-w90x900/include/mach/map.h
3 *
4 * Copyright (c) 2008 Nuvoton technology corporation.
5 *
6 * Wan ZongShun <mcuos.com@gmail.com>
7 *
8 * Based on arch/arm/mach-s3c2410/include/mach/map.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation;version 2 of the License.
13 *
14 */
15
16#ifndef __ASM_ARCH_MAP_H
17#define __ASM_ARCH_MAP_H
18
19#ifndef __ASSEMBLY__
20#define W90X900_ADDR(x)		((void __iomem *)(0xF0000000 + (x)))
21#else
22#define W90X900_ADDR(x)		(0xF0000000 + (x))
23#endif
24
25#define AHB_IO_BASE		0xB0000000
26#define APB_IO_BASE		0xB8000000
27#define CLOCKPW_BASE		(APB_IO_BASE+0x200)
28#define AIC_IO_BASE		(APB_IO_BASE+0x2000)
29#define TIMER_IO_BASE		(APB_IO_BASE+0x1000)
30
31/*
32 * interrupt controller is the first thing we put in, to make
33 * the assembly code for the irq detection easier
34 */
35#define W90X900_VA_IRQ		W90X900_ADDR(0x00000000)
36#define W90X900_PA_IRQ		(0xB8002000)
37#define W90X900_SZ_IRQ		SZ_4K
38
39#define W90X900_VA_GCR		W90X900_ADDR(0x08002000)
40#define W90X900_PA_GCR		(0xB0000000)
41#define W90X900_SZ_GCR		SZ_4K
42
43/* Clock and Power management */
44#define W90X900_VA_CLKPWR	(W90X900_VA_GCR+0x200)
45#define W90X900_PA_CLKPWR	(0xB0000200)
46#define W90X900_SZ_CLKPWR	SZ_4K
47
48/* EBI management */
49#define W90X900_VA_EBI		W90X900_ADDR(0x00001000)
50#define W90X900_PA_EBI		(0xB0001000)
51#define W90X900_SZ_EBI		SZ_4K
52
53/* UARTs */
54#define W90X900_VA_UART		W90X900_ADDR(0x08000000)
55#define W90X900_PA_UART		(0xB8000000)
56#define W90X900_SZ_UART		SZ_4K
57
58/* Timers */
59#define W90X900_VA_TIMER	W90X900_ADDR(0x08001000)
60#define W90X900_PA_TIMER	(0xB8001000)
61#define W90X900_SZ_TIMER	SZ_4K
62
63/* GPIO ports */
64#define W90X900_VA_GPIO		W90X900_ADDR(0x08003000)
65#define W90X900_PA_GPIO		(0xB8003000)
66#define W90X900_SZ_GPIO		SZ_4K
67
68/* GDMA control */
69#define W90X900_VA_GDMA		W90X900_ADDR(0x00004000)
70#define W90X900_PA_GDMA		(0xB0004000)
71#define W90X900_SZ_GDMA		SZ_4K
72
73/* USB host controller*/
74#define W90X900_VA_USBEHCIHOST	W90X900_ADDR(0x00005000)
75#define W90X900_PA_USBEHCIHOST	(0xB0005000)
76#define W90X900_SZ_USBEHCIHOST	SZ_4K
77
78#define W90X900_VA_USBOHCIHOST	W90X900_ADDR(0x00007000)
79#define W90X900_PA_USBOHCIHOST	(0xB0007000)
80#define W90X900_SZ_USBOHCIHOST	SZ_4K
81
82/* I2C hardware controller */
83#define W90X900_VA_I2C		W90X900_ADDR(0x08006000)
84#define W90X900_PA_I2C		(0xB8006000)
85#define W90X900_SZ_I2C		SZ_4K
86
87/* Keypad Interface*/
88#define W90X900_VA_KPI		W90X900_ADDR(0x08008000)
89#define W90X900_PA_KPI		(0xB8008000)
90#define W90X900_SZ_KPI		SZ_4K
91
92/* Smart card host*/
93#define W90X900_VA_SC		W90X900_ADDR(0x08005000)
94#define W90X900_PA_SC		(0xB8005000)
95#define W90X900_SZ_SC		SZ_4K
96
97/* LCD controller*/
98#define W90X900_VA_LCD		W90X900_ADDR(0x00008000)
99#define W90X900_PA_LCD		(0xB0008000)
100#define W90X900_SZ_LCD		SZ_4K
101
102/* 2D controller*/
103#define W90X900_VA_GE		W90X900_ADDR(0x0000B000)
104#define W90X900_PA_GE		(0xB000B000)
105#define W90X900_SZ_GE		SZ_4K
106
107/* ATAPI */
108#define W90X900_VA_ATAPI	W90X900_ADDR(0x0000A000)
109#define W90X900_PA_ATAPI	(0xB000A000)
110#define W90X900_SZ_ATAPI	SZ_4K
111
112/* ADC */
113#define W90X900_VA_ADC		W90X900_ADDR(0x0800A000)
114#define W90X900_PA_ADC		(0xB800A000)
115#define W90X900_SZ_ADC		SZ_4K
116
117/* PS2 Interface*/
118#define W90X900_VA_PS2		W90X900_ADDR(0x08009000)
119#define W90X900_PA_PS2		(0xB8009000)
120#define W90X900_SZ_PS2		SZ_4K
121
122/* RTC */
123#define W90X900_VA_RTC		W90X900_ADDR(0x08004000)
124#define W90X900_PA_RTC		(0xB8004000)
125#define W90X900_SZ_RTC		SZ_4K
126
127/* Pulse Width Modulation(PWM) Registers */
128#define W90X900_VA_PWM		W90X900_ADDR(0x08007000)
129#define W90X900_PA_PWM		(0xB8007000)
130#define W90X900_SZ_PWM		SZ_4K
131
132/* Audio Controller controller */
133#define W90X900_VA_ACTL		W90X900_ADDR(0x00009000)
134#define W90X900_PA_ACTL		(0xB0009000)
135#define W90X900_SZ_ACTL		SZ_4K
136
137/* DMA controller */
138#define W90X900_VA_DMA		W90X900_ADDR(0x0000c000)
139#define W90X900_PA_DMA		(0xB000c000)
140#define W90X900_SZ_DMA		SZ_4K
141
142/* FMI controller */
143#define W90X900_VA_FMI		W90X900_ADDR(0x0000d000)
144#define W90X900_PA_FMI		(0xB000d000)
145#define W90X900_SZ_FMI		SZ_4K
146
147/* USB Device port */
148#define W90X900_VA_USBDEV	W90X900_ADDR(0x00006000)
149#define W90X900_PA_USBDEV	(0xB0006000)
150#define W90X900_SZ_USBDEV	SZ_4K
151
152/* External MAC control*/
153#define W90X900_VA_EMC		W90X900_ADDR(0x00003000)
154#define W90X900_PA_EMC		(0xB0003000)
155#define W90X900_SZ_EMC		SZ_4K
156
157#endif /* __ASM_ARCH_MAP_H */
158