| /linux-4.4.14/arch/arm/mach-s3c64xx/include/mach/ |
| H A D | pm-core.h | 27 * clock sources, we simply enable PCLK at the moment and hope s3c_pm_debug_init_uart()
29 * use with PCLK. s3c_pm_debug_init_uart()
78 * between UCLKx and PCLK, so ensure that when we restore UCON s3c_pm_arch_update_uart()
86 /* change from UCLKx => wrong PCLK, s3c_pm_arch_update_uart()
95 * PCLK2 => PCLK or vice-versa */ s3c_pm_arch_update_uart()
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| H A D | regs-clock.h | 28 /* PCLK GATE Registers */
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| /linux-4.4.14/arch/x86/include/asm/ |
| H A D | apb_timer.h | 27 /* APBT clock speed range from PCLK to fabric base, 25-100MHz */
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| /linux-4.4.14/arch/arm/mach-mv78xx0/ |
| H A D | common.c | 83 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 get_pclk_l2clk()
84 * PCLK/L2CLK by bits [19:14]. get_pclk_l2clk()
93 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK get_pclk_l2clk()
99 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK get_pclk_l2clk()
403 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); mv78xx0_init()
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| /linux-4.4.14/arch/arm/mach-lpc32xx/ |
| H A D | pm.c | 23 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
24 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
28 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
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| H A D | timer.c | 102 * it to compute the PLL frequency and the PCLK divider to get the base lpc32xx_timer_init()
114 /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */ lpc32xx_timer_init()
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| H A D | clock.c | 47 * USB host/device PCLK& |
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
1258 /* Compute HCLK and PCLK bus rates */ clk_init()
1271 printk(KERN_ERR "Error enabling system HCLK and PCLK\n"); clk_init()
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| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 31 #define PCLK 9 macro
65 /* PCLK bus clocks. */
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| H A D | s3c2410.h | 29 #define PCLK 6 macro
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| H A D | s3c2412.h | 31 #define PCLK 8 macro
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| H A D | s3c2443.h | 28 #define PCLK 6 macro
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| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 31 #define PCLK 9 macro
65 /* PCLK bus clocks. */
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| H A D | s3c2410.h | 29 #define PCLK 6 macro
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| H A D | s3c2412.h | 31 #define PCLK 8 macro
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| H A D | s3c2443.h | 28 #define PCLK 6 macro
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| /linux-4.4.14/include/media/davinci/ |
| H A D | vpss.h | 69 * en = 0 disable internal PCLK
70 * en = 1 enables internal PCLK
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| /linux-4.4.14/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 31 #define PCLK 9 macro
65 /* PCLK bus clocks. */
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| H A D | s3c2410.h | 29 #define PCLK 6 macro
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| H A D | s3c2412.h | 31 #define PCLK 8 macro
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| H A D | s3c2443.h | 28 #define PCLK 6 macro
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| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 31 #define PCLK 9 macro
65 /* PCLK bus clocks. */
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| H A D | s3c2410.h | 29 #define PCLK 6 macro
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| H A D | s3c2412.h | 31 #define PCLK 8 macro
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| H A D | s3c2443.h | 28 #define PCLK 6 macro
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| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 31 #define PCLK 9 macro
65 /* PCLK bus clocks. */
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| H A D | s3c2410.h | 29 #define PCLK 6 macro
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| H A D | s3c2412.h | 31 #define PCLK 8 macro
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| H A D | s3c2443.h | 28 #define PCLK 6 macro
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| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 31 #define PCLK 9 macro
65 /* PCLK bus clocks. */
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| H A D | s3c2410.h | 29 #define PCLK 6 macro
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| H A D | s3c2412.h | 31 #define PCLK 8 macro
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| H A D | s3c2443.h | 28 #define PCLK 6 macro
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| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 31 #define PCLK 9 macro
65 /* PCLK bus clocks. */
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| H A D | s3c2410.h | 29 #define PCLK 6 macro
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| H A D | s3c2412.h | 31 #define PCLK 8 macro
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| H A D | s3c2443.h | 28 #define PCLK 6 macro
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| /linux-4.4.14/drivers/clk/versatile/ |
| H A D | clk-impd1.c | 99 /* Register the fixed rate PCLK */ integrator_impd1_clk_init()
139 /* The GPIO blocks and AACI have only PCLK */ integrator_impd1_clk_init()
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| /linux-4.4.14/drivers/gpu/drm/msm/dsi/ |
| H A D | mmss_cc.xml.h | 50 PCLK = 1, enumerator in enum:mmss_cc_clk
59 case PCLK: return 0x00000130; __offset_CLK()
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| /linux-4.4.14/arch/arm/plat-samsung/include/plat/ |
| H A D | cpu-freq.h | 26 * @pclk: The PCLK frequency in Hz.
74 * @p_divisor: Divisor from FCLK to PCLK.
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| /linux-4.4.14/drivers/clocksource/ |
| H A D | asm9260_timer.c | 45 * next positive edge of PCLK. The counters remain reset until TCR[1] is
102 #define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */
214 /* make sure all timers use every rising PCLK edge. */ asm9260_timer_init()
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| H A D | moxart_timer.c | 41 * TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK
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| /linux-4.4.14/drivers/clk/tegra/ |
| H A D | clk-tegra-super-gen4.c | 84 /* PCLK */ tegra_sclk_init()
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| /linux-4.4.14/drivers/cpufreq/ |
| H A D | s3c24xx-cpufreq-debugfs.c | 90 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); info_show()
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| /linux-4.4.14/sound/soc/samsung/ |
| H A D | smartq_wm8987.c | 59 /* Use PCLK for I2S signal generation */ smartq_hifi_hw_params()
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| H A D | neo1973_wm8753.c | 96 /* codec PLL input is PCLK/4 */ neo1973_hifi_hw_params()
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| H A D | s3c24xx_uda134x.c | 166 clk_source == S3C24XX_CLKSRC_MPLL ? "MPLLin" : "PCLK", s3c24xx_uda134x_hw_params()
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| /linux-4.4.14/drivers/clk/samsung/ |
| H A D | clk-s3c2410.c | 116 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
153 ALIAS(PCLK, NULL, "watchdog"),
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| H A D | clk-s3c64xx.c | 230 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
384 ALIAS(PCLK, NULL, "pclk"),
385 ALIAS(PCLK, NULL, "clk_uart_baud2"),
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| H A D | clk-s3c2412.c | 109 DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
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| H A D | clk-s3c2443.c | 148 DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
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| /linux-4.4.14/drivers/media/i2c/soc_camera/ |
| H A D | ov2640.c | 111 #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
216 #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
218 * PCLK (user can latch data at the next
219 * falling edge of PCLK).
241 #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
242 #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
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| H A D | mt9t112.c | 644 * PCLK: 73MHz mt9t112_init_setting()
813 /* Invert PCLK (Data sampled on falling edge of pixclk) */ mt9t112_s_stream()
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| /linux-4.4.14/drivers/video/fbdev/omap2/dss/ |
| H A D | sdi.c | 181 * LCLK and PCLK divisors are located in shadow registers, and we sdi_display_enable()
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| H A D | dss.c | 296 udelay(1); /* wait 2x PCLK */ dss_sdi_enable()
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| /linux-4.4.14/arch/m68k/atari/ |
| H A D | debug.c | 209 /* reg 14: 0 = RTxC, 2 = PCLK */ atari_init_scc_port()
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| /linux-4.4.14/arch/avr32/mach-at32ap/include/mach/ |
| H A D | at32ap700x.h | 228 ATMEL_LCDC(PC, PCLK))
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| /linux-4.4.14/drivers/video/fbdev/omap2/displays-new/ |
| H A D | panel-sony-acx565akm.c | 577 * 3. Providing PCLK,HS,VS signals for 2 frames = ~50msec worst acx565akm_panel_power_on()
608 * We have to provide PCLK,HS,VS signals for 2 frames (worst case acx565akm_panel_power_off()
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| /linux-4.4.14/drivers/media/i2c/ |
| H A D | vs6624_regs.h | 302 #define VS6624_PCLK_SETUP 0x258A /* PCLK setup */
303 #define VS6624_PCLK_EN 0x258C /* PCLK enable */
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| H A D | ov7670.c | 87 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
124 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
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| H A D | ov9650.c | 90 #define REG_COM10 0x15 /* PCLK, HREF, HSYNC signals polarity */
92 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
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| /linux-4.4.14/drivers/media/usb/stkwebcam/ |
| H A D | stk-sensor.c | 134 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
175 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
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| /linux-4.4.14/drivers/i2c/busses/ |
| H A D | i2c-riic.c | 86 /* ICBRx (@ PCLK 33MHz) */
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| H A D | i2c-jz4780.c | 270 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk) jz4780_i2c_set_speed()
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| /linux-4.4.14/drivers/pinctrl/sunxi/ |
| H A D | pinctrl-sun5i-a13.c | 248 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
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| H A D | pinctrl-sun8i-a23.c | 346 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
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| H A D | pinctrl-sun8i-a33.c | 268 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
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| H A D | pinctrl-sun6i-a31s.c | 476 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
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| H A D | pinctrl-sun8i-a83t.c | 309 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
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| H A D | pinctrl-sun9i-a80.c | 398 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
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| H A D | pinctrl-sun4i-a10.c | 882 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
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| H A D | pinctrl-sun6i-a31.c | 553 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
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| H A D | pinctrl-sun7i-a20.c | 891 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
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| /linux-4.4.14/arch/m32r/include/asm/ |
| H A D | s1d13806.h | 10 // Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
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| /linux-4.4.14/drivers/video/fbdev/omap/ |
| H A D | lcd_mipid.c | 199 * controller can still provide the PCLK,HS,VS signals. set_sleep_mode()
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| /linux-4.4.14/arch/arm/mach-ep93xx/ |
| H A D | clock.c | 556 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", ep93xx_clock_init()
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| /linux-4.4.14/sound/soc/codecs/ |
| H A D | max98090.c | 1522 /* Check for supported PCLK to LRCLK ratios */ max98090_configure_bclk()
1527 "Found supported PCLK to LRCLK rates 0x%x\n", max98090_configure_bclk()
1544 "Found user supported PCLK to LRCLK rates\n"); max98090_configure_bclk()
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| /linux-4.4.14/drivers/soc/tegra/ |
| H A D | pmc.c | 484 /* must be at least 200 ns, in APB (PCLK) clock cycles */ tegra_io_rail_prepare()
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| /linux-4.4.14/drivers/video/fbdev/matrox/ |
| H A D | matroxfb_Ti3026.c | 521 /* stop PCLK */ ti3026_setMCLK()
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| /linux-4.4.14/drivers/media/usb/gspca/ |
| H A D | ov519.c | 753 * = 0 (0x00) ......0. "Tri-state VSYNC, PCLK,
832 * COMK[5] "PCLK output selection"
833 * = 0 (0x00) ..0..... "PCLK always output"
834 * COMK[4] "PCLK edge selection"
1188 * provides PCLK"
1189 * CLKRC[5:0] "Clock divider { CLK = PCLK/(1+CLKRC[5:0]) }"
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| H A D | spca561.c | 136 {0x0003, 0x8701}, /* PCLK clock delay adjustment */
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| /linux-4.4.14/arch/m68k/kernel/ |
| H A D | head.S | 2738 /* Initialisation table for SCC with 3.6864 MHz PCLK */
2761 /* Initialisation table for SCC with 7.9872 MHz PCLK */
2762 /* PCLK == 8.0539 gives baud == 9680.1 */
2868 /* Wait for 5 PCLK cycles, which is about 63 CPU cycles */
2907 /* Wait for 5 PCLK cycles, which is about 68 CPU cycles */
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| /linux-4.4.14/drivers/media/platform/soc_camera/ |
| H A D | pxa_camera.c | 1360 /* If PCLK is used to latch data from the sensor, check sense */ pxa_camera_set_crop()
1440 /* If PCLK is used to latch data from the sensor, check sense */ pxa_camera_set_fmt()
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| /linux-4.4.14/drivers/tty/serial/ |
| H A D | zs.c | 100 #define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */
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| /linux-4.4.14/drivers/clk/spear/ |
| H A D | spear1310_clock.c | 234 /* PCLK 24MHz */
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| H A D | spear1340_clock.c | 167 /* PCLK 24MHz */
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| /linux-4.4.14/drivers/gpu/drm/tegra/ |
| H A D | sor.c | 401 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ tegra_sor_setup_pwm()
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| /linux-4.4.14/drivers/net/hamradio/ |
| H A D | scc.c | 742 wr(scc, R14, BRSRC); /* BRG source = PCLK */ init_brg()
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| /linux-4.4.14/drivers/pci/ |
| H A D | quirks.c | 2113 /* Set PCI Master Bus time-out to "1x16 PCLK" */ quirk_via_cx700_pci_parking_caching()
|