1/* 2 * arch/arm/mach-spear13xx/spear1310_clock.c 3 * 4 * SPEAr1310 machine clock framework source file 5 * 6 * Copyright (C) 2012 ST Microelectronics 7 * Viresh Kumar <vireshk@kernel.org> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14#include <linux/clkdev.h> 15#include <linux/err.h> 16#include <linux/io.h> 17#include <linux/of_platform.h> 18#include <linux/spinlock_types.h> 19#include "clk.h" 20 21/* PLL related registers and bit values */ 22#define SPEAR1310_PLL_CFG (misc_base + 0x210) 23 /* PLL_CFG bit values */ 24 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 25 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 26 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2 27 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29 28 #define SPEAR1310_RAS_SYNT_CLK_MASK 2 29 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27 30 #define SPEAR1310_PLL_CLK_MASK 2 31 #define SPEAR1310_PLL3_CLK_SHIFT 24 32 #define SPEAR1310_PLL2_CLK_SHIFT 22 33 #define SPEAR1310_PLL1_CLK_SHIFT 20 34 35#define SPEAR1310_PLL1_CTR (misc_base + 0x214) 36#define SPEAR1310_PLL1_FRQ (misc_base + 0x218) 37#define SPEAR1310_PLL2_CTR (misc_base + 0x220) 38#define SPEAR1310_PLL2_FRQ (misc_base + 0x224) 39#define SPEAR1310_PLL3_CTR (misc_base + 0x22C) 40#define SPEAR1310_PLL3_FRQ (misc_base + 0x230) 41#define SPEAR1310_PLL4_CTR (misc_base + 0x238) 42#define SPEAR1310_PLL4_FRQ (misc_base + 0x23C) 43#define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244) 44 /* PERIP_CLK_CFG bit values */ 45 #define SPEAR1310_GPT_OSC24_VAL 0 46 #define SPEAR1310_GPT_APB_VAL 1 47 #define SPEAR1310_GPT_CLK_MASK 1 48 #define SPEAR1310_GPT3_CLK_SHIFT 11 49 #define SPEAR1310_GPT2_CLK_SHIFT 10 50 #define SPEAR1310_GPT1_CLK_SHIFT 9 51 #define SPEAR1310_GPT0_CLK_SHIFT 8 52 #define SPEAR1310_UART_CLK_PLL5_VAL 0 53 #define SPEAR1310_UART_CLK_OSC24_VAL 1 54 #define SPEAR1310_UART_CLK_SYNT_VAL 2 55 #define SPEAR1310_UART_CLK_MASK 2 56 #define SPEAR1310_UART_CLK_SHIFT 4 57 58 #define SPEAR1310_AUX_CLK_PLL5_VAL 0 59 #define SPEAR1310_AUX_CLK_SYNT_VAL 1 60 #define SPEAR1310_CLCD_CLK_MASK 2 61 #define SPEAR1310_CLCD_CLK_SHIFT 2 62 #define SPEAR1310_C3_CLK_MASK 1 63 #define SPEAR1310_C3_CLK_SHIFT 1 64 65#define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248) 66 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 67 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 68 #define SPEAR1310_GMAC_PHY_CLK_MASK 1 69 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3 70 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 71 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 72 73#define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C) 74 /* I2S_CLK_CFG register mask */ 75 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F 76 #define SPEAR1310_I2S_SCLK_X_SHIFT 27 77 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F 78 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22 79 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21 80 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20 81 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF 82 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12 83 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF 84 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4 85 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3 86 #define SPEAR1310_I2S_REF_SEL_MASK 1 87 #define SPEAR1310_I2S_REF_SHIFT 2 88 #define SPEAR1310_I2S_SRC_CLK_MASK 2 89 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 90 91#define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250) 92#define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254) 93#define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258) 94#define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C) 95#define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260) 96#define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264) 97#define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268) 98#define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270) 99#define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280) 100#define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288) 101#define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290) 102#define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298) 103 /* Check Fractional synthesizer reg masks */ 104 105#define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300) 106 /* PERIP1_CLK_ENB register masks */ 107 #define SPEAR1310_RTC_CLK_ENB 31 108 #define SPEAR1310_ADC_CLK_ENB 30 109 #define SPEAR1310_C3_CLK_ENB 29 110 #define SPEAR1310_JPEG_CLK_ENB 28 111 #define SPEAR1310_CLCD_CLK_ENB 27 112 #define SPEAR1310_DMA_CLK_ENB 25 113 #define SPEAR1310_GPIO1_CLK_ENB 24 114 #define SPEAR1310_GPIO0_CLK_ENB 23 115 #define SPEAR1310_GPT1_CLK_ENB 22 116 #define SPEAR1310_GPT0_CLK_ENB 21 117 #define SPEAR1310_I2S0_CLK_ENB 20 118 #define SPEAR1310_I2S1_CLK_ENB 19 119 #define SPEAR1310_I2C0_CLK_ENB 18 120 #define SPEAR1310_SSP_CLK_ENB 17 121 #define SPEAR1310_UART_CLK_ENB 15 122 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14 123 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13 124 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12 125 #define SPEAR1310_UOC_CLK_ENB 11 126 #define SPEAR1310_UHC1_CLK_ENB 10 127 #define SPEAR1310_UHC0_CLK_ENB 9 128 #define SPEAR1310_GMAC_CLK_ENB 8 129 #define SPEAR1310_CFXD_CLK_ENB 7 130 #define SPEAR1310_SDHCI_CLK_ENB 6 131 #define SPEAR1310_SMI_CLK_ENB 5 132 #define SPEAR1310_FSMC_CLK_ENB 4 133 #define SPEAR1310_SYSRAM0_CLK_ENB 3 134 #define SPEAR1310_SYSRAM1_CLK_ENB 2 135 #define SPEAR1310_SYSROM_CLK_ENB 1 136 #define SPEAR1310_BUS_CLK_ENB 0 137 138#define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304) 139 /* PERIP2_CLK_ENB register masks */ 140 #define SPEAR1310_THSENS_CLK_ENB 8 141 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 142 #define SPEAR1310_ACP_CLK_ENB 6 143 #define SPEAR1310_GPT3_CLK_ENB 5 144 #define SPEAR1310_GPT2_CLK_ENB 4 145 #define SPEAR1310_KBD_CLK_ENB 3 146 #define SPEAR1310_CPU_DBG_CLK_ENB 2 147 #define SPEAR1310_DDR_CORE_CLK_ENB 1 148 #define SPEAR1310_DDR_CTRL_CLK_ENB 0 149 150#define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310) 151 /* RAS_CLK_ENB register masks */ 152 #define SPEAR1310_SYNT3_CLK_ENB 17 153 #define SPEAR1310_SYNT2_CLK_ENB 16 154 #define SPEAR1310_SYNT1_CLK_ENB 15 155 #define SPEAR1310_SYNT0_CLK_ENB 14 156 #define SPEAR1310_PCLK3_CLK_ENB 13 157 #define SPEAR1310_PCLK2_CLK_ENB 12 158 #define SPEAR1310_PCLK1_CLK_ENB 11 159 #define SPEAR1310_PCLK0_CLK_ENB 10 160 #define SPEAR1310_PLL3_CLK_ENB 9 161 #define SPEAR1310_PLL2_CLK_ENB 8 162 #define SPEAR1310_C125M_PAD_CLK_ENB 7 163 #define SPEAR1310_C30M_CLK_ENB 6 164 #define SPEAR1310_C48M_CLK_ENB 5 165 #define SPEAR1310_OSC_25M_CLK_ENB 4 166 #define SPEAR1310_OSC_32K_CLK_ENB 3 167 #define SPEAR1310_OSC_24M_CLK_ENB 2 168 #define SPEAR1310_PCLK_CLK_ENB 1 169 #define SPEAR1310_ACLK_CLK_ENB 0 170 171/* RAS Area Control Register */ 172#define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000) 173 #define SPEAR1310_SSP1_CLK_MASK 3 174 #define SPEAR1310_SSP1_CLK_SHIFT 26 175 #define SPEAR1310_TDM_CLK_MASK 1 176 #define SPEAR1310_TDM2_CLK_SHIFT 24 177 #define SPEAR1310_TDM1_CLK_SHIFT 23 178 #define SPEAR1310_I2C_CLK_MASK 1 179 #define SPEAR1310_I2C7_CLK_SHIFT 22 180 #define SPEAR1310_I2C6_CLK_SHIFT 21 181 #define SPEAR1310_I2C5_CLK_SHIFT 20 182 #define SPEAR1310_I2C4_CLK_SHIFT 19 183 #define SPEAR1310_I2C3_CLK_SHIFT 18 184 #define SPEAR1310_I2C2_CLK_SHIFT 17 185 #define SPEAR1310_I2C1_CLK_SHIFT 16 186 #define SPEAR1310_GPT64_CLK_MASK 1 187 #define SPEAR1310_GPT64_CLK_SHIFT 15 188 #define SPEAR1310_RAS_UART_CLK_MASK 1 189 #define SPEAR1310_UART5_CLK_SHIFT 14 190 #define SPEAR1310_UART4_CLK_SHIFT 13 191 #define SPEAR1310_UART3_CLK_SHIFT 12 192 #define SPEAR1310_UART2_CLK_SHIFT 11 193 #define SPEAR1310_UART1_CLK_SHIFT 10 194 #define SPEAR1310_PCI_CLK_MASK 1 195 #define SPEAR1310_PCI_CLK_SHIFT 0 196 197#define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004) 198 #define SPEAR1310_PHY_CLK_MASK 0x3 199 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 200 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 201 202#define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148) 203 #define SPEAR1310_CAN1_CLK_ENB 25 204 #define SPEAR1310_CAN0_CLK_ENB 24 205 #define SPEAR1310_GPT64_CLK_ENB 23 206 #define SPEAR1310_SSP1_CLK_ENB 22 207 #define SPEAR1310_I2C7_CLK_ENB 21 208 #define SPEAR1310_I2C6_CLK_ENB 20 209 #define SPEAR1310_I2C5_CLK_ENB 19 210 #define SPEAR1310_I2C4_CLK_ENB 18 211 #define SPEAR1310_I2C3_CLK_ENB 17 212 #define SPEAR1310_I2C2_CLK_ENB 16 213 #define SPEAR1310_I2C1_CLK_ENB 15 214 #define SPEAR1310_UART5_CLK_ENB 14 215 #define SPEAR1310_UART4_CLK_ENB 13 216 #define SPEAR1310_UART3_CLK_ENB 12 217 #define SPEAR1310_UART2_CLK_ENB 11 218 #define SPEAR1310_UART1_CLK_ENB 10 219 #define SPEAR1310_RS485_1_CLK_ENB 9 220 #define SPEAR1310_RS485_0_CLK_ENB 8 221 #define SPEAR1310_TDM2_CLK_ENB 7 222 #define SPEAR1310_TDM1_CLK_ENB 6 223 #define SPEAR1310_PCI_CLK_ENB 5 224 #define SPEAR1310_GMII_CLK_ENB 4 225 #define SPEAR1310_MII2_CLK_ENB 3 226 #define SPEAR1310_MII1_CLK_ENB 2 227 #define SPEAR1310_MII0_CLK_ENB 1 228 #define SPEAR1310_ESRAM_CLK_ENB 0 229 230static DEFINE_SPINLOCK(_lock); 231 232/* pll rate configuration table, in ascending order of rates */ 233static struct pll_rate_tbl pll_rtbl[] = { 234 /* PCLK 24MHz */ 235 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ 236 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ 237 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ 238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ 239 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ 240 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ 241 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 242}; 243 244/* vco-pll4 rate configuration table, in ascending order of rates */ 245static struct pll_rate_tbl pll4_rtbl[] = { 246 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ 247 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ 248 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ 249 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 250}; 251 252/* aux rate configuration table, in ascending order of rates */ 253static struct aux_rate_tbl aux_rtbl[] = { 254 /* For VCO1div2 = 500 MHz */ 255 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ 256 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ 257 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ 258 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ 259 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ 260 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ 261}; 262 263/* gmac rate configuration table, in ascending order of rates */ 264static struct aux_rate_tbl gmac_rtbl[] = { 265 /* For gmac phy input clk */ 266 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 267 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 268 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 269 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 270}; 271 272/* clcd rate configuration table, in ascending order of rates */ 273static struct frac_rate_tbl clcd_rtbl[] = { 274 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 275 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 276 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 277 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ 278 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ 279 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 280 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 281 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ 282 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ 283 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 284}; 285 286/* i2s prescaler1 masks */ 287static struct aux_clk_masks i2s_prs1_masks = { 288 .eq_sel_mask = AUX_EQ_SEL_MASK, 289 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT, 290 .eq1_mask = AUX_EQ1_SEL, 291 .eq2_mask = AUX_EQ2_SEL, 292 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK, 293 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT, 294 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK, 295 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT, 296}; 297 298/* i2s sclk (bit clock) syynthesizers masks */ 299static struct aux_clk_masks i2s_sclk_masks = { 300 .eq_sel_mask = AUX_EQ_SEL_MASK, 301 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT, 302 .eq1_mask = AUX_EQ1_SEL, 303 .eq2_mask = AUX_EQ2_SEL, 304 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK, 305 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT, 306 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK, 307 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT, 308 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB, 309}; 310 311/* i2s prs1 aux rate configuration table, in ascending order of rates */ 312static struct aux_rate_tbl i2s_prs1_rtbl[] = { 313 /* For parent clk = 49.152 MHz */ 314 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */ 315 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */ 316 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */ 317 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */ 318 319 /* 320 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz 321 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz 322 */ 323 {.xscale = 1, .yscale = 3, .eq = 0}, 324 325 /* For parent clk = 49.152 MHz */ 326 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/ 327 328 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */ 329}; 330 331/* i2s sclk aux rate configuration table, in ascending order of rates */ 332static struct aux_rate_tbl i2s_sclk_rtbl[] = { 333 /* For i2s_ref_clk = 12.288MHz */ 334 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */ 335 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */ 336}; 337 338/* adc rate configuration table, in ascending order of rates */ 339/* possible adc range is 2.5 MHz to 20 MHz. */ 340static struct aux_rate_tbl adc_rtbl[] = { 341 /* For ahb = 166.67 MHz */ 342 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 343 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 344 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 345 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 346}; 347 348/* General synth rate configuration table, in ascending order of rates */ 349static struct frac_rate_tbl gen_rtbl[] = { 350 /* For vco1div4 = 250 MHz */ 351 {.div = 0x14000}, /* 25 MHz */ 352 {.div = 0x0A000}, /* 50 MHz */ 353 {.div = 0x05000}, /* 100 MHz */ 354 {.div = 0x02000}, /* 250 MHz */ 355}; 356 357/* clock parents */ 358static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 359static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 360static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; 361static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; 362static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", 363 "osc_25m_clk", }; 364static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; 365static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 366static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; 367static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk", 368 "i2s_src_pad_clk", }; 369static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; 370static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 371 "pll3_clk", }; 372static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", 373 "pll2_clk", }; 374static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none", 375 "ras_pll2_clk", "ras_syn0_clk", }; 376static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk", 377 "ras_pll2_clk", "ras_syn0_clk", }; 378static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; 379static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", }; 380static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk", 381 "ras_plclk0_clk", }; 382static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; 383static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; 384 385void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) 386{ 387 struct clk *clk, *clk1; 388 389 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 390 32000); 391 clk_register_clkdev(clk, "osc_32k_clk", NULL); 392 393 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, 394 24000000); 395 clk_register_clkdev(clk, "osc_24m_clk", NULL); 396 397 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, 398 25000000); 399 clk_register_clkdev(clk, "osc_25m_clk", NULL); 400 401 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, 402 125000000); 403 clk_register_clkdev(clk, "gmii_pad_clk", NULL); 404 405 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 406 CLK_IS_ROOT, 12288000); 407 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); 408 409 /* clock derived from 32 KHz osc clk */ 410 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 411 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, 412 &_lock); 413 clk_register_clkdev(clk, NULL, "e0580000.rtc"); 414 415 /* clock derived from 24 or 25 MHz osc clk */ 416 /* vco-pll */ 417 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 418 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 419 SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT, 420 SPEAR1310_PLL_CLK_MASK, 0, &_lock); 421 clk_register_clkdev(clk, "vco1_mclk", NULL); 422 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 423 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, 424 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 425 clk_register_clkdev(clk, "vco1_clk", NULL); 426 clk_register_clkdev(clk1, "pll1_clk", NULL); 427 428 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 429 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 430 SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT, 431 SPEAR1310_PLL_CLK_MASK, 0, &_lock); 432 clk_register_clkdev(clk, "vco2_mclk", NULL); 433 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 434 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, 435 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 436 clk_register_clkdev(clk, "vco2_clk", NULL); 437 clk_register_clkdev(clk1, "pll2_clk", NULL); 438 439 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 440 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 441 SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT, 442 SPEAR1310_PLL_CLK_MASK, 0, &_lock); 443 clk_register_clkdev(clk, "vco3_mclk", NULL); 444 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 445 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, 446 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 447 clk_register_clkdev(clk, "vco3_clk", NULL); 448 clk_register_clkdev(clk1, "pll3_clk", NULL); 449 450 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 451 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl, 452 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); 453 clk_register_clkdev(clk, "vco4_clk", NULL); 454 clk_register_clkdev(clk1, "pll4_clk", NULL); 455 456 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 457 48000000); 458 clk_register_clkdev(clk, "pll5_clk", NULL); 459 460 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 461 25000000); 462 clk_register_clkdev(clk, "pll6_clk", NULL); 463 464 /* vco div n clocks */ 465 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 466 2); 467 clk_register_clkdev(clk, "vco1div2_clk", NULL); 468 469 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 470 4); 471 clk_register_clkdev(clk, "vco1div4_clk", NULL); 472 473 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 474 2); 475 clk_register_clkdev(clk, "vco2div2_clk", NULL); 476 477 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 478 2); 479 clk_register_clkdev(clk, "vco3div2_clk", NULL); 480 481 /* peripherals */ 482 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 483 128); 484 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, 485 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, 486 &_lock); 487 clk_register_clkdev(clk, NULL, "spear_thermal"); 488 489 /* clock derived from pll4 clk */ 490 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 491 1); 492 clk_register_clkdev(clk, "ddr_clk", NULL); 493 494 /* clock derived from pll1 clk */ 495 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 496 CLK_SET_RATE_PARENT, 1, 2); 497 clk_register_clkdev(clk, "cpu_clk", NULL); 498 499 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 500 2); 501 clk_register_clkdev(clk, NULL, "ec800620.wdt"); 502 503 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 504 2); 505 clk_register_clkdev(clk, NULL, "smp_twd"); 506 507 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, 508 6); 509 clk_register_clkdev(clk, "ahb_clk", NULL); 510 511 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, 512 12); 513 clk_register_clkdev(clk, "apb_clk", NULL); 514 515 /* gpt clocks */ 516 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 517 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 518 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT, 519 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 520 clk_register_clkdev(clk, "gpt0_mclk", NULL); 521 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 522 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, 523 &_lock); 524 clk_register_clkdev(clk, NULL, "gpt0"); 525 526 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 527 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 528 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT, 529 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 530 clk_register_clkdev(clk, "gpt1_mclk", NULL); 531 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 532 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, 533 &_lock); 534 clk_register_clkdev(clk, NULL, "gpt1"); 535 536 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 537 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 538 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT, 539 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 540 clk_register_clkdev(clk, "gpt2_mclk", NULL); 541 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 542 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, 543 &_lock); 544 clk_register_clkdev(clk, NULL, "gpt2"); 545 546 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 547 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 548 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT, 549 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 550 clk_register_clkdev(clk, "gpt3_mclk", NULL); 551 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 552 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, 553 &_lock); 554 clk_register_clkdev(clk, NULL, "gpt3"); 555 556 /* others */ 557 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", 558 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl, 559 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 560 clk_register_clkdev(clk, "uart_syn_clk", NULL); 561 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 562 563 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 564 ARRAY_SIZE(uart0_parents), 565 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 566 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, 567 SPEAR1310_UART_CLK_MASK, 0, &_lock); 568 clk_register_clkdev(clk, "uart0_mclk", NULL); 569 570 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 571 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 572 SPEAR1310_UART_CLK_ENB, 0, &_lock); 573 clk_register_clkdev(clk, NULL, "e0000000.serial"); 574 575 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", 576 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, 577 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 578 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 579 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 580 581 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 582 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 583 SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); 584 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 585 586 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 587 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl, 588 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 589 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 590 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 591 592 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 593 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 594 SPEAR1310_CFXD_CLK_ENB, 0, &_lock); 595 clk_register_clkdev(clk, NULL, "b2800000.cf"); 596 clk_register_clkdev(clk, NULL, "arasan_xd"); 597 598 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 599 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl, 600 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 601 clk_register_clkdev(clk, "c3_syn_clk", NULL); 602 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 603 604 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 605 ARRAY_SIZE(c3_parents), 606 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 607 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, 608 SPEAR1310_C3_CLK_MASK, 0, &_lock); 609 clk_register_clkdev(clk, "c3_mclk", NULL); 610 611 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, 612 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, 613 &_lock); 614 clk_register_clkdev(clk, NULL, "c3"); 615 616 /* gmac */ 617 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 618 ARRAY_SIZE(gmac_phy_input_parents), 619 CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG, 620 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, 621 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 622 clk_register_clkdev(clk, "phy_input_mclk", NULL); 623 624 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 625 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl, 626 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 627 clk_register_clkdev(clk, "phy_syn_clk", NULL); 628 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 629 630 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 631 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT, 632 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 633 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 634 clk_register_clkdev(clk, "stmmacphy.0", NULL); 635 636 /* clcd */ 637 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 638 ARRAY_SIZE(clcd_synth_parents), 639 CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT, 640 SPEAR1310_CLCD_SYNT_CLK_SHIFT, 641 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); 642 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 643 644 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, 645 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, 646 ARRAY_SIZE(clcd_rtbl), &_lock); 647 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 648 649 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 650 ARRAY_SIZE(clcd_pixel_parents), 651 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 652 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 653 SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 654 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 655 656 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 657 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, 658 &_lock); 659 clk_register_clkdev(clk, NULL, "e1000000.clcd"); 660 661 /* i2s */ 662 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 663 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT, 664 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT, 665 SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock); 666 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 667 668 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 669 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 670 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 671 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 672 673 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 674 ARRAY_SIZE(i2s_ref_parents), 675 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 676 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, 677 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); 678 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 679 680 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 681 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 682 0, &_lock); 683 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 684 685 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", 686 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG, 687 &i2s_sclk_masks, i2s_sclk_rtbl, 688 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 689 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 690 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); 691 692 /* clock derived from ahb clk */ 693 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 694 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0, 695 &_lock); 696 clk_register_clkdev(clk, NULL, "e0280000.i2c"); 697 698 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, 699 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0, 700 &_lock); 701 clk_register_clkdev(clk, NULL, "ea800000.dma"); 702 clk_register_clkdev(clk, NULL, "eb000000.dma"); 703 704 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, 705 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0, 706 &_lock); 707 clk_register_clkdev(clk, NULL, "b2000000.jpeg"); 708 709 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, 710 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0, 711 &_lock); 712 clk_register_clkdev(clk, NULL, "e2000000.eth"); 713 714 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, 715 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0, 716 &_lock); 717 clk_register_clkdev(clk, NULL, "b0000000.flash"); 718 719 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, 720 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0, 721 &_lock); 722 clk_register_clkdev(clk, NULL, "ea000000.flash"); 723 724 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 725 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, 726 &_lock); 727 clk_register_clkdev(clk, NULL, "e4000000.ohci"); 728 clk_register_clkdev(clk, NULL, "e4800000.ehci"); 729 730 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 731 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, 732 &_lock); 733 clk_register_clkdev(clk, NULL, "e5000000.ohci"); 734 clk_register_clkdev(clk, NULL, "e5800000.ehci"); 735 736 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 737 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, 738 &_lock); 739 clk_register_clkdev(clk, NULL, "e3800000.otg"); 740 741 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, 742 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 743 0, &_lock); 744 clk_register_clkdev(clk, NULL, "b1000000.pcie"); 745 clk_register_clkdev(clk, NULL, "b1000000.ahci"); 746 747 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, 748 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 749 0, &_lock); 750 clk_register_clkdev(clk, NULL, "b1800000.pcie"); 751 clk_register_clkdev(clk, NULL, "b1800000.ahci"); 752 753 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, 754 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 755 0, &_lock); 756 clk_register_clkdev(clk, NULL, "b4000000.pcie"); 757 clk_register_clkdev(clk, NULL, "b4000000.ahci"); 758 759 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 760 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, 761 &_lock); 762 clk_register_clkdev(clk, "sysram0_clk", NULL); 763 764 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, 765 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0, 766 &_lock); 767 clk_register_clkdev(clk, "sysram1_clk", NULL); 768 769 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 770 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, 771 ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 772 clk_register_clkdev(clk, "adc_syn_clk", NULL); 773 clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 774 775 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 776 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 777 SPEAR1310_ADC_CLK_ENB, 0, &_lock); 778 clk_register_clkdev(clk, NULL, "e0080000.adc"); 779 780 /* clock derived from apb clk */ 781 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, 782 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0, 783 &_lock); 784 clk_register_clkdev(clk, NULL, "e0100000.spi"); 785 786 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, 787 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0, 788 &_lock); 789 clk_register_clkdev(clk, NULL, "e0600000.gpio"); 790 791 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, 792 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0, 793 &_lock); 794 clk_register_clkdev(clk, NULL, "e0680000.gpio"); 795 796 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, 797 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0, 798 &_lock); 799 clk_register_clkdev(clk, NULL, "e0180000.i2s"); 800 801 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, 802 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0, 803 &_lock); 804 clk_register_clkdev(clk, NULL, "e0200000.i2s"); 805 806 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, 807 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0, 808 &_lock); 809 clk_register_clkdev(clk, NULL, "e0300000.kbd"); 810 811 /* RAS clks */ 812 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 813 ARRAY_SIZE(gen_synth0_1_parents), 814 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, 815 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, 816 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 817 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); 818 819 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 820 ARRAY_SIZE(gen_synth2_3_parents), 821 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, 822 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, 823 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 824 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); 825 826 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, 827 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 828 &_lock); 829 clk_register_clkdev(clk, "gen_syn0_clk", NULL); 830 831 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, 832 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 833 &_lock); 834 clk_register_clkdev(clk, "gen_syn1_clk", NULL); 835 836 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, 837 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 838 &_lock); 839 clk_register_clkdev(clk, "gen_syn2_clk", NULL); 840 841 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, 842 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 843 &_lock); 844 clk_register_clkdev(clk, "gen_syn3_clk", NULL); 845 846 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, 847 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, 848 &_lock); 849 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); 850 851 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, 852 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0, 853 &_lock); 854 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); 855 856 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, 857 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0, 858 &_lock); 859 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); 860 861 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, 862 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0, 863 &_lock); 864 clk_register_clkdev(clk, "ras_pll2_clk", NULL); 865 866 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, 867 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0, 868 &_lock); 869 clk_register_clkdev(clk, "ras_pll3_clk", NULL); 870 871 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, 872 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, 873 &_lock); 874 clk_register_clkdev(clk, "ras_tx125_clk", NULL); 875 876 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, 877 30000000); 878 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, 879 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0, 880 &_lock); 881 clk_register_clkdev(clk, "ras_30m_clk", NULL); 882 883 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, 884 48000000); 885 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, 886 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0, 887 &_lock); 888 clk_register_clkdev(clk, "ras_48m_clk", NULL); 889 890 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, 891 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0, 892 &_lock); 893 clk_register_clkdev(clk, "ras_ahb_clk", NULL); 894 895 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, 896 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0, 897 &_lock); 898 clk_register_clkdev(clk, "ras_apb_clk", NULL); 899 900 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT, 901 50000000); 902 903 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT, 904 50000000); 905 906 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, 907 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, 908 &_lock); 909 clk_register_clkdev(clk, NULL, "c_can_platform.0"); 910 911 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, 912 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0, 913 &_lock); 914 clk_register_clkdev(clk, NULL, "c_can_platform.1"); 915 916 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, 917 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0, 918 &_lock); 919 clk_register_clkdev(clk, NULL, "5c400000.eth"); 920 921 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, 922 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0, 923 &_lock); 924 clk_register_clkdev(clk, NULL, "5c500000.eth"); 925 926 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, 927 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0, 928 &_lock); 929 clk_register_clkdev(clk, NULL, "5c600000.eth"); 930 931 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, 932 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0, 933 &_lock); 934 clk_register_clkdev(clk, NULL, "5c700000.eth"); 935 936 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", 937 smii_rgmii_phy_parents, 938 ARRAY_SIZE(smii_rgmii_phy_parents), 939 CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1, 940 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, 941 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 942 clk_register_clkdev(clk, "stmmacphy.1", NULL); 943 clk_register_clkdev(clk, "stmmacphy.2", NULL); 944 clk_register_clkdev(clk, "stmmacphy.4", NULL); 945 946 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, 947 ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT, 948 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 949 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 950 clk_register_clkdev(clk, "stmmacphy.3", NULL); 951 952 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, 953 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 954 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT, 955 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 956 clk_register_clkdev(clk, "uart1_mclk", NULL); 957 958 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 959 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, 960 &_lock); 961 clk_register_clkdev(clk, NULL, "5c800000.serial"); 962 963 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, 964 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 965 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT, 966 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 967 clk_register_clkdev(clk, "uart2_mclk", NULL); 968 969 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, 970 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, 971 &_lock); 972 clk_register_clkdev(clk, NULL, "5c900000.serial"); 973 974 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, 975 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 976 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT, 977 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 978 clk_register_clkdev(clk, "uart3_mclk", NULL); 979 980 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, 981 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, 982 &_lock); 983 clk_register_clkdev(clk, NULL, "5ca00000.serial"); 984 985 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, 986 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 987 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT, 988 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 989 clk_register_clkdev(clk, "uart4_mclk", NULL); 990 991 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, 992 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, 993 &_lock); 994 clk_register_clkdev(clk, NULL, "5cb00000.serial"); 995 996 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, 997 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 998 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT, 999 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 1000 clk_register_clkdev(clk, "uart5_mclk", NULL); 1001 1002 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, 1003 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, 1004 &_lock); 1005 clk_register_clkdev(clk, NULL, "5cc00000.serial"); 1006 1007 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, 1008 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1009 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT, 1010 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1011 clk_register_clkdev(clk, "i2c1_mclk", NULL); 1012 1013 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, 1014 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, 1015 &_lock); 1016 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); 1017 1018 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, 1019 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1020 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT, 1021 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1022 clk_register_clkdev(clk, "i2c2_mclk", NULL); 1023 1024 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, 1025 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, 1026 &_lock); 1027 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); 1028 1029 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, 1030 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1031 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT, 1032 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1033 clk_register_clkdev(clk, "i2c3_mclk", NULL); 1034 1035 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, 1036 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, 1037 &_lock); 1038 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); 1039 1040 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, 1041 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1042 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT, 1043 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1044 clk_register_clkdev(clk, "i2c4_mclk", NULL); 1045 1046 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, 1047 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, 1048 &_lock); 1049 clk_register_clkdev(clk, NULL, "5d000000.i2c"); 1050 1051 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, 1052 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1053 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT, 1054 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1055 clk_register_clkdev(clk, "i2c5_mclk", NULL); 1056 1057 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, 1058 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, 1059 &_lock); 1060 clk_register_clkdev(clk, NULL, "5d100000.i2c"); 1061 1062 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, 1063 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1064 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT, 1065 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1066 clk_register_clkdev(clk, "i2c6_mclk", NULL); 1067 1068 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, 1069 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, 1070 &_lock); 1071 clk_register_clkdev(clk, NULL, "5d200000.i2c"); 1072 1073 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, 1074 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1075 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT, 1076 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1077 clk_register_clkdev(clk, "i2c7_mclk", NULL); 1078 1079 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, 1080 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, 1081 &_lock); 1082 clk_register_clkdev(clk, NULL, "5d300000.i2c"); 1083 1084 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, 1085 ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT, 1086 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT, 1087 SPEAR1310_SSP1_CLK_MASK, 0, &_lock); 1088 clk_register_clkdev(clk, "ssp1_mclk", NULL); 1089 1090 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, 1091 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, 1092 &_lock); 1093 clk_register_clkdev(clk, NULL, "5d400000.spi"); 1094 1095 clk = clk_register_mux(NULL, "pci_mclk", pci_parents, 1096 ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT, 1097 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT, 1098 SPEAR1310_PCI_CLK_MASK, 0, &_lock); 1099 clk_register_clkdev(clk, "pci_mclk", NULL); 1100 1101 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, 1102 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, 1103 &_lock); 1104 clk_register_clkdev(clk, NULL, "pci"); 1105 1106 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, 1107 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, 1108 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT, 1109 SPEAR1310_TDM_CLK_MASK, 0, &_lock); 1110 clk_register_clkdev(clk, "tdm1_mclk", NULL); 1111 1112 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, 1113 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, 1114 &_lock); 1115 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); 1116 1117 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, 1118 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, 1119 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT, 1120 SPEAR1310_TDM_CLK_MASK, 0, &_lock); 1121 clk_register_clkdev(clk, "tdm2_mclk", NULL); 1122 1123 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, 1124 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, 1125 &_lock); 1126 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); 1127} 1128