1/*
2 * linux/drivers/video/omap2/dss/sdi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "SDI"
21
22#include <linux/kernel.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/regulator/consumer.h>
26#include <linux/export.h>
27#include <linux/platform_device.h>
28#include <linux/string.h>
29#include <linux/of.h>
30#include <linux/component.h>
31
32#include <video/omapdss.h>
33#include "dss.h"
34
35static struct {
36	struct platform_device *pdev;
37
38	bool update_enabled;
39	struct regulator *vdds_sdi_reg;
40
41	struct dss_lcd_mgr_config mgr_config;
42	struct omap_video_timings timings;
43	int datapairs;
44
45	struct omap_dss_device output;
46
47	bool port_initialized;
48} sdi;
49
50struct sdi_clk_calc_ctx {
51	unsigned long pck_min, pck_max;
52
53	unsigned long fck;
54	struct dispc_clock_info dispc_cinfo;
55};
56
57static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
58		unsigned long pck, void *data)
59{
60	struct sdi_clk_calc_ctx *ctx = data;
61
62	ctx->dispc_cinfo.lck_div = lckd;
63	ctx->dispc_cinfo.pck_div = pckd;
64	ctx->dispc_cinfo.lck = lck;
65	ctx->dispc_cinfo.pck = pck;
66
67	return true;
68}
69
70static bool dpi_calc_dss_cb(unsigned long fck, void *data)
71{
72	struct sdi_clk_calc_ctx *ctx = data;
73
74	ctx->fck = fck;
75
76	return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
77			dpi_calc_dispc_cb, ctx);
78}
79
80static int sdi_calc_clock_div(unsigned long pclk,
81		unsigned long *fck,
82		struct dispc_clock_info *dispc_cinfo)
83{
84	int i;
85	struct sdi_clk_calc_ctx ctx;
86
87	/*
88	 * DSS fclk gives us very few possibilities, so finding a good pixel
89	 * clock may not be possible. We try multiple times to find the clock,
90	 * each time widening the pixel clock range we look for, up to
91	 * +/- 1MHz.
92	 */
93
94	for (i = 0; i < 10; ++i) {
95		bool ok;
96
97		memset(&ctx, 0, sizeof(ctx));
98		if (pclk > 1000 * i * i * i)
99			ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
100		else
101			ctx.pck_min = 0;
102		ctx.pck_max = pclk + 1000 * i * i * i;
103
104		ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx);
105		if (ok) {
106			*fck = ctx.fck;
107			*dispc_cinfo = ctx.dispc_cinfo;
108			return 0;
109		}
110	}
111
112	return -EINVAL;
113}
114
115static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
116{
117	struct omap_overlay_manager *mgr = sdi.output.manager;
118
119	sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
120
121	sdi.mgr_config.stallmode = false;
122	sdi.mgr_config.fifohandcheck = false;
123
124	sdi.mgr_config.video_port_width = 24;
125	sdi.mgr_config.lcden_sig_polarity = 1;
126
127	dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
128}
129
130static int sdi_display_enable(struct omap_dss_device *dssdev)
131{
132	struct omap_dss_device *out = &sdi.output;
133	struct omap_video_timings *t = &sdi.timings;
134	unsigned long fck;
135	struct dispc_clock_info dispc_cinfo;
136	unsigned long pck;
137	int r;
138
139	if (out == NULL || out->manager == NULL) {
140		DSSERR("failed to enable display: no output/manager\n");
141		return -ENODEV;
142	}
143
144	r = regulator_enable(sdi.vdds_sdi_reg);
145	if (r)
146		goto err_reg_enable;
147
148	r = dispc_runtime_get();
149	if (r)
150		goto err_get_dispc;
151
152	/* 15.5.9.1.2 */
153	t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
154	t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
155
156	r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo);
157	if (r)
158		goto err_calc_clock_div;
159
160	sdi.mgr_config.clock_info = dispc_cinfo;
161
162	pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
163
164	if (pck != t->pixelclock) {
165		DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
166			t->pixelclock, pck);
167
168		t->pixelclock = pck;
169	}
170
171
172	dss_mgr_set_timings(out->manager, t);
173
174	r = dss_set_fck_rate(fck);
175	if (r)
176		goto err_set_dss_clock_div;
177
178	sdi_config_lcd_manager(dssdev);
179
180	/*
181	 * LCLK and PCLK divisors are located in shadow registers, and we
182	 * normally write them to DISPC registers when enabling the output.
183	 * However, SDI uses pck-free as source clock for its PLL, and pck-free
184	 * is affected by the divisors. And as we need the PLL before enabling
185	 * the output, we need to write the divisors early.
186	 *
187	 * It seems just writing to the DISPC register is enough, and we don't
188	 * need to care about the shadow register mechanism for pck-free. The
189	 * exact reason for this is unknown.
190	 */
191	dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
192
193	dss_sdi_init(sdi.datapairs);
194	r = dss_sdi_enable();
195	if (r)
196		goto err_sdi_enable;
197	mdelay(2);
198
199	r = dss_mgr_enable(out->manager);
200	if (r)
201		goto err_mgr_enable;
202
203	return 0;
204
205err_mgr_enable:
206	dss_sdi_disable();
207err_sdi_enable:
208err_set_dss_clock_div:
209err_calc_clock_div:
210	dispc_runtime_put();
211err_get_dispc:
212	regulator_disable(sdi.vdds_sdi_reg);
213err_reg_enable:
214	return r;
215}
216
217static void sdi_display_disable(struct omap_dss_device *dssdev)
218{
219	struct omap_overlay_manager *mgr = sdi.output.manager;
220
221	dss_mgr_disable(mgr);
222
223	dss_sdi_disable();
224
225	dispc_runtime_put();
226
227	regulator_disable(sdi.vdds_sdi_reg);
228}
229
230static void sdi_set_timings(struct omap_dss_device *dssdev,
231		struct omap_video_timings *timings)
232{
233	sdi.timings = *timings;
234}
235
236static void sdi_get_timings(struct omap_dss_device *dssdev,
237		struct omap_video_timings *timings)
238{
239	*timings = sdi.timings;
240}
241
242static int sdi_check_timings(struct omap_dss_device *dssdev,
243			struct omap_video_timings *timings)
244{
245	struct omap_overlay_manager *mgr = sdi.output.manager;
246
247	if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
248		return -EINVAL;
249
250	if (timings->pixelclock == 0)
251		return -EINVAL;
252
253	return 0;
254}
255
256static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
257{
258	sdi.datapairs = datapairs;
259}
260
261static int sdi_init_regulator(void)
262{
263	struct regulator *vdds_sdi;
264
265	if (sdi.vdds_sdi_reg)
266		return 0;
267
268	vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
269	if (IS_ERR(vdds_sdi)) {
270		if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
271			DSSERR("can't get VDDS_SDI regulator\n");
272		return PTR_ERR(vdds_sdi);
273	}
274
275	sdi.vdds_sdi_reg = vdds_sdi;
276
277	return 0;
278}
279
280static int sdi_connect(struct omap_dss_device *dssdev,
281		struct omap_dss_device *dst)
282{
283	struct omap_overlay_manager *mgr;
284	int r;
285
286	r = sdi_init_regulator();
287	if (r)
288		return r;
289
290	mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
291	if (!mgr)
292		return -ENODEV;
293
294	r = dss_mgr_connect(mgr, dssdev);
295	if (r)
296		return r;
297
298	r = omapdss_output_set_device(dssdev, dst);
299	if (r) {
300		DSSERR("failed to connect output to new device: %s\n",
301				dst->name);
302		dss_mgr_disconnect(mgr, dssdev);
303		return r;
304	}
305
306	return 0;
307}
308
309static void sdi_disconnect(struct omap_dss_device *dssdev,
310		struct omap_dss_device *dst)
311{
312	WARN_ON(dst != dssdev->dst);
313
314	if (dst != dssdev->dst)
315		return;
316
317	omapdss_output_unset_device(dssdev);
318
319	if (dssdev->manager)
320		dss_mgr_disconnect(dssdev->manager, dssdev);
321}
322
323static const struct omapdss_sdi_ops sdi_ops = {
324	.connect = sdi_connect,
325	.disconnect = sdi_disconnect,
326
327	.enable = sdi_display_enable,
328	.disable = sdi_display_disable,
329
330	.check_timings = sdi_check_timings,
331	.set_timings = sdi_set_timings,
332	.get_timings = sdi_get_timings,
333
334	.set_datapairs = sdi_set_datapairs,
335};
336
337static void sdi_init_output(struct platform_device *pdev)
338{
339	struct omap_dss_device *out = &sdi.output;
340
341	out->dev = &pdev->dev;
342	out->id = OMAP_DSS_OUTPUT_SDI;
343	out->output_type = OMAP_DISPLAY_TYPE_SDI;
344	out->name = "sdi.0";
345	out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
346	/* We have SDI only on OMAP3, where it's on port 1 */
347	out->port_num = 1;
348	out->ops.sdi = &sdi_ops;
349	out->owner = THIS_MODULE;
350
351	omapdss_register_output(out);
352}
353
354static void sdi_uninit_output(struct platform_device *pdev)
355{
356	struct omap_dss_device *out = &sdi.output;
357
358	omapdss_unregister_output(out);
359}
360
361static int sdi_bind(struct device *dev, struct device *master, void *data)
362{
363	struct platform_device *pdev = to_platform_device(dev);
364
365	sdi.pdev = pdev;
366
367	sdi_init_output(pdev);
368
369	return 0;
370}
371
372static void sdi_unbind(struct device *dev, struct device *master, void *data)
373{
374	struct platform_device *pdev = to_platform_device(dev);
375
376	sdi_uninit_output(pdev);
377}
378
379static const struct component_ops sdi_component_ops = {
380	.bind	= sdi_bind,
381	.unbind	= sdi_unbind,
382};
383
384static int sdi_probe(struct platform_device *pdev)
385{
386	return component_add(&pdev->dev, &sdi_component_ops);
387}
388
389static int sdi_remove(struct platform_device *pdev)
390{
391	component_del(&pdev->dev, &sdi_component_ops);
392	return 0;
393}
394
395static struct platform_driver omap_sdi_driver = {
396	.probe		= sdi_probe,
397	.remove         = sdi_remove,
398	.driver         = {
399		.name   = "omapdss_sdi",
400		.suppress_bind_attrs = true,
401	},
402};
403
404int __init sdi_init_platform_driver(void)
405{
406	return platform_driver_register(&omap_sdi_driver);
407}
408
409void sdi_uninit_platform_driver(void)
410{
411	platform_driver_unregister(&omap_sdi_driver);
412}
413
414int sdi_init_port(struct platform_device *pdev, struct device_node *port)
415{
416	struct device_node *ep;
417	u32 datapairs;
418	int r;
419
420	ep = omapdss_of_get_next_endpoint(port, NULL);
421	if (!ep)
422		return 0;
423
424	r = of_property_read_u32(ep, "datapairs", &datapairs);
425	if (r) {
426		DSSERR("failed to parse datapairs\n");
427		goto err_datapairs;
428	}
429
430	sdi.datapairs = datapairs;
431
432	of_node_put(ep);
433
434	sdi.pdev = pdev;
435
436	sdi_init_output(pdev);
437
438	sdi.port_initialized = true;
439
440	return 0;
441
442err_datapairs:
443	of_node_put(ep);
444
445	return r;
446}
447
448void sdi_uninit_port(struct device_node *port)
449{
450	if (!sdi.port_initialized)
451		return;
452
453	sdi_uninit_output(sdi.pdev);
454}
455