1/*
2 * Allwinner A20 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun7i_a20_pins[] = {
22	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23		  SUNXI_FUNCTION(0x0, "gpio_in"),
24		  SUNXI_FUNCTION(0x1, "gpio_out"),
25		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD3 */
26		  SUNXI_FUNCTION(0x3, "spi1"),		/* CS0 */
27		  SUNXI_FUNCTION(0x4, "uart2"),		/* RTS */
28		  SUNXI_FUNCTION(0x5, "gmac")),		/* GRXD3 */
29	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
30		  SUNXI_FUNCTION(0x0, "gpio_in"),
31		  SUNXI_FUNCTION(0x1, "gpio_out"),
32		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD2 */
33		  SUNXI_FUNCTION(0x3, "spi1"),		/* CLK */
34		  SUNXI_FUNCTION(0x4, "uart2"),		/* CTS */
35		  SUNXI_FUNCTION(0x5, "gmac")),		/* GRXD2 */
36	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
37		  SUNXI_FUNCTION(0x0, "gpio_in"),
38		  SUNXI_FUNCTION(0x1, "gpio_out"),
39		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD1 */
40		  SUNXI_FUNCTION(0x3, "spi1"),		/* MOSI */
41		  SUNXI_FUNCTION(0x4, "uart2"),		/* TX */
42		  SUNXI_FUNCTION(0x5, "gmac")),		/* GRXD1 */
43	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
44		  SUNXI_FUNCTION(0x0, "gpio_in"),
45		  SUNXI_FUNCTION(0x1, "gpio_out"),
46		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD0 */
47		  SUNXI_FUNCTION(0x3, "spi1"),		/* MISO */
48		  SUNXI_FUNCTION(0x4, "uart2"),		/* RX */
49		  SUNXI_FUNCTION(0x5, "gmac")),		/* GRXD0 */
50	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51		  SUNXI_FUNCTION(0x0, "gpio_in"),
52		  SUNXI_FUNCTION(0x1, "gpio_out"),
53		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD3 */
54		  SUNXI_FUNCTION(0x3, "spi1"),		/* CS1 */
55		  SUNXI_FUNCTION(0x5, "gmac")),		/* GTXD3 */
56	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
57		  SUNXI_FUNCTION(0x0, "gpio_in"),
58		  SUNXI_FUNCTION(0x1, "gpio_out"),
59		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD2 */
60		  SUNXI_FUNCTION(0x3, "spi3"),		/* CS0 */
61		  SUNXI_FUNCTION(0x5, "gmac")),		/* GTXD2 */
62	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
63		  SUNXI_FUNCTION(0x0, "gpio_in"),
64		  SUNXI_FUNCTION(0x1, "gpio_out"),
65		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD1 */
66		  SUNXI_FUNCTION(0x3, "spi3"),		/* CLK */
67		  SUNXI_FUNCTION(0x5, "gmac")),		/* GTXD1 */
68	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
69		  SUNXI_FUNCTION(0x0, "gpio_in"),
70		  SUNXI_FUNCTION(0x1, "gpio_out"),
71		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD0 */
72		  SUNXI_FUNCTION(0x3, "spi3"),		/* MOSI */
73		  SUNXI_FUNCTION(0x5, "gmac")),		/* GTXD0 */
74	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
75		  SUNXI_FUNCTION(0x0, "gpio_in"),
76		  SUNXI_FUNCTION(0x1, "gpio_out"),
77		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXCK */
78		  SUNXI_FUNCTION(0x3, "spi3"),		/* MISO */
79		  SUNXI_FUNCTION(0x5, "gmac")),		/* GRXCK */
80	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
81		  SUNXI_FUNCTION(0x0, "gpio_in"),
82		  SUNXI_FUNCTION(0x1, "gpio_out"),
83		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXERR */
84		  SUNXI_FUNCTION(0x3, "spi3"),		/* CS1 */
85		  SUNXI_FUNCTION(0x5, "gmac"),		/* GNULL / ERXERR */
86		  SUNXI_FUNCTION(0x6, "i2s1")),		/* MCLK */
87	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
88		  SUNXI_FUNCTION(0x0, "gpio_in"),
89		  SUNXI_FUNCTION(0x1, "gpio_out"),
90		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXDV */
91		  SUNXI_FUNCTION(0x4, "uart1"),		/* TX */
92		  SUNXI_FUNCTION(0x5, "gmac")),		/* GRXCTL / ERXDV */
93	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
94		  SUNXI_FUNCTION(0x0, "gpio_in"),
95		  SUNXI_FUNCTION(0x1, "gpio_out"),
96		  SUNXI_FUNCTION(0x2, "emac"),		/* EMDC */
97		  SUNXI_FUNCTION(0x4, "uart1"),		/* RX */
98		  SUNXI_FUNCTION(0x5, "gmac")),		/* EMDC */
99	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
100		  SUNXI_FUNCTION(0x0, "gpio_in"),
101		  SUNXI_FUNCTION(0x1, "gpio_out"),
102		  SUNXI_FUNCTION(0x2, "emac"),		/* EMDIO */
103		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
104		  SUNXI_FUNCTION(0x4, "uart1"),		/* RTS */
105		  SUNXI_FUNCTION(0x5, "gmac")),		/* EMDIO */
106	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
107		  SUNXI_FUNCTION(0x0, "gpio_in"),
108		  SUNXI_FUNCTION(0x1, "gpio_out"),
109		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXEN */
110		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
111		  SUNXI_FUNCTION(0x4, "uart1"),		/* CTS */
112		  SUNXI_FUNCTION(0x5, "gmac")),		/* GTXCTL / ETXEN */
113	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
114		  SUNXI_FUNCTION(0x0, "gpio_in"),
115		  SUNXI_FUNCTION(0x1, "gpio_out"),
116		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXCK */
117		  SUNXI_FUNCTION(0x3, "uart7"),		/* TX */
118		  SUNXI_FUNCTION(0x4, "uart1"),		/* DTR */
119		  SUNXI_FUNCTION(0x5, "gmac"),		/* GNULL / ETXCK */
120		  SUNXI_FUNCTION(0x6, "i2s1")),		/* BCLK */
121	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
122		  SUNXI_FUNCTION(0x0, "gpio_in"),
123		  SUNXI_FUNCTION(0x1, "gpio_out"),
124		  SUNXI_FUNCTION(0x2, "emac"),		/* ECRS */
125		  SUNXI_FUNCTION(0x3, "uart7"),		/* RX */
126		  SUNXI_FUNCTION(0x4, "uart1"),		/* DSR */
127		  SUNXI_FUNCTION(0x5, "gmac"),		/* GTXCK / ECRS */
128		  SUNXI_FUNCTION(0x6, "i2s1")),		/* LRCK */
129	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
130		  SUNXI_FUNCTION(0x0, "gpio_in"),
131		  SUNXI_FUNCTION(0x1, "gpio_out"),
132		  SUNXI_FUNCTION(0x2, "emac"),		/* ECOL */
133		  SUNXI_FUNCTION(0x3, "can"),		/* TX */
134		  SUNXI_FUNCTION(0x4, "uart1"),		/* DCD */
135		  SUNXI_FUNCTION(0x5, "gmac"),		/* GCLKIN / ECOL */
136		  SUNXI_FUNCTION(0x6, "i2s1")),		/* DO */
137	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
138		  SUNXI_FUNCTION(0x0, "gpio_in"),
139		  SUNXI_FUNCTION(0x1, "gpio_out"),
140		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXERR */
141		  SUNXI_FUNCTION(0x3, "can"),		/* RX */
142		  SUNXI_FUNCTION(0x4, "uart1"),		/* RING */
143		  SUNXI_FUNCTION(0x5, "gmac"),		/* GNULL / ETXERR */
144		  SUNXI_FUNCTION(0x6, "i2s1")),		/* LRCK */
145	/* Hole */
146	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
147		  SUNXI_FUNCTION(0x0, "gpio_in"),
148		  SUNXI_FUNCTION(0x1, "gpio_out"),
149		  SUNXI_FUNCTION(0x2, "i2c0")),		/* SCK */
150	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
151		  SUNXI_FUNCTION(0x0, "gpio_in"),
152		  SUNXI_FUNCTION(0x1, "gpio_out"),
153		  SUNXI_FUNCTION(0x2, "i2c0")),		/* SDA */
154	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
155		  SUNXI_FUNCTION(0x0, "gpio_in"),
156		  SUNXI_FUNCTION(0x1, "gpio_out"),
157		  SUNXI_FUNCTION(0x2, "pwm")),		/* PWM0 */
158	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
159		  SUNXI_FUNCTION(0x0, "gpio_in"),
160		  SUNXI_FUNCTION(0x1, "gpio_out"),
161		  SUNXI_FUNCTION(0x2, "ir0"),		/* TX */
162		  SUNXI_FUNCTION(0x4, "spdif")),	/* MCLK */
163	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
164		  SUNXI_FUNCTION(0x0, "gpio_in"),
165		  SUNXI_FUNCTION(0x1, "gpio_out"),
166		  SUNXI_FUNCTION(0x2, "ir0")),		/* RX */
167	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
168		  SUNXI_FUNCTION(0x0, "gpio_in"),
169		  SUNXI_FUNCTION(0x1, "gpio_out"),
170		  SUNXI_FUNCTION(0x2, "i2s0"),		/* MCLK */
171		  SUNXI_FUNCTION(0x3, "ac97")),		/* MCLK */
172	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
173		  SUNXI_FUNCTION(0x0, "gpio_in"),
174		  SUNXI_FUNCTION(0x1, "gpio_out"),
175		  SUNXI_FUNCTION(0x2, "i2s0"),		/* BCLK */
176		  SUNXI_FUNCTION(0x3, "ac97")),		/* BCLK */
177	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
178		  SUNXI_FUNCTION(0x0, "gpio_in"),
179		  SUNXI_FUNCTION(0x1, "gpio_out"),
180		  SUNXI_FUNCTION(0x2, "i2s0"),		/* LRCK */
181		  SUNXI_FUNCTION(0x3, "ac97")),		/* SYNC */
182	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
183		  SUNXI_FUNCTION(0x0, "gpio_in"),
184		  SUNXI_FUNCTION(0x1, "gpio_out"),
185		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO0 */
186		  SUNXI_FUNCTION(0x3, "ac97")),		/* DO */
187	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
188		  SUNXI_FUNCTION(0x0, "gpio_in"),
189		  SUNXI_FUNCTION(0x1, "gpio_out"),
190		  SUNXI_FUNCTION(0x2, "i2s0")),		/* DO1 */
191	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
192		  SUNXI_FUNCTION(0x0, "gpio_in"),
193		  SUNXI_FUNCTION(0x1, "gpio_out"),
194		  SUNXI_FUNCTION(0x2, "i2s0")),		/* DO2 */
195	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
196		  SUNXI_FUNCTION(0x0, "gpio_in"),
197		  SUNXI_FUNCTION(0x1, "gpio_out"),
198		  SUNXI_FUNCTION(0x2, "i2s0")),		/* DO3 */
199	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
200		  SUNXI_FUNCTION(0x0, "gpio_in"),
201		  SUNXI_FUNCTION(0x1, "gpio_out"),
202		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DI */
203		  SUNXI_FUNCTION(0x3, "ac97"),		/* DI */
204		  SUNXI_FUNCTION(0x4, "spdif")),	/* DI */
205	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
206		  SUNXI_FUNCTION(0x0, "gpio_in"),
207		  SUNXI_FUNCTION(0x1, "gpio_out"),
208		  SUNXI_FUNCTION(0x2, "spi2"),		/* CS1 */
209		  SUNXI_FUNCTION(0x4, "spdif")),	/* DO */
210	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
211		  SUNXI_FUNCTION(0x0, "gpio_in"),
212		  SUNXI_FUNCTION(0x1, "gpio_out"),
213		  SUNXI_FUNCTION(0x2, "spi2"),		/* CS0 */
214		  SUNXI_FUNCTION(0x3, "jtag")),		/* MS0 */
215	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
216		  SUNXI_FUNCTION(0x0, "gpio_in"),
217		  SUNXI_FUNCTION(0x1, "gpio_out"),
218		  SUNXI_FUNCTION(0x2, "spi2"),		/* CLK */
219		  SUNXI_FUNCTION(0x3, "jtag")),		/* CK0 */
220	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
221		  SUNXI_FUNCTION(0x0, "gpio_in"),
222		  SUNXI_FUNCTION(0x1, "gpio_out"),
223		  SUNXI_FUNCTION(0x2, "spi2"),		/* MOSI */
224		  SUNXI_FUNCTION(0x3, "jtag")),		/* DO0 */
225	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
226		  SUNXI_FUNCTION(0x0, "gpio_in"),
227		  SUNXI_FUNCTION(0x1, "gpio_out"),
228		  SUNXI_FUNCTION(0x2, "spi2"),		/* MISO */
229		  SUNXI_FUNCTION(0x3, "jtag")),		/* DI0 */
230	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
231		  SUNXI_FUNCTION(0x0, "gpio_in"),
232		  SUNXI_FUNCTION(0x1, "gpio_out"),
233		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SCK */
234	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
235		  SUNXI_FUNCTION(0x0, "gpio_in"),
236		  SUNXI_FUNCTION(0x1, "gpio_out"),
237		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SDA */
238	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
239		  SUNXI_FUNCTION(0x0, "gpio_in"),
240		  SUNXI_FUNCTION(0x1, "gpio_out"),
241		  SUNXI_FUNCTION(0x2, "i2c2")),		/* SCK */
242	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
243		  SUNXI_FUNCTION(0x0, "gpio_in"),
244		  SUNXI_FUNCTION(0x1, "gpio_out"),
245		  SUNXI_FUNCTION(0x2, "i2c2")),		/* SDA */
246	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
247		  SUNXI_FUNCTION(0x0, "gpio_in"),
248		  SUNXI_FUNCTION(0x1, "gpio_out"),
249		  SUNXI_FUNCTION(0x2, "uart0"),		/* TX */
250		  SUNXI_FUNCTION(0x3, "ir1")),		/* TX */
251	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
252		  SUNXI_FUNCTION(0x0, "gpio_in"),
253		  SUNXI_FUNCTION(0x1, "gpio_out"),
254		  SUNXI_FUNCTION(0x2, "uart0"),		/* RX */
255		  SUNXI_FUNCTION(0x3, "ir1")),		/* RX */
256	/* Hole */
257	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
258		  SUNXI_FUNCTION(0x0, "gpio_in"),
259		  SUNXI_FUNCTION(0x1, "gpio_out"),
260		  SUNXI_FUNCTION(0x2, "nand0"),		/* NWE */
261		  SUNXI_FUNCTION(0x3, "spi0")),		/* MOSI */
262	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
263		  SUNXI_FUNCTION(0x0, "gpio_in"),
264		  SUNXI_FUNCTION(0x1, "gpio_out"),
265		  SUNXI_FUNCTION(0x2, "nand0"),		/* NALE */
266		  SUNXI_FUNCTION(0x3, "spi0")),		/* MISO */
267	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
268		  SUNXI_FUNCTION(0x0, "gpio_in"),
269		  SUNXI_FUNCTION(0x1, "gpio_out"),
270		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCLE */
271		  SUNXI_FUNCTION(0x3, "spi0")),		/* SCK */
272	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
273		  SUNXI_FUNCTION(0x0, "gpio_in"),
274		  SUNXI_FUNCTION(0x1, "gpio_out"),
275		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE1 */
276	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
277		  SUNXI_FUNCTION(0x0, "gpio_in"),
278		  SUNXI_FUNCTION(0x1, "gpio_out"),
279		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE0 */
280	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
281		  SUNXI_FUNCTION(0x0, "gpio_in"),
282		  SUNXI_FUNCTION(0x1, "gpio_out"),
283		  SUNXI_FUNCTION(0x2, "nand0")),	/* NRE# */
284	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
285		  SUNXI_FUNCTION(0x0, "gpio_in"),
286		  SUNXI_FUNCTION(0x1, "gpio_out"),
287		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB0 */
288		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CMD */
289	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
290		  SUNXI_FUNCTION(0x0, "gpio_in"),
291		  SUNXI_FUNCTION(0x1, "gpio_out"),
292		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB1 */
293		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CLK */
294	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
295		  SUNXI_FUNCTION(0x0, "gpio_in"),
296		  SUNXI_FUNCTION(0x1, "gpio_out"),
297		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ0 */
298		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D0 */
299	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
300		  SUNXI_FUNCTION(0x0, "gpio_in"),
301		  SUNXI_FUNCTION(0x1, "gpio_out"),
302		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ1 */
303		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D1 */
304	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
305		  SUNXI_FUNCTION(0x0, "gpio_in"),
306		  SUNXI_FUNCTION(0x1, "gpio_out"),
307		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ2 */
308		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D2 */
309	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
310		  SUNXI_FUNCTION(0x0, "gpio_in"),
311		  SUNXI_FUNCTION(0x1, "gpio_out"),
312		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ3 */
313		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D3 */
314	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
315		  SUNXI_FUNCTION(0x0, "gpio_in"),
316		  SUNXI_FUNCTION(0x1, "gpio_out"),
317		  SUNXI_FUNCTION(0x2, "nand0")),	/* NDQ4 */
318	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
319		  SUNXI_FUNCTION(0x0, "gpio_in"),
320		  SUNXI_FUNCTION(0x1, "gpio_out"),
321		  SUNXI_FUNCTION(0x2, "nand0")),	/* NDQ5 */
322	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
323		  SUNXI_FUNCTION(0x0, "gpio_in"),
324		  SUNXI_FUNCTION(0x1, "gpio_out"),
325		  SUNXI_FUNCTION(0x2, "nand0")),	/* NDQ6 */
326	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
327		  SUNXI_FUNCTION(0x0, "gpio_in"),
328		  SUNXI_FUNCTION(0x1, "gpio_out"),
329		  SUNXI_FUNCTION(0x2, "nand0")),	/* NDQ7 */
330	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
331		  SUNXI_FUNCTION(0x0, "gpio_in"),
332		  SUNXI_FUNCTION(0x1, "gpio_out"),
333		  SUNXI_FUNCTION(0x2, "nand0")),	/* NWP */
334	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
335		  SUNXI_FUNCTION(0x0, "gpio_in"),
336		  SUNXI_FUNCTION(0x1, "gpio_out"),
337		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE2 */
338	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
339		  SUNXI_FUNCTION(0x0, "gpio_in"),
340		  SUNXI_FUNCTION(0x1, "gpio_out"),
341		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE3 */
342	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
343		  SUNXI_FUNCTION(0x0, "gpio_in"),
344		  SUNXI_FUNCTION(0x1, "gpio_out"),
345		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE4 */
346		  SUNXI_FUNCTION(0x3, "spi2"),		/* CS0 */
347		  SUNXI_FUNCTION_IRQ(0x6, 12)),		/* EINT12 */
348	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
349		  SUNXI_FUNCTION(0x0, "gpio_in"),
350		  SUNXI_FUNCTION(0x1, "gpio_out"),
351		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE5 */
352		  SUNXI_FUNCTION(0x3, "spi2"),		/* CLK */
353		  SUNXI_FUNCTION_IRQ(0x6, 13)),		/* EINT13 */
354	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
355		  SUNXI_FUNCTION(0x0, "gpio_in"),
356		  SUNXI_FUNCTION(0x1, "gpio_out"),
357		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE6 */
358		  SUNXI_FUNCTION(0x3, "spi2"),		/* MOSI */
359		  SUNXI_FUNCTION_IRQ(0x6, 14)),		/* EINT14 */
360	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
361		  SUNXI_FUNCTION(0x0, "gpio_in"),
362		  SUNXI_FUNCTION(0x1, "gpio_out"),
363		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE7 */
364		  SUNXI_FUNCTION(0x3, "spi2"),		/* MISO */
365		  SUNXI_FUNCTION_IRQ(0x6, 15)),		/* EINT15 */
366	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
367		  SUNXI_FUNCTION(0x0, "gpio_in"),
368		  SUNXI_FUNCTION(0x1, "gpio_out"),
369		  SUNXI_FUNCTION(0x3, "spi0")),		/* CS0 */
370	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
371		  SUNXI_FUNCTION(0x0, "gpio_in"),
372		  SUNXI_FUNCTION(0x1, "gpio_out"),
373		  SUNXI_FUNCTION(0x2, "nand0")),	/* NDQS */
374	/* Hole */
375	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
376		  SUNXI_FUNCTION(0x0, "gpio_in"),
377		  SUNXI_FUNCTION(0x1, "gpio_out"),
378		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D0 */
379		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP0 */
380	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
381		  SUNXI_FUNCTION(0x0, "gpio_in"),
382		  SUNXI_FUNCTION(0x1, "gpio_out"),
383		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D1 */
384		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN0 */
385	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
386		  SUNXI_FUNCTION(0x0, "gpio_in"),
387		  SUNXI_FUNCTION(0x1, "gpio_out"),
388		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
389		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP1 */
390	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
391		  SUNXI_FUNCTION(0x0, "gpio_in"),
392		  SUNXI_FUNCTION(0x1, "gpio_out"),
393		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
394		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN1 */
395	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
396		  SUNXI_FUNCTION(0x0, "gpio_in"),
397		  SUNXI_FUNCTION(0x1, "gpio_out"),
398		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
399		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP2 */
400	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
401		  SUNXI_FUNCTION(0x0, "gpio_in"),
402		  SUNXI_FUNCTION(0x1, "gpio_out"),
403		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
404		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN2 */
405	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
406		  SUNXI_FUNCTION(0x0, "gpio_in"),
407		  SUNXI_FUNCTION(0x1, "gpio_out"),
408		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
409		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VPC */
410	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
411		  SUNXI_FUNCTION(0x0, "gpio_in"),
412		  SUNXI_FUNCTION(0x1, "gpio_out"),
413		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
414		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VNC */
415	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
416		  SUNXI_FUNCTION(0x0, "gpio_in"),
417		  SUNXI_FUNCTION(0x1, "gpio_out"),
418		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D8 */
419		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP3 */
420	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
421		  SUNXI_FUNCTION(0x0, "gpio_in"),
422		  SUNXI_FUNCTION(0x1, "gpio_out"),
423		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D9 */
424		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VM3 */
425	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
426		  SUNXI_FUNCTION(0x0, "gpio_in"),
427		  SUNXI_FUNCTION(0x1, "gpio_out"),
428		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D10 */
429		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP0 */
430	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
431		  SUNXI_FUNCTION(0x0, "gpio_in"),
432		  SUNXI_FUNCTION(0x1, "gpio_out"),
433		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D11 */
434		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN0 */
435	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
436		  SUNXI_FUNCTION(0x0, "gpio_in"),
437		  SUNXI_FUNCTION(0x1, "gpio_out"),
438		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */
439		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP1 */
440	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
441		  SUNXI_FUNCTION(0x0, "gpio_in"),
442		  SUNXI_FUNCTION(0x1, "gpio_out"),
443		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */
444		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN1 */
445	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
446		  SUNXI_FUNCTION(0x0, "gpio_in"),
447		  SUNXI_FUNCTION(0x1, "gpio_out"),
448		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */
449		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP2 */
450	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
451		  SUNXI_FUNCTION(0x0, "gpio_in"),
452		  SUNXI_FUNCTION(0x1, "gpio_out"),
453		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */
454		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN2 */
455	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
456		  SUNXI_FUNCTION(0x0, "gpio_in"),
457		  SUNXI_FUNCTION(0x1, "gpio_out"),
458		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D16 */
459		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VPC */
460	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
461		  SUNXI_FUNCTION(0x0, "gpio_in"),
462		  SUNXI_FUNCTION(0x1, "gpio_out"),
463		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D17 */
464		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VNC */
465	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
466		  SUNXI_FUNCTION(0x0, "gpio_in"),
467		  SUNXI_FUNCTION(0x1, "gpio_out"),
468		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */
469		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP3 */
470	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
471		  SUNXI_FUNCTION(0x0, "gpio_in"),
472		  SUNXI_FUNCTION(0x1, "gpio_out"),
473		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */
474		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN3 */
475	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
476		  SUNXI_FUNCTION(0x0, "gpio_in"),
477		  SUNXI_FUNCTION(0x1, "gpio_out"),
478		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */
479		  SUNXI_FUNCTION(0x3, "csi1")),		/* MCLK */
480	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
481		  SUNXI_FUNCTION(0x0, "gpio_in"),
482		  SUNXI_FUNCTION(0x1, "gpio_out"),
483		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */
484		  SUNXI_FUNCTION(0x3, "sim")),		/* VPPEN */
485	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
486		  SUNXI_FUNCTION(0x0, "gpio_in"),
487		  SUNXI_FUNCTION(0x1, "gpio_out"),
488		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */
489		  SUNXI_FUNCTION(0x3, "sim")),		/* VPPPP */
490	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
491		  SUNXI_FUNCTION(0x0, "gpio_in"),
492		  SUNXI_FUNCTION(0x1, "gpio_out"),
493		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */
494		  SUNXI_FUNCTION(0x3, "sim")),		/* DET */
495	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
496		  SUNXI_FUNCTION(0x0, "gpio_in"),
497		  SUNXI_FUNCTION(0x1, "gpio_out"),
498		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */
499		  SUNXI_FUNCTION(0x3, "sim")),		/* VCCEN */
500	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
501		  SUNXI_FUNCTION(0x0, "gpio_in"),
502		  SUNXI_FUNCTION(0x1, "gpio_out"),
503		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */
504		  SUNXI_FUNCTION(0x3, "sim")),		/* RST */
505	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
506		  SUNXI_FUNCTION(0x0, "gpio_in"),
507		  SUNXI_FUNCTION(0x1, "gpio_out"),
508		  SUNXI_FUNCTION(0x2, "lcd0"),		/* HSYNC */
509		  SUNXI_FUNCTION(0x3, "sim")),		/* SCK */
510	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
511		  SUNXI_FUNCTION(0x0, "gpio_in"),
512		  SUNXI_FUNCTION(0x1, "gpio_out"),
513		  SUNXI_FUNCTION(0x2, "lcd0"),		/* VSYNC */
514		  SUNXI_FUNCTION(0x3, "sim")),		/* SDA */
515	/* Hole */
516	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
517		  SUNXI_FUNCTION(0x0, "gpio_in"),
518		  SUNXI_FUNCTION(0x1, "gpio_out"),
519		  SUNXI_FUNCTION(0x2, "ts0"),		/* CLK */
520		  SUNXI_FUNCTION(0x3, "csi0")),		/* PCK */
521	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
522		  SUNXI_FUNCTION(0x0, "gpio_in"),
523		  SUNXI_FUNCTION(0x1, "gpio_out"),
524		  SUNXI_FUNCTION(0x2, "ts0"),		/* ERR */
525		  SUNXI_FUNCTION(0x3, "csi0")),		/* CK */
526	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
527		  SUNXI_FUNCTION(0x0, "gpio_in"),
528		  SUNXI_FUNCTION(0x1, "gpio_out"),
529		  SUNXI_FUNCTION(0x2, "ts0"),		/* SYNC */
530		  SUNXI_FUNCTION(0x3, "csi0")),		/* HSYNC */
531	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
532		  SUNXI_FUNCTION(0x0, "gpio_in"),
533		  SUNXI_FUNCTION(0x1, "gpio_out"),
534		  SUNXI_FUNCTION(0x2, "ts0"),		/* DVLD */
535		  SUNXI_FUNCTION(0x3, "csi0")),		/* VSYNC */
536	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
537		  SUNXI_FUNCTION(0x0, "gpio_in"),
538		  SUNXI_FUNCTION(0x1, "gpio_out"),
539		  SUNXI_FUNCTION(0x2, "ts0"),		/* D0 */
540		  SUNXI_FUNCTION(0x3, "csi0")),		/* D0 */
541	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
542		  SUNXI_FUNCTION(0x0, "gpio_in"),
543		  SUNXI_FUNCTION(0x1, "gpio_out"),
544		  SUNXI_FUNCTION(0x2, "ts0"),		/* D1 */
545		  SUNXI_FUNCTION(0x3, "csi0"),		/* D1 */
546		  SUNXI_FUNCTION(0x4, "sim")),		/* VPPEN */
547	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
548		  SUNXI_FUNCTION(0x0, "gpio_in"),
549		  SUNXI_FUNCTION(0x1, "gpio_out"),
550		  SUNXI_FUNCTION(0x2, "ts0"),		/* D2 */
551		  SUNXI_FUNCTION(0x3, "csi0")),		/* D2 */
552	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
553		  SUNXI_FUNCTION(0x0, "gpio_in"),
554		  SUNXI_FUNCTION(0x1, "gpio_out"),
555		  SUNXI_FUNCTION(0x2, "ts0"),		/* D3 */
556		  SUNXI_FUNCTION(0x3, "csi0")),		/* D3 */
557	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
558		  SUNXI_FUNCTION(0x0, "gpio_in"),
559		  SUNXI_FUNCTION(0x1, "gpio_out"),
560		  SUNXI_FUNCTION(0x2, "ts0"),		/* D4 */
561		  SUNXI_FUNCTION(0x3, "csi0")),		/* D4 */
562	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
563		  SUNXI_FUNCTION(0x0, "gpio_in"),
564		  SUNXI_FUNCTION(0x1, "gpio_out"),
565		  SUNXI_FUNCTION(0x2, "ts0"),		/* D5 */
566		  SUNXI_FUNCTION(0x3, "csi0")),		/* D5 */
567	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
568		  SUNXI_FUNCTION(0x0, "gpio_in"),
569		  SUNXI_FUNCTION(0x1, "gpio_out"),
570		  SUNXI_FUNCTION(0x2, "ts0"),		/* D6 */
571		  SUNXI_FUNCTION(0x3, "csi0")),		/* D6 */
572	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
573		  SUNXI_FUNCTION(0x0, "gpio_in"),
574		  SUNXI_FUNCTION(0x1, "gpio_out"),
575		  SUNXI_FUNCTION(0x2, "ts0"),		/* D7 */
576		  SUNXI_FUNCTION(0x3, "csi0")),		/* D7 */
577	/* Hole */
578	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
579		  SUNXI_FUNCTION(0x0, "gpio_in"),
580		  SUNXI_FUNCTION(0x1, "gpio_out"),
581		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
582		  SUNXI_FUNCTION(0x4, "jtag")),		/* MSI */
583	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
584		  SUNXI_FUNCTION(0x0, "gpio_in"),
585		  SUNXI_FUNCTION(0x1, "gpio_out"),
586		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
587		  SUNXI_FUNCTION(0x4, "jtag")),		/* DI1 */
588	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
589		  SUNXI_FUNCTION(0x0, "gpio_in"),
590		  SUNXI_FUNCTION(0x1, "gpio_out"),
591		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
592		  SUNXI_FUNCTION(0x4, "uart0")),	/* TX */
593	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
594		  SUNXI_FUNCTION(0x0, "gpio_in"),
595		  SUNXI_FUNCTION(0x1, "gpio_out"),
596		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
597		  SUNXI_FUNCTION(0x4, "jtag")),		/* DO1 */
598	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
599		  SUNXI_FUNCTION(0x0, "gpio_in"),
600		  SUNXI_FUNCTION(0x1, "gpio_out"),
601		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
602		  SUNXI_FUNCTION(0x4, "uart0")),	/* RX */
603	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
604		  SUNXI_FUNCTION(0x0, "gpio_in"),
605		  SUNXI_FUNCTION(0x1, "gpio_out"),
606		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
607		  SUNXI_FUNCTION(0x4, "jtag")),		/* CK1 */
608	/* Hole */
609	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
610		  SUNXI_FUNCTION(0x0, "gpio_in"),
611		  SUNXI_FUNCTION(0x1, "gpio_out"),
612		  SUNXI_FUNCTION(0x2, "ts1"),		/* CLK */
613		  SUNXI_FUNCTION(0x3, "csi1"),		/* PCK */
614		  SUNXI_FUNCTION(0x4, "mmc1")),		/* CMD */
615	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
616		  SUNXI_FUNCTION(0x0, "gpio_in"),
617		  SUNXI_FUNCTION(0x1, "gpio_out"),
618		  SUNXI_FUNCTION(0x2, "ts1"),		/* ERR */
619		  SUNXI_FUNCTION(0x3, "csi1"),		/* CK */
620		  SUNXI_FUNCTION(0x4, "mmc1")),		/* CLK */
621	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
622		  SUNXI_FUNCTION(0x0, "gpio_in"),
623		  SUNXI_FUNCTION(0x1, "gpio_out"),
624		  SUNXI_FUNCTION(0x2, "ts1"),		/* SYNC */
625		  SUNXI_FUNCTION(0x3, "csi1"),		/* HSYNC */
626		  SUNXI_FUNCTION(0x4, "mmc1")),		/* D0 */
627	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
628		  SUNXI_FUNCTION(0x0, "gpio_in"),
629		  SUNXI_FUNCTION(0x1, "gpio_out"),
630		  SUNXI_FUNCTION(0x2, "ts1"),		/* DVLD */
631		  SUNXI_FUNCTION(0x3, "csi1"),		/* VSYNC */
632		  SUNXI_FUNCTION(0x4, "mmc1")),		/* D1 */
633	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
634		  SUNXI_FUNCTION(0x0, "gpio_in"),
635		  SUNXI_FUNCTION(0x1, "gpio_out"),
636		  SUNXI_FUNCTION(0x2, "ts1"),		/* D0 */
637		  SUNXI_FUNCTION(0x3, "csi1"),		/* D0 */
638		  SUNXI_FUNCTION(0x4, "mmc1"),		/* D2 */
639		  SUNXI_FUNCTION(0x5, "csi0")),		/* D8 */
640	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
641		  SUNXI_FUNCTION(0x0, "gpio_in"),
642		  SUNXI_FUNCTION(0x1, "gpio_out"),
643		  SUNXI_FUNCTION(0x2, "ts1"),		/* D1 */
644		  SUNXI_FUNCTION(0x3, "csi1"),		/* D1 */
645		  SUNXI_FUNCTION(0x4, "mmc1"),		/* D3 */
646		  SUNXI_FUNCTION(0x5, "csi0")),		/* D9 */
647	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
648		  SUNXI_FUNCTION(0x0, "gpio_in"),
649		  SUNXI_FUNCTION(0x1, "gpio_out"),
650		  SUNXI_FUNCTION(0x2, "ts1"),		/* D2 */
651		  SUNXI_FUNCTION(0x3, "csi1"),		/* D2 */
652		  SUNXI_FUNCTION(0x4, "uart3"),		/* TX */
653		  SUNXI_FUNCTION(0x5, "csi0")),		/* D10 */
654	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
655		  SUNXI_FUNCTION(0x0, "gpio_in"),
656		  SUNXI_FUNCTION(0x1, "gpio_out"),
657		  SUNXI_FUNCTION(0x2, "ts1"),		/* D3 */
658		  SUNXI_FUNCTION(0x3, "csi1"),		/* D3 */
659		  SUNXI_FUNCTION(0x4, "uart3"),		/* RX */
660		  SUNXI_FUNCTION(0x5, "csi0")),		/* D11 */
661	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
662		  SUNXI_FUNCTION(0x0, "gpio_in"),
663		  SUNXI_FUNCTION(0x1, "gpio_out"),
664		  SUNXI_FUNCTION(0x2, "ts1"),		/* D4 */
665		  SUNXI_FUNCTION(0x3, "csi1"),		/* D4 */
666		  SUNXI_FUNCTION(0x4, "uart3"),		/* RTS */
667		  SUNXI_FUNCTION(0x5, "csi0")),		/* D12 */
668	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
669		  SUNXI_FUNCTION(0x0, "gpio_in"),
670		  SUNXI_FUNCTION(0x1, "gpio_out"),
671		  SUNXI_FUNCTION(0x2, "ts1"),		/* D5 */
672		  SUNXI_FUNCTION(0x3, "csi1"),		/* D5 */
673		  SUNXI_FUNCTION(0x4, "uart3"),		/* CTS */
674		  SUNXI_FUNCTION(0x5, "csi0")),		/* D13 */
675	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
676		  SUNXI_FUNCTION(0x0, "gpio_in"),
677		  SUNXI_FUNCTION(0x1, "gpio_out"),
678		  SUNXI_FUNCTION(0x2, "ts1"),		/* D6 */
679		  SUNXI_FUNCTION(0x3, "csi1"),		/* D6 */
680		  SUNXI_FUNCTION(0x4, "uart4"),		/* TX */
681		  SUNXI_FUNCTION(0x5, "csi0")),		/* D14 */
682	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
683		  SUNXI_FUNCTION(0x0, "gpio_in"),
684		  SUNXI_FUNCTION(0x1, "gpio_out"),
685		  SUNXI_FUNCTION(0x2, "ts1"),		/* D7 */
686		  SUNXI_FUNCTION(0x3, "csi1"),		/* D7 */
687		  SUNXI_FUNCTION(0x4, "uart4"),		/* RX */
688		  SUNXI_FUNCTION(0x5, "csi0")),		/* D15 */
689	/* Hole */
690	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
691		  SUNXI_FUNCTION(0x0, "gpio_in"),
692		  SUNXI_FUNCTION(0x1, "gpio_out"),
693		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D0 */
694		  SUNXI_FUNCTION(0x4, "uart3"),		/* TX */
695		  SUNXI_FUNCTION_IRQ(0x6, 0),		/* EINT0 */
696		  SUNXI_FUNCTION(0x7, "csi1")),		/* D0 */
697	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
698		  SUNXI_FUNCTION(0x0, "gpio_in"),
699		  SUNXI_FUNCTION(0x1, "gpio_out"),
700		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D1 */
701		  SUNXI_FUNCTION(0x4, "uart3"),		/* RX */
702		  SUNXI_FUNCTION_IRQ(0x6, 1),		/* EINT1 */
703		  SUNXI_FUNCTION(0x7, "csi1")),		/* D1 */
704	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
705		  SUNXI_FUNCTION(0x0, "gpio_in"),
706		  SUNXI_FUNCTION(0x1, "gpio_out"),
707		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D2 */
708		  SUNXI_FUNCTION(0x4, "uart3"),		/* RTS */
709		  SUNXI_FUNCTION_IRQ(0x6, 2),		/* EINT2 */
710		  SUNXI_FUNCTION(0x7, "csi1")),		/* D2 */
711	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
712		  SUNXI_FUNCTION(0x0, "gpio_in"),
713		  SUNXI_FUNCTION(0x1, "gpio_out"),
714		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D3 */
715		  SUNXI_FUNCTION(0x4, "uart3"),		/* CTS */
716		  SUNXI_FUNCTION_IRQ(0x6, 3),		/* EINT3 */
717		  SUNXI_FUNCTION(0x7, "csi1")),		/* D3 */
718	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
719		  SUNXI_FUNCTION(0x0, "gpio_in"),
720		  SUNXI_FUNCTION(0x1, "gpio_out"),
721		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D4 */
722		  SUNXI_FUNCTION(0x4, "uart4"),		/* TX */
723		  SUNXI_FUNCTION_IRQ(0x6, 4),		/* EINT4 */
724		  SUNXI_FUNCTION(0x7, "csi1")),		/* D4 */
725	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
726		  SUNXI_FUNCTION(0x0, "gpio_in"),
727		  SUNXI_FUNCTION(0x1, "gpio_out"),
728		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D5 */
729		  SUNXI_FUNCTION(0x4, "uart4"),		/* RX */
730		  SUNXI_FUNCTION_IRQ(0x6, 5),		/* EINT5 */
731		  SUNXI_FUNCTION(0x7, "csi1")),		/* D5 */
732	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
733		  SUNXI_FUNCTION(0x0, "gpio_in"),
734		  SUNXI_FUNCTION(0x1, "gpio_out"),
735		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D6 */
736		  SUNXI_FUNCTION(0x4, "uart5"),		/* TX */
737		  SUNXI_FUNCTION(0x5, "ms"),		/* BS */
738		  SUNXI_FUNCTION_IRQ(0x6, 6),		/* EINT6 */
739		  SUNXI_FUNCTION(0x7, "csi1")),		/* D6 */
740	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
741		  SUNXI_FUNCTION(0x0, "gpio_in"),
742		  SUNXI_FUNCTION(0x1, "gpio_out"),
743		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D7 */
744		  SUNXI_FUNCTION(0x4, "uart5"),		/* RX */
745		  SUNXI_FUNCTION(0x5, "ms"),		/* CLK */
746		  SUNXI_FUNCTION_IRQ(0x6, 7),		/* EINT7 */
747		  SUNXI_FUNCTION(0x7, "csi1")),		/* D7 */
748	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
749		  SUNXI_FUNCTION(0x0, "gpio_in"),
750		  SUNXI_FUNCTION(0x1, "gpio_out"),
751		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D8 */
752		  SUNXI_FUNCTION(0x3, "emac"),		/* ERXD3 */
753		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN0 */
754		  SUNXI_FUNCTION(0x5, "ms"),		/* D0 */
755		  SUNXI_FUNCTION_IRQ(0x6, 8),		/* EINT8 */
756		  SUNXI_FUNCTION(0x7, "csi1")),		/* D8 */
757	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
758		  SUNXI_FUNCTION(0x0, "gpio_in"),
759		  SUNXI_FUNCTION(0x1, "gpio_out"),
760		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D9 */
761		  SUNXI_FUNCTION(0x3, "emac"),		/* ERXD2 */
762		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN1 */
763		  SUNXI_FUNCTION(0x5, "ms"),		/* D1 */
764		  SUNXI_FUNCTION_IRQ(0x6, 9),		/* EINT9 */
765		  SUNXI_FUNCTION(0x7, "csi1")),		/* D9 */
766	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
767		  SUNXI_FUNCTION(0x0, "gpio_in"),
768		  SUNXI_FUNCTION(0x1, "gpio_out"),
769		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D10 */
770		  SUNXI_FUNCTION(0x3, "emac"),		/* ERXD1 */
771		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN2 */
772		  SUNXI_FUNCTION(0x5, "ms"),		/* D2 */
773		  SUNXI_FUNCTION_IRQ(0x6, 10),		/* EINT10 */
774		  SUNXI_FUNCTION(0x7, "csi1")),		/* D10 */
775	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
776		  SUNXI_FUNCTION(0x0, "gpio_in"),
777		  SUNXI_FUNCTION(0x1, "gpio_out"),
778		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D11 */
779		  SUNXI_FUNCTION(0x3, "emac"),		/* ERXD0 */
780		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN3 */
781		  SUNXI_FUNCTION(0x5, "ms"),		/* D3 */
782		  SUNXI_FUNCTION_IRQ(0x6, 11),		/* EINT11 */
783		  SUNXI_FUNCTION(0x7, "csi1")),		/* D11 */
784	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
785		  SUNXI_FUNCTION(0x0, "gpio_in"),
786		  SUNXI_FUNCTION(0x1, "gpio_out"),
787		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D12 */
788		  SUNXI_FUNCTION(0x4, "ps2"),		/* SCK1 */
789		  SUNXI_FUNCTION_IRQ(0x6, 12),		/* EINT12 */
790		  SUNXI_FUNCTION(0x7, "csi1")),		/* D12 */
791	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
792		  SUNXI_FUNCTION(0x0, "gpio_in"),
793		  SUNXI_FUNCTION(0x1, "gpio_out"),
794		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D13 */
795		  SUNXI_FUNCTION(0x4, "ps2"),		/* SDA1 */
796		  SUNXI_FUNCTION(0x5, "sim"),		/* RST */
797		  SUNXI_FUNCTION_IRQ(0x6, 13),		/* EINT13 */
798		  SUNXI_FUNCTION(0x7, "csi1")),		/* D13 */
799	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
800		  SUNXI_FUNCTION(0x0, "gpio_in"),
801		  SUNXI_FUNCTION(0x1, "gpio_out"),
802		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D14 */
803		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXD3 */
804		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN4 */
805		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPEN */
806		  SUNXI_FUNCTION_IRQ(0x6, 14),		/* EINT14 */
807		  SUNXI_FUNCTION(0x7, "csi1")),		/* D14 */
808	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
809		  SUNXI_FUNCTION(0x0, "gpio_in"),
810		  SUNXI_FUNCTION(0x1, "gpio_out"),
811		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D15 */
812		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXD3 */
813		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN5 */
814		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPPP */
815		  SUNXI_FUNCTION_IRQ(0x6, 15),		/* EINT15 */
816		  SUNXI_FUNCTION(0x7, "csi1")),		/* D15 */
817	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
818		  SUNXI_FUNCTION(0x0, "gpio_in"),
819		  SUNXI_FUNCTION(0x1, "gpio_out"),
820		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D16 */
821		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXD2 */
822		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN6 */
823		  SUNXI_FUNCTION_IRQ(0x6, 16),		/* EINT16 */
824		  SUNXI_FUNCTION(0x7, "csi1")),		/* D16 */
825	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
826		  SUNXI_FUNCTION(0x0, "gpio_in"),
827		  SUNXI_FUNCTION(0x1, "gpio_out"),
828		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D17 */
829		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXD1 */
830		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN7 */
831		  SUNXI_FUNCTION(0x5, "sim"),		/* VCCEN */
832		  SUNXI_FUNCTION_IRQ(0x6, 17),		/* EINT17 */
833		  SUNXI_FUNCTION(0x7, "csi1")),		/* D17 */
834	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
835		  SUNXI_FUNCTION(0x0, "gpio_in"),
836		  SUNXI_FUNCTION(0x1, "gpio_out"),
837		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D18 */
838		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXD0 */
839		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT0 */
840		  SUNXI_FUNCTION(0x5, "sim"),		/* SCK */
841		  SUNXI_FUNCTION_IRQ(0x6, 18),		/* EINT18 */
842		  SUNXI_FUNCTION(0x7, "csi1")),		/* D18 */
843	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
844		  SUNXI_FUNCTION(0x0, "gpio_in"),
845		  SUNXI_FUNCTION(0x1, "gpio_out"),
846		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D19 */
847		  SUNXI_FUNCTION(0x3, "emac"),		/* ERXERR */
848		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT1 */
849		  SUNXI_FUNCTION(0x5, "sim"),		/* SDA */
850		  SUNXI_FUNCTION_IRQ(0x6, 19),		/* EINT19 */
851		  SUNXI_FUNCTION(0x7, "csi1")),		/* D19 */
852	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
853		  SUNXI_FUNCTION(0x0, "gpio_in"),
854		  SUNXI_FUNCTION(0x1, "gpio_out"),
855		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D20 */
856		  SUNXI_FUNCTION(0x3, "emac"),		/* ERXDV */
857		  SUNXI_FUNCTION(0x4, "can"),		/* TX */
858		  SUNXI_FUNCTION_IRQ(0x6, 20),		/* EINT20 */
859		  SUNXI_FUNCTION(0x7, "csi1")),		/* D20 */
860	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
861		  SUNXI_FUNCTION(0x0, "gpio_in"),
862		  SUNXI_FUNCTION(0x1, "gpio_out"),
863		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D21 */
864		  SUNXI_FUNCTION(0x3, "emac"),		/* EMDC */
865		  SUNXI_FUNCTION(0x4, "can"),		/* RX */
866		  SUNXI_FUNCTION_IRQ(0x6, 21),		/* EINT21 */
867		  SUNXI_FUNCTION(0x7, "csi1")),		/* D21 */
868	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
869		  SUNXI_FUNCTION(0x0, "gpio_in"),
870		  SUNXI_FUNCTION(0x1, "gpio_out"),
871		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D22 */
872		  SUNXI_FUNCTION(0x3, "emac"),		/* EMDIO */
873		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT2 */
874		  SUNXI_FUNCTION(0x5, "mmc1"),		/* CMD */
875		  SUNXI_FUNCTION(0x7, "csi1")),		/* D22 */
876	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
877		  SUNXI_FUNCTION(0x0, "gpio_in"),
878		  SUNXI_FUNCTION(0x1, "gpio_out"),
879		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D23 */
880		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXEN */
881		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT3 */
882		  SUNXI_FUNCTION(0x5, "mmc1"),		/* CLK */
883		  SUNXI_FUNCTION(0x7, "csi1")),		/* D23 */
884	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
885		  SUNXI_FUNCTION(0x0, "gpio_in"),
886		  SUNXI_FUNCTION(0x1, "gpio_out"),
887		  SUNXI_FUNCTION(0x2, "lcd1"),		/* CLK */
888		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXCK */
889		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT4 */
890		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D0 */
891		  SUNXI_FUNCTION(0x7, "csi1")),		/* PCLK */
892	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
893		  SUNXI_FUNCTION(0x0, "gpio_in"),
894		  SUNXI_FUNCTION(0x1, "gpio_out"),
895		  SUNXI_FUNCTION(0x2, "lcd1"),		/* DE */
896		  SUNXI_FUNCTION(0x3, "emac"),		/* ECRS */
897		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT5 */
898		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D1 */
899		  SUNXI_FUNCTION(0x7, "csi1")),		/* FIELD */
900	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
901		  SUNXI_FUNCTION(0x0, "gpio_in"),
902		  SUNXI_FUNCTION(0x1, "gpio_out"),
903		  SUNXI_FUNCTION(0x2, "lcd1"),		/* HSYNC */
904		  SUNXI_FUNCTION(0x3, "emac"),		/* ECOL */
905		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT6 */
906		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D2 */
907		  SUNXI_FUNCTION(0x7, "csi1")),		/* HSYNC */
908	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
909		  SUNXI_FUNCTION(0x0, "gpio_in"),
910		  SUNXI_FUNCTION(0x1, "gpio_out"),
911		  SUNXI_FUNCTION(0x2, "lcd1"),		/* VSYNC */
912		  SUNXI_FUNCTION(0x3, "emac"),		/* ETXERR */
913		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT7 */
914		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D3 */
915		  SUNXI_FUNCTION(0x7, "csi1")),		/* VSYNC */
916	/* Hole */
917	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
918		  SUNXI_FUNCTION(0x0, "gpio_in"),
919		  SUNXI_FUNCTION(0x1, "gpio_out"),
920		  SUNXI_FUNCTION(0x3, "i2c3")),		/* SCK */
921	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
922		  SUNXI_FUNCTION(0x0, "gpio_in"),
923		  SUNXI_FUNCTION(0x1, "gpio_out"),
924		  SUNXI_FUNCTION(0x3, "i2c3")),		/* SDA */
925	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
926		  SUNXI_FUNCTION(0x0, "gpio_in"),
927		  SUNXI_FUNCTION(0x1, "gpio_out"),
928		  SUNXI_FUNCTION(0x3, "i2c4")),		/* SCK */
929	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
930		  SUNXI_FUNCTION(0x0, "gpio_in"),
931		  SUNXI_FUNCTION(0x1, "gpio_out"),
932		  SUNXI_FUNCTION(0x2, "pwm"),		/* PWM1 */
933		  SUNXI_FUNCTION(0x3, "i2c4")),		/* SDA */
934	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
935		  SUNXI_FUNCTION(0x0, "gpio_in"),
936		  SUNXI_FUNCTION(0x1, "gpio_out"),
937		  SUNXI_FUNCTION(0x2, "mmc3")),		/* CMD */
938	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
939		  SUNXI_FUNCTION(0x0, "gpio_in"),
940		  SUNXI_FUNCTION(0x1, "gpio_out"),
941		  SUNXI_FUNCTION(0x2, "mmc3")),		/* CLK */
942	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
943		  SUNXI_FUNCTION(0x0, "gpio_in"),
944		  SUNXI_FUNCTION(0x1, "gpio_out"),
945		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D0 */
946	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
947		  SUNXI_FUNCTION(0x0, "gpio_in"),
948		  SUNXI_FUNCTION(0x1, "gpio_out"),
949		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D1 */
950	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
951		  SUNXI_FUNCTION(0x0, "gpio_in"),
952		  SUNXI_FUNCTION(0x1, "gpio_out"),
953		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D2 */
954	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
955		  SUNXI_FUNCTION(0x0, "gpio_in"),
956		  SUNXI_FUNCTION(0x1, "gpio_out"),
957		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D3 */
958	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
959		  SUNXI_FUNCTION(0x0, "gpio_in"),
960		  SUNXI_FUNCTION(0x1, "gpio_out"),
961		  SUNXI_FUNCTION(0x2, "spi0"),		/* CS0 */
962		  SUNXI_FUNCTION(0x3, "uart5"),		/* TX */
963		  SUNXI_FUNCTION_IRQ(0x5, 22)),		/* EINT22 */
964	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
965		  SUNXI_FUNCTION(0x0, "gpio_in"),
966		  SUNXI_FUNCTION(0x1, "gpio_out"),
967		  SUNXI_FUNCTION(0x2, "spi0"),		/* CLK */
968		  SUNXI_FUNCTION(0x3, "uart5"),		/* RX */
969		  SUNXI_FUNCTION_IRQ(0x5, 23)),		/* EINT23 */
970	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
971		  SUNXI_FUNCTION(0x0, "gpio_in"),
972		  SUNXI_FUNCTION(0x1, "gpio_out"),
973		  SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */
974		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
975		  SUNXI_FUNCTION(0x4, "clk_out_a"),	/* CLK_OUT_A */
976		  SUNXI_FUNCTION_IRQ(0x5, 24)),		/* EINT24 */
977	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
978		  SUNXI_FUNCTION(0x0, "gpio_in"),
979		  SUNXI_FUNCTION(0x1, "gpio_out"),
980		  SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */
981		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
982		  SUNXI_FUNCTION(0x4, "clk_out_b"),	/* CLK_OUT_B */
983		  SUNXI_FUNCTION_IRQ(0x5, 25)),		/* EINT25 */
984	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
985		  SUNXI_FUNCTION(0x0, "gpio_in"),
986		  SUNXI_FUNCTION(0x1, "gpio_out"),
987		  SUNXI_FUNCTION(0x2, "spi0"),		/* CS1 */
988		  SUNXI_FUNCTION(0x3, "ps2"),		/* SCK1 */
989		  SUNXI_FUNCTION(0x4, "timer4"),	/* TCLKIN0 */
990		  SUNXI_FUNCTION_IRQ(0x5, 26)),		/* EINT26 */
991	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
992		  SUNXI_FUNCTION(0x0, "gpio_in"),
993		  SUNXI_FUNCTION(0x1, "gpio_out"),
994		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS1 */
995		  SUNXI_FUNCTION(0x3, "ps2"),		/* SDA1 */
996		  SUNXI_FUNCTION(0x4, "timer5"),	/* TCLKIN1 */
997		  SUNXI_FUNCTION_IRQ(0x5, 27)),		/* EINT27 */
998	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
999		  SUNXI_FUNCTION(0x0, "gpio_in"),
1000		  SUNXI_FUNCTION(0x1, "gpio_out"),
1001		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */
1002		  SUNXI_FUNCTION(0x3, "uart2"),		/* RTS */
1003		  SUNXI_FUNCTION_IRQ(0x5, 28)),		/* EINT28 */
1004	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
1005		  SUNXI_FUNCTION(0x0, "gpio_in"),
1006		  SUNXI_FUNCTION(0x1, "gpio_out"),
1007		  SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */
1008		  SUNXI_FUNCTION(0x3, "uart2"),		/* CTS */
1009		  SUNXI_FUNCTION_IRQ(0x5, 29)),		/* EINT29 */
1010	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
1011		  SUNXI_FUNCTION(0x0, "gpio_in"),
1012		  SUNXI_FUNCTION(0x1, "gpio_out"),
1013		  SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */
1014		  SUNXI_FUNCTION(0x3, "uart2"),		/* TX */
1015		  SUNXI_FUNCTION_IRQ(0x5, 30)),		/* EINT30 */
1016	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
1017		  SUNXI_FUNCTION(0x0, "gpio_in"),
1018		  SUNXI_FUNCTION(0x1, "gpio_out"),
1019		  SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */
1020		  SUNXI_FUNCTION(0x3, "uart2"),		/* RX */
1021		  SUNXI_FUNCTION_IRQ(0x5, 31)),		/* EINT31 */
1022	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
1023		  SUNXI_FUNCTION(0x0, "gpio_in"),
1024		  SUNXI_FUNCTION(0x1, "gpio_out"),
1025		  SUNXI_FUNCTION(0x2, "ps2"),		/* SCK0 */
1026		  SUNXI_FUNCTION(0x3, "uart7"),		/* TX */
1027		  SUNXI_FUNCTION(0x4, "hdmi")),		/* HSCL */
1028	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
1029		  SUNXI_FUNCTION(0x0, "gpio_in"),
1030		  SUNXI_FUNCTION(0x1, "gpio_out"),
1031		  SUNXI_FUNCTION(0x2, "ps2"),		/* SDA0 */
1032		  SUNXI_FUNCTION(0x3, "uart7"),		/* RX */
1033		  SUNXI_FUNCTION(0x4, "hdmi")),		/* HSDA */
1034};
1035
1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
1037	.pins = sun7i_a20_pins,
1038	.npins = ARRAY_SIZE(sun7i_a20_pins),
1039	.irq_banks = 1,
1040};
1041
1042static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
1043{
1044	return sunxi_pinctrl_init(pdev,
1045				  &sun7i_a20_pinctrl_data);
1046}
1047
1048static const struct of_device_id sun7i_a20_pinctrl_match[] = {
1049	{ .compatible = "allwinner,sun7i-a20-pinctrl", },
1050	{}
1051};
1052MODULE_DEVICE_TABLE(of, sun7i_a20_pinctrl_match);
1053
1054static struct platform_driver sun7i_a20_pinctrl_driver = {
1055	.probe	= sun7i_a20_pinctrl_probe,
1056	.driver	= {
1057		.name		= "sun7i-a20-pinctrl",
1058		.of_match_table	= sun7i_a20_pinctrl_match,
1059	},
1060};
1061module_platform_driver(sun7i_a20_pinctrl_driver);
1062
1063MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
1064MODULE_DESCRIPTION("Allwinner A20 pinctrl driver");
1065MODULE_LICENSE("GPL");
1066