Searched refs:CRn (Results 1 - 12 of 12) sorted by relevance

/linux-4.4.14/arch/arm64/kvm/
H A Dsys_regs.c444 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
447 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
450 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
453 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
458 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
477 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
480 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
483 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
489 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
492 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
510 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
513 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
516 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
519 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
522 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
525 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
528 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
531 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
535 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
538 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
541 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
545 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
549 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
552 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
555 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
558 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
561 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
564 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
568 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
571 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
574 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
577 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
580 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
584 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
587 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
591 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
594 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
598 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
602 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
605 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
609 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
612 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
616 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
620 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
624 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
627 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
630 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
633 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
636 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
639 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
642 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
645 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
648 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
651 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
654 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
657 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
660 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
664 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
667 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
671 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
674 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
677 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
750 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
752 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
754 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
756 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
759 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
768 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
770 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
774 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
777 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
779 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
782 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
784 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
789 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
791 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
794 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
806 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
810 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
813 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
817 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
820 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
834 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
837 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
839 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
841 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
843 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
845 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
847 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
865 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
867 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
868 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
869 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
870 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
871 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
872 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
873 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
874 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
875 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
876 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
877 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
882 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
883 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
884 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
887 { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
888 { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
889 { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
890 { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
891 { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
892 { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
893 { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
894 { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
895 { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
896 { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
897 { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
898 { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
899 { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
901 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
902 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
903 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
904 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
907 { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
909 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
913 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
914 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
915 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
957 if (params->CRn != r->CRn) find_reg()
1068 params.CRn = 0; kvm_handle_cp_64()
1116 params.CRn = (hsr >> 10) & 0xf; kvm_handle_cp_32()
1233 params.CRn = (esr >> 10) & 0xf; kvm_handle_sys_reg()
1267 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) index_to_params()
1347 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1349 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1351 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1353 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1355 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1357 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1359 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1361 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1363 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1365 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1367 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1369 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1371 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1373 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1375 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1377 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1379 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1381 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1383 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1597 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | sys_reg_to_index()
H A Dsys_regs.h28 u8 CRn; member in struct:sys_reg_params
41 u8 CRn; member in struct:sys_reg_desc
69 kvm_pr_unimpl(" { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n", print_sys_reg_instr()
70 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); print_sys_reg_instr()
132 if (i1->CRn != i2->CRn) cmp_sys_reg()
133 return i1->CRn - i2->CRn; cmp_sys_reg()
142 #define CRn(_x) .CRn = _x macro
H A Dsys_regs_generic_v8.c54 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
58 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
64 { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
/linux-4.4.14/arch/arm/kvm/
H A Dcoproc.c263 * CRn denotes the primary register number, but is copied to the CRm in the
266 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
271 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
275 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
279 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
283 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
288 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
290 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
292 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
298 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
302 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
304 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
306 { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
308 { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
312 { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
314 { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
323 { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
324 { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
325 { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
329 { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
331 { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
336 { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
337 { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
338 { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
339 { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
340 { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
341 { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
342 { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
343 { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
344 { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
345 { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
346 { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
347 { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
348 { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
351 { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
353 { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
357 { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
359 { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
363 { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
367 { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
369 { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
371 { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
373 { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
377 { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
381 { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
419 if (params->CRn != r->CRn) find_reg()
439 trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn, emulate_cp15()
477 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf; kvm_handle_cp15_64()
514 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf; kvm_handle_cp15_32()
540 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK) index_to_params()
557 /* CRm to CRn: see cp15_to_index for details */ index_to_params()
558 params->CRn = ((id & KVM_REG_ARM_CRM_MASK) index_to_params()
642 { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
643 { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
644 { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
645 { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
646 { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
648 { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
649 { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
650 { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
651 { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
652 { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
653 { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
654 { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
655 { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
657 { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
658 { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
659 { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
660 { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
661 { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
662 { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
664 { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
665 { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
1103 * CRn always denotes the primary coproc. reg. nr. for the cp15_to_index()
1109 val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT); cp15_to_index()
1115 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT); cp15_to_index()
H A Dcoproc.h23 unsigned long CRn; member in struct:coproc_params
35 unsigned long CRn; member in struct:coproc_reg
62 p->CRn, p->Op1, p->is_write ? "write" : "read"); print_cp_instr()
64 kvm_pr_unimpl(" { CRn(%2lu), CRm(%2lu), Op1(%2lu), Op2(%2lu), is32," print_cp_instr()
66 p->CRn, p->CRm, p->Op1, p->Op2, print_cp_instr()
136 if (i1->CRn != i2->CRn) cmp_reg()
137 return i1->CRn - i2->CRn; cmp_reg()
148 #define CRn(_x) .CRn = _x macro
150 #define CRm64(_x) .CRn = _x, .CRm = 0
H A Dcoproc_a15.c28 * CRn denotes the primary register number, but is copied to the CRm in the
31 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
36 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
H A Dcoproc_a7.c31 * CRn denotes the primary register number, but is copied to the CRm in the
34 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
39 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
H A Dtrace.h138 TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn,
140 TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
145 __field( unsigned int, CRn )
155 __entry->CRn = CRn;
162 __entry->Op1, __entry->Rt1, __entry->CRn,
/linux-4.4.14/arch/arm/include/asm/
H A Darch_gicv3.h26 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) p15, Op1, %0, CRn, CRm, Op2
/linux-4.4.14/arch/arm64/kernel/
H A Dcpufeature.c249 /* Op1 = 0, CRn = 0, CRm = 1 */
258 /* Op1 = 0, CRn = 0, CRm = 2 */
267 /* Op1 = 0, CRn = 0, CRm = 3 */
272 /* Op1 = 0, CRn = 0, CRm = 4 */
276 /* Op1 = 0, CRn = 0, CRm = 5 */
280 /* Op1 = 0, CRn = 0, CRm = 6 */
284 /* Op1 = 0, CRn = 0, CRm = 7 */
288 /* Op1 = 3, CRn = 0, CRm = 0 */
292 /* Op1 = 3, CRn = 14, CRm = 0 */
/linux-4.4.14/arch/arm64/include/asm/
H A Dsysreg.h31 * [15-12] : CRn
/linux-4.4.14/arch/arm/kernel/
H A Dtcm.c210 * | | | | | +----------- CRn 0 = 1001
226 * | | | | +--------------------- CRn

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