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Searched refs:POSTING_READ (Results 1 – 26 of 26) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Di915_irq.c94 POSTING_READ(GEN8_##type##_IMR(which)); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
104 POSTING_READ(type##IMR); \
107 POSTING_READ(type##IIR); \
109 POSTING_READ(type##IIR); \
121 POSTING_READ(reg); \
123 POSTING_READ(reg); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
138 POSTING_READ(type##IMR); \
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Dintel_hdmi.c167 POSTING_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
218 POSTING_READ(reg); in ibx_write_infoframe()
270 POSTING_READ(reg); in cpt_write_infoframe()
319 POSTING_READ(reg); in vlv_write_infoframe()
367 POSTING_READ(ctl_reg); in hsw_write_infoframe()
511 POSTING_READ(reg); in g4x_set_infoframes()
519 POSTING_READ(reg); in g4x_set_infoframes()
529 POSTING_READ(reg); in g4x_set_infoframes()
558 POSTING_READ(reg); in ibx_set_infoframes()
566 POSTING_READ(reg); in ibx_set_infoframes()
[all …]
Dintel_ddi.c365 POSTING_READ(_FDI_RXA_CTL); in hsw_fdi_link_train()
394 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
404 POSTING_READ(_FDI_RXA_CTL); in hsw_fdi_link_train()
413 POSTING_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
435 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
442 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
448 POSTING_READ(_FDI_RXA_CTL); in hsw_fdi_link_train()
455 POSTING_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
1555 POSTING_READ(DPLL_CTRL1); in intel_ddi_pre_enable()
1795 POSTING_READ(WRPLL_CTL(pll->id)); in hsw_ddi_pll_enable()
[all …]
Dintel_fifo_underrun.c113 POSTING_READ(reg); in i9xx_check_fifo_underruns()
133 POSTING_READ(reg); in i9xx_set_fifo_underrun_reporting()
188 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in broadwell_set_fifo_underrun_reporting()
Dintel_crt.c149 POSTING_READ(SPLL_CTL); in hsw_crt_pre_enable()
221 POSTING_READ(SPLL_CTL); in hsw_crt_post_disable()
363 POSTING_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
584 POSTING_READ(pipeconf_reg); in intel_crt_load_detect()
785 POSTING_READ(crt->adpa_reg); in intel_crt_reset()
Dintel_display.c1601 POSTING_READ(reg); in vlv_enable_pll()
1608 POSTING_READ(DPLL_MD(crtc->pipe)); in vlv_enable_pll()
1612 POSTING_READ(reg); in vlv_enable_pll()
1615 POSTING_READ(reg); in vlv_enable_pll()
1618 POSTING_READ(reg); in vlv_enable_pll()
1656 POSTING_READ(DPLL_MD(pipe)); in chv_enable_pll()
1705 POSTING_READ(reg); in i9xx_enable_pll()
1722 POSTING_READ(reg); in i9xx_enable_pll()
1725 POSTING_READ(reg); in i9xx_enable_pll()
1728 POSTING_READ(reg); in i9xx_enable_pll()
[all …]
Dintel_dp.c372 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
375 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
378 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
1512 POSTING_READ(DP_A); in ironlake_set_pll_cpu_edp()
1724 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_on()
1789 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_off_sync()
1880 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
1888 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
1896 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
1943 POSTING_READ(pp_ctrl_reg); in edp_panel_off()
[all …]
Dintel_panel.c800 POSTING_READ(BLC_PWM_PCH_CTL1); in bdw_enable_backlight()
836 POSTING_READ(BLC_PWM_CPU_CTL2); in pch_enable_backlight()
850 POSTING_READ(BLC_PWM_PCH_CTL1); in pch_enable_backlight()
878 POSTING_READ(BLC_PWM_CTL); in i9xx_enable_backlight()
920 POSTING_READ(BLC_PWM_CTL2); in i965_enable_backlight()
954 POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
Dintel_lrc.c317 POSTING_READ(RING_EXECLIST_STATUS(ring)); in execlists_elsp_write()
1142 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); in gen8_init_common_ring()
1148 POSTING_READ(RING_MODE_GEN7(ring)); in gen8_init_common_ring()
1224 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_logical_ring_get_irq()
1240 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_logical_ring_put_irq()
1911 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); in lrc_setup_hardware_status_page()
Dintel_i2c.c135 POSTING_READ(bus->gpio_reg); in set_clock()
152 POSTING_READ(bus->gpio_reg); in set_data()
Dintel_psr.c91 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
101 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
Dintel_ringbuffer.c511 POSTING_READ(mmio); in intel_ring_setup_status_page()
1415 POSTING_READ(RING_ACTHD(ring->mmio_base)); in gen6_ring_get_seqno()
1490 POSTING_READ(IMR); in i9xx_ring_get_irq()
1508 POSTING_READ(IMR); in i9xx_ring_put_irq()
1683 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_ring_get_irq()
1705 POSTING_READ(RING_IMR(ring->mmio_base)); in gen8_ring_put_irq()
2324 POSTING_READ(RING_TAIL(ring->mmio_base)); in gen6_bsd_ring_write_tail()
Dintel_lvds.c231 POSTING_READ(lvds_encoder->reg); in intel_enable_lvds()
262 POSTING_READ(lvds_encoder->reg); in intel_disable_lvds()
Di915_gem_gtt.c1032 POSTING_READ(RING_PP_DIR_DCLV(ring)); in gen6_mm_switch()
1623 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); in i915_check_and_clear_faults()
1632 POSTING_READ(GFX_FLSH_CNTL_GEN6); in i915_ggtt_flush()
1777 POSTING_READ(GFX_FLSH_CNTL_GEN6); in gen8_ggtt_insert_entries()
1821 POSTING_READ(GFX_FLSH_CNTL_GEN6); in gen6_ggtt_insert_entries()
Dintel_dsi.c320 POSTING_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_enable()
336 POSTING_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_disable()
Dintel_runtime_pm.c258 POSTING_READ(HSW_PWR_WELL_DRIVER); in hsw_set_power_well()
378 POSTING_READ(HSW_PWR_WELL_DRIVER); in skl_set_power_well()
Dintel_sprite.c292 POSTING_READ(PLANE_SURF(pipe, plane)); in skl_update_plane()
308 POSTING_READ(PLANE_SURF(pipe, plane)); in skl_disable_plane()
Dintel_uncore.c1358 POSTING_READ(VDECCLK_GATE_D); in g4x_do_reset()
1368 POSTING_READ(VDECCLK_GATE_D); in g4x_do_reset()
Dintel_tv.c1231 POSTING_READ(TV_DAC); in intel_tv_detect_type()
1261 POSTING_READ(TV_CTL); in intel_tv_detect_type()
Dintel_fbc.c180 POSTING_READ(MSG_FBC_REND_STATE); in intel_fbc_nuke()
Di915_gem.c3083 POSTING_READ(fence_reg); in i965_write_fence_reg()
3105 POSTING_READ(fence_reg + 4); in i965_write_fence_reg()
3108 POSTING_READ(fence_reg); in i965_write_fence_reg()
3111 POSTING_READ(fence_reg + 4); in i965_write_fence_reg()
3156 POSTING_READ(reg); in i915_write_fence_reg()
3188 POSTING_READ(FENCE_REG_830_0 + reg * 4); in i830_write_fence_reg()
Dintel_sdvo.c1450 POSTING_READ(intel_sdvo->sdvo_reg); in intel_disable_sdvo()
1454 POSTING_READ(intel_sdvo->sdvo_reg); in intel_disable_sdvo()
Di915_drv.c1238 POSTING_READ(VLV_GTLC_WAKE_CTRL); in vlv_allow_gt_wake()
Dintel_pm.c903 POSTING_READ(DSPFW1); in vlv_write_wm_values()
3774 POSTING_READ(VIDSTART); in ironlake_enable_drps()
3986 POSTING_READ(GEN6_RPNSWREQ); in gen6_set_rps()
5567 POSTING_READ(ECR); in intel_init_emon()
Di915_drv.h3202 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) macro
Di915_debugfs.c3662 POSTING_READ(PIPE_CRC_CTL(pipe)); in pipe_crc_set_source()