1601 	POSTING_READ(reg);  in vlv_enable_pll()
1608 	POSTING_READ(DPLL_MD(crtc->pipe));  in vlv_enable_pll()
1612 	POSTING_READ(reg);  in vlv_enable_pll()
1615 	POSTING_READ(reg);  in vlv_enable_pll()
1618 	POSTING_READ(reg);  in vlv_enable_pll()
1656 	POSTING_READ(DPLL_MD(pipe));  in chv_enable_pll()
1705 	POSTING_READ(reg);  in i9xx_enable_pll()
1722 	POSTING_READ(reg);  in i9xx_enable_pll()
1725 	POSTING_READ(reg);  in i9xx_enable_pll()
1728 	POSTING_READ(reg);  in i9xx_enable_pll()
1766 	POSTING_READ(DPLL(pipe));  in i9xx_disable_pll()
1783 	POSTING_READ(DPLL(pipe));  in vlv_disable_pll()
1800 	POSTING_READ(DPLL(pipe));  in chv_disable_pll()
2133 	POSTING_READ(reg);  in intel_enable_pipe()
2195 	POSTING_READ(reg);  in intel_flush_primary_plane()
2685 		POSTING_READ(reg);  in i9xx_update_primary_plane()
2791 	POSTING_READ(reg);  in i9xx_update_primary_plane()
2811 		POSTING_READ(reg);  in ironlake_update_primary_plane()
2893 	POSTING_READ(reg);  in ironlake_update_primary_plane()
2956 		POSTING_READ(PLANE_CTL(pipe, 0));  in skylake_update_primary_plane()
3029 	POSTING_READ(PLANE_SURF(pipe, 0));  in skylake_update_primary_plane()
3269 	POSTING_READ(reg);  in intel_fdi_normal_train()
3315 	POSTING_READ(reg);  in ironlake_fdi_link_train()
3350 	POSTING_READ(reg);  in ironlake_fdi_link_train()
3395 	POSTING_READ(reg);  in gen6_fdi_link_train()
3424 	POSTING_READ(reg);  in gen6_fdi_link_train()
3434 		POSTING_READ(reg);  in gen6_fdi_link_train()
3477 	POSTING_READ(reg);  in gen6_fdi_link_train()
3487 		POSTING_READ(reg);  in gen6_fdi_link_train()
3527 	POSTING_READ(reg);  in ivb_manual_fdi_link_train()
3569 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
3604 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
3645 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
3652 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
3661 		POSTING_READ(reg);  in ironlake_fdi_pll_enable()
3683 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
3691 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
3707 	POSTING_READ(reg);  in ironlake_fdi_disable()
3715 	POSTING_READ(reg);  in ironlake_fdi_disable()
3743 	POSTING_READ(reg);  in ironlake_fdi_disable()
3951 	POSTING_READ(SOUTH_CHICKEN1);  in cpt_set_fdi_bc_bifurcation()
4387 		POSTING_READ(IPS_CTL);  in hsw_disable_ips()
6778 	POSTING_READ(PIPECONF(intel_crtc->pipe));  in i9xx_set_pipeconf()
7231 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
7247 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
7258 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
7269 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
7557 	POSTING_READ(PIPECONF(pipe));  in ironlake_set_pipeconf()
7644 	POSTING_READ(PIPECONF(cpu_transcoder));  in haswell_set_pipeconf()
7647 	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));  in haswell_set_pipeconf()
8307 		POSTING_READ(D_COMP_BDW);  in hsw_write_dcomp()
8341 	POSTING_READ(LCPLL_CTL);  in hsw_disable_lcpll()
8359 		POSTING_READ(LCPLL_CTL);  in hsw_disable_lcpll()
8386 		POSTING_READ(LCPLL_CTL);  in hsw_restore_lcpll()
8685 		POSTING_READ(_CURACNTR);  in i845_update_cursor()
8701 		POSTING_READ(_CURACNTR);  in i845_update_cursor()
8742 		POSTING_READ(CURCNTR(pipe));  in i9xx_update_cursor()
8748 	POSTING_READ(CURBASE(pipe));  in i9xx_update_cursor()
9942 	POSTING_READ(PLANE_SURF(pipe, 0));  in skl_do_mmio_flip()
9967 	POSTING_READ(DSPSURF(intel_crtc->plane));  in ilk_do_mmio_flip()
12273 	POSTING_READ(PCH_DPLL(pll->id));  in ibx_pch_dpll_enable()
12282 	POSTING_READ(PCH_DPLL(pll->id));  in ibx_pch_dpll_enable()
12299 	POSTING_READ(PCH_DPLL(pll->id));  in ibx_pch_dpll_disable()
13749 	POSTING_READ(vga_reg);  in i915_disable_vga()