/linux-4.4.14/drivers/media/usb/gspca/m5602/ |
H A D | m5602_s5k4aa.h | 46 #define S5K4AA_H_BLANK_HI__ 0x1d 97 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 104 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 116 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 120 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 140 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 147 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 159 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 163 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00},
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H A D | m5602_s5k83a.h | 75 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 93 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 108 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00}, 126 {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00},
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/linux-4.4.14/drivers/media/usb/gspca/ |
H A D | ov534.c | 162 {0x1d, 0x48}, 163 {0x1d, 0x00}, 164 {0x1d, 0xff}, 165 {0x1d, 0x02}, 166 {0x1d, 0x58}, 167 {0x1d, 0x00}, 169 {0x1d, 0x0a}, 170 {0x1d, 0x0e}, 205 {0x7c, 0x1d}, 246 {0x37, 0x1d}, 367 {0x1d, 0x0a}, 394 {0x1d, 0x48}, /* output YUV422 */ 406 {0x1d, 0x0a}, 454 { 0x1d, 0x40 }, 455 { 0x1d, 0x02 }, /* payload size 0x0200 * 4 = 2048 bytes */ 456 { 0x1d, 0x00 }, /* payload size */ 458 { 0x1d, 0x02 }, /* frame size 0x025800 * 4 = 614400 */ 459 { 0x1d, 0x58 }, /* frame size */ 460 { 0x1d, 0x00 }, /* frame size */ 463 { 0x1d, 0x08 }, /* turn on UVC header */ 464 { 0x1d, 0x0e }, /* .. */ 569 {0x1d, 0x40}, 570 {0x1d, 0x02}, 571 {0x1d, 0x00}, 572 {0x1d, 0x02}, 573 {0x1d, 0x58}, 574 {0x1d, 0x00}, 590 {0x1d, 0x40}, 591 {0x1d, 0x02}, 592 {0x1d, 0x00}, 593 {0x1d, 0x01}, 594 {0x1d, 0x4b}, 595 {0x1d, 0x00},
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H A D | ov534_9.c | 177 {0x1d, 0x48}, 178 {0x1d, 0x00}, 179 {0x1d, 0xff}, 181 {0x1d, 0x2e}, 182 {0x1d, 0x1e}, 215 {0x1d, 0x48}, 216 {0x1d, 0x00}, 217 {0x1d, 0xff}, 219 {0x1d, 0x2e}, /* for Iso */ 220 {0x1d, 0x1e}, 253 {0x1d, 0x48}, 254 {0x1d, 0x00}, 255 {0x1d, 0xff}, 257 {0x1d, 0x2e}, /* for Iso */ 258 {0x1d, 0x1e}, 292 {0x1d, 0x48}, 293 {0x1d, 0x00}, 294 {0x1d, 0xff}, 296 {0x1d, 0x2e}, /* for Iso */ 297 {0x1d, 0x1e}, 331 {0x1d, 0x48}, 332 {0x1d, 0x00}, 333 {0x1d, 0xff}, 335 {0x1d, 0x2e}, /* for Iso */ 336 {0x1d, 0x1e}, 370 {0x1d, 0x48}, 371 {0x1d, 0x00}, 372 {0x1d, 0xff}, 374 {0x1d, 0x2e}, /* for Iso */ 375 {0x1d, 0x1e}, 397 {0x1d, 0x48}, 427 {0x17, 0x1d}, /* hstart*/ 759 {0x17, 0x1d}, /* hstart */ 782 {0x17, 0x1d}, /* hstart */ 805 {0x17, 0x1d}, /* hstart */ 1009 {0x1d, 0x48}, 1010 {0x1d, 0x00}, 1011 {0x1d, 0xff}, 1013 {0x1d, 0x2e}, 1014 {0x1d, 0x1e}, 1471 reg_w(gspca_dev, 0x1d, 0x00); sd_init()
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H A D | spca505.c | 287 {0x06, 0xe2, 0x1d}, 519 {0x04, 0x1d, 0x00}, /* imagetype (1d) */ 534 {0x06, 0xe2, 0x1d}, 645 {0x02, 0x1c, 0x1d}, /* 320x240 */ sd_start()
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H A D | conex.c | 376 {0x20, 0x1d, 0x1d, 0x20, 0x41, 0x2e, 0x31, 0x26}, 459 {0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25, 0x1d}, 488 {0x13, 0x11, 0x11, 0x13, 0x26, 0x1b, 0x1d, 0x17}, 577 {0x14, 0x1d, 0x1a, 0x1f, 0x1e, 0x1d, 0x1a, 0x1c},
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H A D | sunplus.c | 208 0x16, 0x1c, 0x1d, 0x1d, 0x22, 0x1e, 0x1f, 0x1e}, 233 0x16, 0x1c, 0x1d, 0x1d, 0x1d /* 0x22 */ , 0x1e, 0x1f, 0x1e, 638 reg_w_riv(gspca_dev, 0x1d, 0x00, 0); sd_init()
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/linux-4.4.14/arch/arm/mach-imx/ |
H A D | mach-imx6sx.c | 26 phy_write(dev, 0x1d, 0x1f); ar8031_phy_fixup() 30 phy_write(dev, 0x1d, 0x5); ar8031_phy_fixup()
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H A D | mach-imx7d.c | 25 phy_write(dev, 0x1d, 0x1f); ar8031_phy_fixup() 37 phy_write(dev, 0x1d, 0x5); ar8031_phy_fixup()
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/linux-4.4.14/drivers/media/dvb-frontends/ |
H A D | itd1000.c | 211 { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 212 { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 213 { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 214 { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } }, 216 { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } }, 217 { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } }, 218 { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } }, 219 { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } }, 220 { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
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H A D | lgdt330x_priv.h | 37 TIMING_RECOVERY= 0x1d,
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H A D | stv0900_init.h | 210 { STV0900_8PSK_23, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 215 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, 217 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, 219 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }, 497 { R0900_GENCFG , 0x1d },
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H A D | mb86a16_priv.h | 100 #define MB86A16_DCC8 0x1d
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/linux-4.4.14/lib/raid6/ |
H A D | mmx.c | 26 u64 x1d; member in struct:raid6_mmx_constants 52 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); raid6_mmx1_gen_syndrome() 100 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); raid6_mmx2_gen_syndrome()
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H A D | sse1.c | 31 u64 x1d; member in struct:raid6_mmx_constants 57 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); raid6_sse11_gen_syndrome() 116 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); raid6_sse12_gen_syndrome()
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H A D | avx2.c | 28 u64 x1d[4]; member in struct:raid6_avx2_constants 54 asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0])); raid6_avx21_gen_syndrome() 113 asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0])); raid6_avx22_gen_syndrome() 177 asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0])); raid6_avx24_gen_syndrome()
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H A D | mktables.c | 31 a = (a << 1) ^ (a & 0x80 ? 0x1d : 0); gfmul()
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H A D | sse2.c | 24 u64 x1d[2]; member in struct:raid6_sse_constants 53 asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0])); raid6_sse21_gen_syndrome() 105 asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0])); raid6_sse21_xor_syndrome() 163 asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0])); raid6_sse22_gen_syndrome() 216 asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0])); raid6_sse22_xor_syndrome() 295 asm volatile("movdqa %0,%%xmm0" :: "m" (raid6_sse_constants.x1d[0])); raid6_sse24_gen_syndrome() 382 asm volatile("movdqa %0,%%xmm0" :: "m" (raid6_sse_constants.x1d[0])); raid6_sse24_xor_syndrome()
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/linux-4.4.14/drivers/media/rc/keymaps/ |
H A D | rc-evga-indtube.c | 26 { 0x1d, KEY_VOLUMEUP},
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H A D | rc-twinhan1027.c | 16 { 0x1d, KEY_5 },
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H A D | rc-apac-viewcomp.c | 49 { 0x1d, KEY_PLAYPAUSE }, /* stop */
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H A D | rc-cinergy-1400.c | 50 { 0x1d, KEY_MUTE },
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H A D | rc-cinergy.c | 47 { 0x1d, KEY_FORWARD },
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H A D | rc-dntv-live-dvb-t.c | 51 { 0x1d, KEY_RECORD }, /* record */
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H A D | rc-dntv-live-dvbt-pro.c | 30 { 0x1d, KEY_5 },
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H A D | rc-encore-enltv-fm53.c | 25 { 0x1d, KEY_2},
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H A D | rc-flydvb.c | 39 { 0x1d, KEY_ENTER }, /* Enter */
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H A D | rc-genius-tvgo-a11mce.c | 25 { 0x1d, KEY_2 },
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H A D | rc-gotview7135.c | 46 { 0x1d, KEY_REWIND },
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H A D | rc-kaiomy.c | 60 { 0x1d, KEY_GREEN},
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H A D | rc-kworld-pc150u.c | 25 { 0x1d, KEY_POWER2 },
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H A D | rc-npgtech.c | 17 { 0x1d, KEY_SWITCHVIDEOMODE }, /* switch inputs */
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H A D | rc-pctv-sedna.c | 49 { 0x1d, KEY_RECORD },
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H A D | rc-pinnacle-grey.c | 51 { 0x1d, KEY_MENU },
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H A D | rc-pixelview.c | 56 { 0x1d, KEY_REFRESH }, /* reset */
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H A D | rc-purpletv.c | 38 { 0x1d, KEY_DOWN },
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H A D | rc-pv951.c | 37 { 0x1d, KEY_PAGEDOWN },
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H A D | rc-real-audio-220-32-keys.c | 50 { 0x1d, KEY_RECORD},
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H A D | rc-technisat-ts35.c | 41 {0x1d, KEY_BACK},
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H A D | rc-terratec-cinergy-c-pci.c | 46 { 0x1d, KEY_MENU}, /* DVD Menu */
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H A D | rc-terratec-cinergy-s2-hd.c | 29 { 0x1d, KEY_MENU}, /* DVD-Menu */
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H A D | rc-terratec-cinergy-xs.c | 55 { 0x1d, KEY_MUTE},
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H A D | rc-tevii-nec.c | 48 { 0x1d, KEY_BACK},
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H A D | rc-twinhan-dtv-cab-ci.c | 55 { 0x1d, KEY_NEXT}, /* Skip >| */
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H A D | rc-videomate-m1f.c | 58 { 0x1d, KEY_0 },
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H A D | rc-videomate-s350.c | 37 { 0x1d, KEY_8},
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H A D | rc-videomate-tv-pvr.c | 57 { 0x1d, KEY_8 },
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H A D | rc-avermedia-cardbus.c | 46 { 0x1d, KEY_REWIND },
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H A D | rc-behold.c | 103 /* 0x1d 0x13 0x19 *
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H A D | rc-budget-ci-old.c | 43 { 0x1d, KEY_DOWN },
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H A D | rc-encore-enltv.c | 38 { 0x1d, KEY_9 },
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H A D | rc-eztv.c | 31 { 0x1d, KEY_RESTART }, /* playback / angle / del */
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H A D | rc-kworld-plus-tv-analog.c | 23 { 0x1d, KEY_POWER2 },
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H A D | rc-manli.c | 109 /* 0x1d unused ? */
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H A D | rc-snapstream-firefly.c | 51 { 0x1d, KEY_LEFT },
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H A D | rc-medion-x10-digitainer.c | 49 { 0x1d, KEY_LEFT },
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H A D | rc-medion-x10-or2x.c | 53 { 0x1d, KEY_LEFT },
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H A D | rc-medion-x10.c | 71 { 0x1d, KEY_LEFT }, /* left */
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H A D | rc-msi-tvanywhere-plus.c | 98 { 0x1d, KEY_RESTART }, /* Reset */
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H A D | rc-ati-x10.c | 87 { 0x1d, KEY_LEFT }, /* left */
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/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/asm/ |
H A D | cpu_vect.h | 36 #define BREAK_13_INTR_VECT 0x1d
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/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/ |
H A D | cpu_vect.h | 36 #define BREAK_13_INTR_VECT 0x1d
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/linux-4.4.14/sound/soc/codecs/ |
H A D | wm8770.h | 46 #define WM8770_OUTMUX2 0x1d
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H A D | wm8974.h | 36 #define WM8974_NOTCH3 0x1d
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H A D | wm8978.h | 43 #define WM8978_NOTCH_FILTER_3 0x1d
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H A D | wm8510.h | 36 #define WM8510_NOTCH3 0x1d
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H A D | cs42l56.h | 45 #define CS42L56_GAIN_BIAS_CTL 0x1d 172 #define CS42L56_MCLK_LRCLK_768 0x1d
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H A D | wm8960.h | 44 #define WM8960_APOP2 0x1d
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H A D | ak4671.h | 46 #define AK4671_DIGITAL_FILTER_SELECT 0x1d
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H A D | nau8825.h | 41 #define NAU8825_REG_I2S_PCM_CTRL2 0x1d 217 /* I2S_PCM_CTRL2 (0x1d) */
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H A D | es8328.h | 162 #define ES8328_DACCONTROL7 0x1d
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H A D | rt286.h | 30 #define RT286_BEEP 0x1d
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H A D | rt298.h | 31 #define RT298_BEEP 0x1d
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H A D | sta32x.h | 53 #define STA32X_A1CF1 0x1d
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H A D | sta350.h | 55 #define STA350_A1CF1 0x1d
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/linux-4.4.14/include/linux/mfd/pcf50633/ |
H A D | pmic.h | 10 #define PCF50633_REG_AUTOMXC 0x1d
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/linux-4.4.14/drivers/cpufreq/ |
H A D | longhaul.h | 331 0x00, 0x10, 0x0f, 0x1f, 0x0e, 0x1e, 0x0d, 0x1d, 348 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
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/linux-4.4.14/drivers/gpu/drm/i810/ |
H A D | i810_drv.h | 218 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 224 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 225 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 226 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x2) 227 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 228 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
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/linux-4.4.14/drivers/media/tuners/ |
H A D | fc0013.c | 199 ret = fc0013_readreg(priv, 0x1d, &tmp); fc0013_set_vhf_track() 204 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c); fc0013_set_vhf_track() 206 ret = fc0013_writereg(priv, 0x1d, tmp | 0x18); fc0013_set_vhf_track() 208 ret = fc0013_writereg(priv, 0x1d, tmp | 0x14); fc0013_set_vhf_track() 210 ret = fc0013_writereg(priv, 0x1d, tmp | 0x10); fc0013_set_vhf_track() 212 ret = fc0013_writereg(priv, 0x1d, tmp | 0x0c); fc0013_set_vhf_track() 214 ret = fc0013_writereg(priv, 0x1d, tmp | 0x08); fc0013_set_vhf_track() 216 ret = fc0013_writereg(priv, 0x1d, tmp | 0x04); fc0013_set_vhf_track() 218 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c); fc0013_set_vhf_track()
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H A D | tda18271-maps.c | 71 { .lomax = 607000, .pd = 0x1d, .d = 0x0d }, 243 { .rfmax = 46200, .val = 0x1d }, 272 { .rfmax = 157800, .val = 0x1d }, 376 { .rfmax = 72000, .val = 0x1d }, 472 { .rfmax = 178000, .val = 0x1d }, 511 { .rfmax = 240000, .val = 0x1d }, 640 { .rfmax = 511000, .val = 0x1d }, 821 { .rfmax = 366000, .val = 0x1d }, 859 { .rfmax = 522000, .val = 0x1d }, 1211 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ 1215 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ 1246 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ 1248 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */
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H A D | mt2266.c | 117 static u8 mt2266_uhf[] = { 0x1d, 0xdc, 0x00, 0x0a, 0xd4, 0x03, 0x64, 0x64, 120 static u8 mt2266_vhf[] = { 0x1d, 0xfe, 0x00, 0x00, 0xb4, 0x03, 0xa5, 0xa5,
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H A D | e4000_priv.h | 136 { 4480000, 0xfc, 0x1d },
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H A D | tda18218_priv.h | 55 #define R1D_PSM2 0x1d /* PSM byte 2 */
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/linux-4.4.14/drivers/video/fbdev/ |
H A D | bw2.c | 197 0x1c, 0x00, 0x1d, 0x0a, 0x1e, 0xff, 0x1f, 0x01, 204 0x1c, 0x00, 0x1d, 0x08, 0x1e, 0xff, 0x1f, 0x01, 211 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01, 218 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01, 225 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
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H A D | cg3.c | 285 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01, 292 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01, 299 0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
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/linux-4.4.14/drivers/video/fbdev/sis/ |
H A D | oem300.h | 421 {0xf3,0x00,0x1d,0x20}, 439 {0xf3,0x00,0x1d,0x20}, 457 {0xf3,0x00,0x1d,0x20}, 493 {0xf3,0x00,0x1d,0x20}, 511 {0xf3,0x00,0x1d,0x20}, 529 {0xf3,0x00,0x1d,0x20}, 705 { 0x1d, 0x1c, 0x00 }, 714 { 0x1d, 0x1c, 0x00 }, 722 { 0x1d, 0x1c, 0x00 }, 734 { 0x1d, 0x1c, 0x00 }, 744 { 0x1d, 0x1c, 0x00 }, 752 { 0x1d, 0x1c, 0x00 }, 762 { 0x1d, 0x1c, 0x00 }, 771 { 0x1d, 0x1c, 0x00 }, 782 { 0x1d, 0x1c, 0x00 }, 794 { 0x1d, 0x1c, 0x00 }, 806 { 0x1d, 0x1c, 0x00 }, 815 { 0x1d, 0x1c, 0x00 }, 823 { 0x1d, 0x1c, 0x00 },
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H A D | 310vtbl.h | 148 {0x1d,0x6a1b,0x0000,SIS_RI_960x540, 0x00,0x00,0x00,0x00,0x53,-1}, /* 960x540 */ 189 {0x0137,0x1d,0x19,0x07,0x07,0x3a,1280,1024, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 0x1b */ 191 {0x0207,0x1f,0x20,0x00,0x07,0x3a,1280,1024, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 0x1d */ 245 {0x0067,0x52,0x6a,0x00,0x1c,0x1d, 960, 540, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 0x53 960x540 60Hz */ 246 {0x0077,0x53,0x6b,0x0b,0x1d,0x20, 960, 600, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 0x54 960x600 60Hz */ 300 {{0x7d,0x63,0x63,0x81,0x6e,0x1d,0x98,0xf0, 344 0x01}}, /* 0x1d */ 372 {{0x40,0xef,0xef,0x84,0x03,0x1d,0xda,0x1f, 381 {{0x40,0xef,0xef,0x84,0x03,0x1d,0xda,0x1f, 384 {{0x40,0xef,0xef,0x84,0x03,0x1d,0xda,0x1f, 387 {{0x40,0xef,0xef,0x84,0x03,0x1d,0xda,0x1f, 465 {{0x83,0x69,0x69,0x87,0x6f,0x1d,0x03,0x3E, /* 848x480-60 */ 537 {{0x7f,0x63,0x63,0x83,0x6d,0x1d,0x0b,0x3e, /* 800x480 (wide) 60 Hz */ 699 { 0xe0,0x46,132}, /* 0x1d */ 822 { 0xe0,0x46,132}, /* 0x1d */ 1249 {{0xe5,0x7f,0xb7,0x1d,0xa7,0x3e,0x04,0x5a,0x05,0x00,0x80,0x20,0x3e,0xe4,0x22,0x00}} 1303 {{0xe5,0x7f,0xb7,0x1d,0xa7,0x3e,0x04,0x6e,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x03}} 1307 {{0xe5,0x7f,0xb7,0x1d,0xa7,0x3e,0x04,0x5a,0x05,0x00,0x80,0x1a,0x33,0x3f,0x2f,0x00}} 1323 {{0xe4,0x7f,0xb7,0x1e,0xaf,0x29,0x37,0x5a,0x05,0x00,0x80,0x1d,0xf1,0x6c,0xcb,0x00}}
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/linux-4.4.14/drivers/staging/comedi/drivers/ |
H A D | ni_labpc_regs.h | 68 #define STAT2_REG 0x1d /* R: Status 2 reg */
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/linux-4.4.14/drivers/hid/ |
H A D | hid-roccat-isku.h | 23 ISKU_SIZE_KEYS_MEDIA = 0x1d,
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/linux-4.4.14/include/uapi/linux/ |
H A D | serio.h | 52 #define SERIO_IFORCE 0x1d
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/linux-4.4.14/arch/powerpc/platforms/52xx/ |
H A D | lite5200_sleep.S | 65 stw r10, (0x1d*4)(r4) 243 lwz r10, (0x1d*4)(r4) 284 /* 0x1d reserved by 0xf0 */ 357 * 0x1d - reserved by 0xf0 (BDI2000)
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/linux-4.4.14/arch/mips/include/asm/ |
H A D | cacheops.h | 80 #define Index_Store_Data_D 0x1d
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/linux-4.4.14/drivers/media/platform/sti/bdisp/ |
H A D | bdisp-filter.h | 103 0x02, 0x01, 0xf9, 0x2d, 0x1d, 0xf5, 0x06, 0xff, 117 0x04, 0xff, 0xfd, 0x29, 0x1d, 0xf7, 0x02, 0x01, 131 0x01, 0xf8, 0x08, 0x25, 0x1d, 0x01, 0xf9, 0x03, 256 0xf5, 0x1d, 0x33, 0x00, 0xfb, 271 0x01, 0x1d, 0x22, 0x07, 0xf9,
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/linux-4.4.14/drivers/usb/misc/sisusbvga/ |
H A D | sisusb_init.h | 163 static const unsigned short ModeIndex_960x540[] = { 0x1d, 0x1e, 0x00, 0x1f }; 261 {1680, 1050, 8, 16}, /* 0x1d */ 318 {0x52, 0xba1b, 0x0134, SIS_RI_512x384, 0x00, 0x00, 0x00, 0x00, 0x1d, 4}, /* 512x384x8 */ 321 {0x58, 0xba1d, 0x0137, SIS_RI_512x384, 0x00, 0x00, 0x00, 0x00, 0x1d, 4}, /* 512x384x16 */ 323 {0x5c, 0xba1f, 0x0000, SIS_RI_512x384, 0x00, 0x00, 0x00, 0x00, 0x1d, 4}, /* 512x384x32 */ 360 {0x1d, 0x6a1b, 0x0000, SIS_RI_960x540, 0x00, 0x00, 0x00, 0x00, 0x2d, -1}, /* 960x540 */ 408 {0xc077, 0x03, 0x0b, 0x06, 0x06, 0x52, 512, 384, 0x30, 0x00, 0x00}, /* 0x1d */ 424 {0x0067, 0x52, 0x6a, 0x00, 0x1c, 0x1d, 960, 540, 0x30, 0x00, 0x00}, /* 0x2d 960x540 60Hz */ 425 {0x0077, 0x53, 0x6b, 0x0b, 0x1d, 0x20, 960, 600, 0x30, 0x00, 0x00}, /* 0x2e 960x600 60Hz */ 427 {0x0137, 0x1d, 0x19, 0x07, 0x07, 0x3a, 1280, 1024, 0x00, 0x00, 0x00}, /* 0x30 */ 482 {{0x7d, 0x63, 0x63, 0x81, 0x6e, 0x1d, 0x98, 0xf0, 526 0x01}}, /* 0x1d */ 554 {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f, 563 {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f, 566 {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f, 569 {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f, 647 {{0x83, 0x69, 0x69, 0x87, 0x6f, 0x1d, 0x03, 0x3E, 724 {0xe0, 0x46, 132}, /* 0x1d */
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/linux-4.4.14/drivers/net/wireless/realtek/rtl818x/rtl8180/ |
H A D | rtl8225se.c | 39 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 51 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 60 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 102 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
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/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gca/ |
H A D | gfx_8_1_sh_mask.h | 62 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 80 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 98 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 116 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 134 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 152 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 170 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 188 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 324 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 360 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 396 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 432 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 468 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 504 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 540 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 576 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 992 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d 1142 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 1814 #define CP_DFY_CNTL__MODE__SHIFT 0x1d 2012 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2042 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d 2072 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d 2102 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d 2132 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d 2162 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d 2192 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d 2222 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d 2298 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 2308 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 2318 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 2460 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2484 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2508 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2532 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2556 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2580 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2604 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2628 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2652 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2676 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2700 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2724 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2748 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2772 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2796 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2820 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2844 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2868 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2892 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 2916 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 3062 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d 3122 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d 3250 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d 3292 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d 3432 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d 3590 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d 3660 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 3674 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 3726 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d 3786 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d 3802 #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d 3828 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d 3844 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d 3854 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d 3976 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d 4030 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d 4146 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d 4192 #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d 4372 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 4426 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d 4468 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d 4496 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d 4540 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d 4640 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d 4728 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d 4742 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d 4838 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d 5148 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d 5188 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d 5248 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d 5292 #define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d 5362 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d 5932 #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d 6066 #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d 6104 #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d 6124 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d 6146 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d 6168 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d 6190 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d 6226 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 6330 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d 7002 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d 7518 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d 7928 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d 8110 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d 8130 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 8186 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d 8218 #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d 8254 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d 8274 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d 8288 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d 8308 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d 8322 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d 8342 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d 8356 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d 8376 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d 8390 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d 8430 #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d 8458 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d 8494 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d 8548 #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d 8572 #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d 8596 #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d 8620 #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d 8702 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d 8732 #define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d 8768 #define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d 9074 #define RLC_MC_CNTL__RESERVED__SHIFT 0x1d 9368 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d 9692 #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d 12958 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d 12980 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 13002 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 13772 #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d 13930 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d 13944 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d 14306 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 14318 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 14406 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d 14434 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d 14618 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d 14644 #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d 14740 #define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d 14822 #define SQ_WAVE_MODE__CSP__SHIFT 0x1d 14830 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d 15044 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d 15318 #define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d 15430 #define SQ_VOP3_1__NEG__SHIFT 0x1d 15536 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d 15558 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d 15580 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d 15602 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d 15624 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d 15688 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d 15752 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d 15816 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d 15998 #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d 16146 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16166 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16440 #define TA_STATUS__FA_BUSY__SHIFT 0x1d 16534 #define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d 16580 #define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d 16784 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d 16976 #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d 16986 #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d 16996 #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d 17006 #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d 17052 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 17072 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 17092 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 17112 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 17272 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 17366 #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d 17820 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d 17884 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d 18620 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d 18640 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 18660 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d 18772 #define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d 18814 #define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d 18856 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d 18918 #define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d 18976 #define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d 19038 #define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d 19082 #define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d 19124 #define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d 19218 #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d 19264 #define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 19326 #define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d 19388 #define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d 19450 #define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d 19504 #define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d 19564 #define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d 19702 #define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 19766 #define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d 19830 #define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d 19846 #define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d 19944 #define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d 19990 #define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d 20072 #define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d 20158 #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d 20186 #define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d 20238 #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d 20302 #define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d 20366 #define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d 20426 #define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d 20640 #define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d 20698 #define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d 20762 #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d 20878 #define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d 20936 #define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
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H A D | gfx_8_0_sh_mask.h | 60 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 78 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 96 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 114 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 132 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 150 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 168 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 186 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 322 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 358 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 394 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 430 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 466 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 502 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 538 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 574 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 990 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d 1132 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 1292 #define CP_DFY_CNTL__MODE__SHIFT 0x1d 1488 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1518 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d 1548 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d 1578 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d 1608 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d 1638 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d 1668 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d 1698 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d 1774 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 1784 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 1794 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 1938 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1962 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1986 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2010 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2034 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2058 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2082 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2106 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2130 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2154 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2178 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2202 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2226 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2250 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2274 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2298 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2322 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2346 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2370 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 2394 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 2540 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d 2600 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d 2728 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d 2770 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d 2910 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d 3068 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d 3138 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 3152 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 3204 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d 3264 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d 3280 #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d 3306 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d 3322 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d 3332 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d 3454 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d 3508 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d 3624 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d 3670 #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d 3850 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 3904 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d 3946 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d 3974 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d 4018 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d 4118 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d 4206 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d 4220 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d 4316 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d 4624 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d 4664 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d 4724 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d 4762 #define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d 4832 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d 5402 #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d 5538 #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d 5576 #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d 5596 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d 5618 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d 5640 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d 5662 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d 5692 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 5796 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d 6468 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d 6982 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d 7392 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d 7556 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d 7576 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 7632 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d 7664 #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d 7700 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d 7720 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d 7734 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d 7754 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d 7768 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d 7788 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7802 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7822 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7836 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7876 #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d 7904 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d 7940 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d 7994 #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d 8018 #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d 8042 #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d 8066 #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d 8148 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d 8178 #define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d 8214 #define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d 8520 #define RLC_MC_CNTL__RESERVED__SHIFT 0x1d 8818 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d 9150 #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d 12568 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d 12590 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 12612 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 13382 #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d 13540 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d 13554 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d 13916 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 13928 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 14016 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d 14044 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d 14228 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d 14254 #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d 14350 #define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d 14432 #define SQ_WAVE_MODE__CSP__SHIFT 0x1d 14440 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d 14654 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d 14928 #define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d 15040 #define SQ_VOP3_1__NEG__SHIFT 0x1d 15146 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d 15168 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d 15190 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d 15212 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d 15234 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d 15298 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d 15362 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d 15426 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d 15584 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 15604 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 15868 #define TA_STATUS__FA_BUSY__SHIFT 0x1d 15962 #define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d 16008 #define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d 16212 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d 16402 #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d 16410 #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d 16418 #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d 16426 #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d 16472 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16492 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16512 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16532 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16692 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16788 #define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d 17240 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d 17304 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d 18040 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d 18060 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 18080 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d 18192 #define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d 18234 #define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d 18276 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d 18338 #define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d 18396 #define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d 18458 #define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d 18490 #define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d 18532 #define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d 18626 #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d 18672 #define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 18734 #define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d 18796 #define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d 18858 #define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d 18912 #define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d 18972 #define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d 19110 #define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 19174 #define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d 19238 #define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d 19254 #define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d 19352 #define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d 19398 #define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d 19480 #define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d 19566 #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d 19594 #define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d 19646 #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d 19710 #define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d 19774 #define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d 19834 #define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d 20048 #define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d 20106 #define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d 20170 #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d 20286 #define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d 20344 #define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
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H A D | gfx_7_2_sh_mask.h | 54 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 72 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 90 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 108 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 126 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 144 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 162 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 180 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 776 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d 886 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 1166 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1190 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d 1214 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d 1238 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d 1262 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d 1286 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d 1310 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d 1334 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d 1504 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1524 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1544 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1564 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1584 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1604 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1624 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1644 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1664 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1684 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1704 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1724 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1744 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1764 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1784 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1804 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1824 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1844 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 1864 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 1884 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 2008 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d 2068 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d 2196 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d 2224 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d 2362 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d 2512 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d 2574 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 2588 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 2638 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d 2694 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d 2710 #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d 2736 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d 2752 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d 2762 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d 2840 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d 2898 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d 3008 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d 3056 #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d 3230 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 3332 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d 3358 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d 3396 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d 3488 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d 3500 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d 3592 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d 3898 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d 3938 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d 3998 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d 4034 #define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d 4104 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d 4674 #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d 4792 #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d 4828 #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d 4848 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d 4870 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d 4892 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d 4914 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d 4942 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 5042 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d 5680 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d 6194 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d 6604 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d 6768 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d 6788 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 6844 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d 6876 #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d 6912 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d 6932 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d 6946 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d 6966 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d 6980 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d 7000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7014 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7034 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7048 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7088 #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d 7116 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d 7152 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d 7206 #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d 7230 #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d 7254 #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d 7278 #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d 7360 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d 7390 #define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d 7426 #define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d 7710 #define RLC_MC_CNTL__RESERVED__SHIFT 0x1d 7900 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d 10836 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d 10858 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 10880 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 11640 #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d 11744 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d 12160 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d 12188 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d 12364 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d 12388 #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d 12544 #define SQ_WAVE_MODE__CSP__SHIFT 0x1d 12550 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d 12800 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d 13134 #define SQ_VOP3_1__NEG__SHIFT 0x1d 13210 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d 13232 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d 13254 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d 13276 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d 13298 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d 13362 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d 13426 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d 13490 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d 13634 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 13654 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 13674 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 13978 #define TA_STATUS__FA_BUSY__SHIFT 0x1d 14058 #define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d 14104 #define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d 14304 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d 14494 #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d 14502 #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d 14510 #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d 14518 #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d 14536 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14556 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14576 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14596 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14724 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 14820 #define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d 15272 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d 15336 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d 15890 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d 15910 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 15930 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d 16040 #define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d 16082 #define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d 16124 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d 16186 #define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d 16244 #define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d 16306 #define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d 16352 #define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 16414 #define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d 16476 #define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d 16538 #define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d 16592 #define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d 16652 #define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d 16790 #define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 16854 #define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d 16918 #define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d 16934 #define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d 17032 #define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d 17078 #define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d 17160 #define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d 17246 #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d 17274 #define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d 17326 #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d 17390 #define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d 17454 #define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d 17514 #define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d 17728 #define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d 17786 #define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d 17902 #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d 18018 #define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d 18076 #define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d 18118 #define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x1d
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H A D | gfx_7_2_enum.h | 149 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, 429 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, 624 DB_PERF_SEL_DB_SC_quad_sends = 0x1d, 911 GRBM_PERF_SEL_CPG_BUSY = 0x1d, 1015 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, 1170 SC_SUPERTILE_PER_PRIM_H5 = 0x1d, 1693 SPI_PERF_ES_LAST_WAVE = 0x1d, 2110 SQ_PERF_SEL_INSTS_VMEM = 0x1d, 2617 #define SQ_S_BITSET1_B32 0x1d 2735 #define SQ_V_CMPX_NEQ_F32 0x1d 3019 #define SQ_BUFFER_STORE_DWORDX2 0x1d 3082 #define SQ_DS_GWS_BARRIER 0x1d 3230 #define SQ_IMAGE_ATOMIC_FCMPSWAP 0x1d 3341 #define SQ_S_DCACHE_INV_VOL 0x1d 3488 #define SQ_V_XOR_B32 0x1d 3520 #define SQ_FLAT_STORE_DWORDX2 0x1d 3674 #define SQ_S_XNOR_B64 0x1d 3832 TVX_FMT_32_32 = 0x1d, 3914 TVX_Inst_Gather4_C = 0x1d, 3977 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1d, 4119 TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL = 0x1d, 4262 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, 4399 TA_PERF_SEL_RESERVED_29 = 0x1d, 4512 TD_PERF_SEL_RESERVED_29 = 0x1d, 4569 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, 4803 FLUSH_GS_OUTPUT = 0x1d, 4998 vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, 5288 DBG_CLIENT_BLKID_mcb = 0x1d, 5439 DBG_BLOCK_ID_UVDM = 0x1d, 5673 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 5791 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 5995 FMT_24_8_FLOAT = 0x1d, 6079 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | gfx_8_1_enum.h | 155 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, 614 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, 818 DB_PERF_SEL_DB_SC_quad_sends = 0x1d, 1114 GRBM_PERF_SEL_CPG_BUSY = 0x1d, 1218 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, 1373 SC_SUPERTILE_PER_PRIM_H5 = 0x1d, 1898 SPI_PERF_ES_LAST_WAVE = 0x1d, 2331 SQ_PERF_SEL_INSTS_VMEM = 0x1d, 2900 #define SQ_S_SETPC_B64 0x1d 3524 #define SQ_BUFFER_STORE_DWORDX2 0x1d 3773 #define SQ_V_CEIL_F32 0x1d 3860 #define SQ_S_SET_GPR_IDX_MODE 0x1d 3898 #define SQ_V_SUBB_U32 0x1d 3932 #define SQ_FLAT_STORE_DWORDX2 0x1d 4128 #define SQ_S_LSHL_B64 0x1d 4319 TVX_FMT_32_32 = 0x1d, 4401 TVX_Inst_Gather4_C = 0x1d, 4464 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d, 4606 TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d, 4844 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, 4890 TA_PERF_SEL_RESERVED_29 = 0x1d, 5011 TD_PERF_SEL_bicubic_filter_wavefront = 0x1d, 5069 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, 5355 FLUSH_GS_OUTPUT = 0x1d, 5556 vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, 5730 wd_perf_se1_hs_done_latency = 0x1d, 5786 DBG_BLOCK_ID_VGT1 = 0x1d, 6043 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 6165 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 6227 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 6460 COLOR_RESERVED_29 = 0x1d, 6493 FMT_24_8_FLOAT = 0x1d, 6577 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | gfx_8_0_enum.h | 155 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, 605 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, 809 DB_PERF_SEL_DB_SC_quad_sends = 0x1d, 1096 GRBM_PERF_SEL_CPG_BUSY = 0x1d, 1200 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, 1355 SC_SUPERTILE_PER_PRIM_H5 = 0x1d, 1880 SPI_PERF_ES_LAST_WAVE = 0x1d, 2313 SQ_PERF_SEL_INSTS_VMEM = 0x1d, 2882 #define SQ_S_SETPC_B64 0x1d 3506 #define SQ_BUFFER_STORE_DWORDX2 0x1d 3755 #define SQ_V_CEIL_F32 0x1d 3840 #define SQ_S_SET_GPR_IDX_MODE 0x1d 3878 #define SQ_V_SUBB_U32 0x1d 3912 #define SQ_FLAT_STORE_DWORDX2 0x1d 4106 #define SQ_S_LSHL_B64 0x1d 4264 TVX_FMT_32_32 = 0x1d, 4346 TVX_Inst_Gather4_C = 0x1d, 4409 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d, 4551 TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d, 4789 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, 4835 TA_PERF_SEL_RESERVED_29 = 0x1d, 4956 TD_PERF_SEL_bicubic_filter_wavefront = 0x1d, 5013 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, 5286 FLUSH_GS_OUTPUT = 0x1d, 5487 vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, 5661 wd_perf_se1_hs_done_latency = 0x1d, 5821 DBG_CLIENT_BLKID_sx20 = 0x1d, 5981 DBG_BLOCK_ID_UVDM = 0x1d, 6215 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 6333 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 6543 FMT_24_8_FLOAT = 0x1d, 6627 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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/linux-4.4.14/drivers/staging/fbtft/ |
H A D | fb_hx8357d.c | 86 0x1d, init_display() 102 0x1d, init_display()
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/linux-4.4.14/drivers/media/pci/ttpci/ |
H A D | ttpci-eeprom.c | 68 0x1d, 0x36, 0x64, 0x78}; getmac_tt() 93 0x1d, 0x36, 0x64, 0x78}; ttpci_eeprom_decode_mac()
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/linux-4.4.14/arch/unicore32/include/asm/ |
H A D | irq.h | 47 #define IRQ_TIMER3 0x1d
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/linux-4.4.14/lib/ |
H A D | bitrev.c | 34 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
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/linux-4.4.14/include/video/ |
H A D | mipi_display.h | 55 MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
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H A D | cirrus.h | 59 #define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */ 72 #define CL_CRT1D 0x1d /* Overlay Extended Control register */
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/linux-4.4.14/include/linux/ulpi/ |
H A D | regs.h | 30 #define ULPI_CARKIT_INT_EN 0x1d
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/linux-4.4.14/include/linux/ |
H A D | asn1_ber_bytecode.h | 66 ASN1_OP_COMPLETE = 0x1d,
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/linux-4.4.14/arch/mips/kernel/ |
H A D | mips-cm.c | 77 [0x1d] = "0x1d", 129 "0x1c", "0x1d", "0x1e", "0x1f" 138 "0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
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/linux-4.4.14/arch/m68k/include/asm/ |
H A D | amipcmcia.h | 89 #define CISTPL_DEVICE_OA 0x1d
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H A D | m5206sim.h | 34 #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
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H A D | m520xsim.h | 31 #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
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H A D | m68360_regs.h | 189 #define CPMVEC_SCC2 0x1d 221 /* #define CPMVEC_SCC2 ((ushort)0x1d) */
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/linux-4.4.14/arch/microblaze/kernel/cpu/ |
H A D | cpuinfo.c | 47 {"9.1", 0x1d},
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/linux-4.4.14/arch/arm/mach-omap2/ |
H A D | omap-secure.h | 38 #define OMAP4_HAL_SAVEGIC_INDEX 0x1d
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/linux-4.4.14/drivers/net/wireless/p54/ |
H A D | p54spi_eeprom.h | 236 0x1d, 0x7a, 0x1d, 0x7a, 0x1d, 0x7a, 0x1d, 0x7a, 471 0x1d, 0x71, 0x1d, 0x71, 0x1d, 0x71, 0x1d, 0x71, 472 0x1d, 0x71, 0x1d, 0x71, 0x1d, 0x71, 0x1d, 0x71,
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/linux-4.4.14/fs/nls/ |
H A D | nls_ascii.c | 63 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 86 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 105 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_cp1251.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 189 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 224 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_cp855.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 185 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 221 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_cp857.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 187 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 223 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_cp866.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 191 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 227 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_cp874.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 159 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 195 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_iso8859-1.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 143 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 179 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_iso8859-13.c | 101 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 171 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 207 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_iso8859-5.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 158 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 194 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_iso8859-6.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 150 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 186 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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H A D | nls_iso8859-9.c | 103 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 158 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */ 194 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 0x18-0x1f */
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/linux-4.4.14/sound/pci/hda/ |
H A D | patch_analog.c | 292 { 0x1d, 0x90a7013e }, /* int mic */ 300 { 0x1d, 0x90a7013e }, /* int mic */ 312 { 0x1d, 0x01a19020 }, /* rear mic */ 325 { 0x1d, 0x411111f0 }, /* N/A */ 335 { 0x1d, 0x90a7013e }, /* int mic */ 355 { 0x1d, 0x90a70130 }, /* int mic */ 408 0x1d, 0x05, patch_ad1986a() 830 .path = { 0x02, 0x1d, 0x1b }, ad1988_add_spdif_mux_ctl() 836 .path = { 0x08, 0x0b, 0x1d, 0x1b }, ad1988_add_spdif_mux_ctl() 842 .path = { 0x09, 0x0b, 0x1d, 0x1b }, ad1988_add_spdif_mux_ctl() 848 .path = { 0x0f, 0x0b, 0x1d, 0x1b }, ad1988_add_spdif_mux_ctl() 856 get_wcaps_type(get_wcaps(codec, 0x1d)) != AC_WID_AUD_MIX) ad1988_add_spdif_mux_ctl()
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/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_8_2_enum.h | 57 DBG_BLOCK_ID_VGT1 = 0x1d, 314 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 436 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 498 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 753 FMT_24_8_FLOAT = 0x1d, 837 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | gmc_8_1_enum.h | 161 DBG_CLIENT_BLKID_sx20 = 0x1d, 321 DBG_BLOCK_ID_UVDM = 0x1d, 555 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 673 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 883 FMT_24_8_FLOAT = 0x1d, 967 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | gmc_7_0_sh_mask.h | 142 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d 364 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d 666 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d 714 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d 988 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d 1044 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d 1778 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d 3888 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 4386 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4396 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4406 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4416 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4426 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4436 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4446 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4456 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4466 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4476 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4486 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4496 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4506 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4516 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4526 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4536 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4546 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4556 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4566 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4576 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4586 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4596 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4606 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4616 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4626 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4636 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4646 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4656 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4666 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4676 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4788 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4798 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5162 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d 5328 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 6038 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d
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H A D | gmc_8_2_sh_mask.h | 188 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d 460 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d 762 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d 810 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d 1054 #define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d 1126 #define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d 1198 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d 1284 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d 2100 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d 4798 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 5300 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5310 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5320 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5330 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5340 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5350 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5360 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5370 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5380 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5390 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5400 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5410 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5420 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5430 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5440 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5450 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5460 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5470 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5480 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5490 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5500 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5510 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5520 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5530 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5540 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5550 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5560 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5570 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5580 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5590 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5702 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5712 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5740 #define MC_GRUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5750 #define MC_GRUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5908 #define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d 6270 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d 6306 #define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d 6362 #define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d 6450 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 6724 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d 6734 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d 7484 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d 7680 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d 7712 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d 7744 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d 7776 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
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/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/smu/ |
H A D | smu_7_1_0_enum.h | 205 DBG_CLIENT_BLKID_mcb = 0x1d, 356 DBG_BLOCK_ID_UVDM = 0x1d, 590 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 708 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 912 FMT_24_8_FLOAT = 0x1d, 996 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | smu_7_1_1_enum.h | 211 DBG_CLIENT_BLKID_smu_2 = 0x1d, 351 DBG_BLOCK_ID_UVDM = 0x1d, 585 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 703 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 913 FMT_24_8_FLOAT = 0x1d, 997 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | smu_8_0_enum.h | 57 DBG_BLOCK_ID_VGT1 = 0x1d, 314 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 436 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 498 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 753 FMT_24_8_FLOAT = 0x1d, 837 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | smu_7_1_1_sh_mask.h | 214 #define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d 542 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 792 #define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d 3376 #define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d 3660 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d 3724 #define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3786 #define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3848 #define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3910 #define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3972 #define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4034 #define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4096 #define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4158 #define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4224 #define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d 4394 #define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4408 #define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4422 #define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4436 #define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4450 #define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4464 #define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4478 #define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4492 #define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4506 #define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4520 #define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4534 #define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4548 #define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4562 #define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4576 #define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4590 #define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4604 #define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
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/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_5_0_enum.h | 174 DBG_CLIENT_BLKID_sx20 = 0x1d, 334 DBG_BLOCK_ID_UVDM = 0x1d, 568 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 686 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 896 FMT_24_8_FLOAT = 0x1d, 980 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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H A D | uvd_6_0_enum.h | 70 DBG_BLOCK_ID_VGT1 = 0x1d, 327 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 449 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 511 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 766 FMT_24_8_FLOAT = 0x1d, 850 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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/linux-4.4.14/crypto/ |
H A D | fcrypt.c | 94 Z(0x3d), Z(0xe5), Z(0xb3), Z(0x5b), Z(0xae), Z(0xd5), Z(0xad), Z(0x1d), 142 Z(0x80), Z(0x48), Z(0x81), Z(0xb7), Z(0x1d), Z(0x43), Z(0xd9), Z(0xd7), 163 Z(0x3f), Z(0x09), Z(0xa3), Z(0x8d), Z(0xfb), Z(0xed), Z(0xda), Z(0x1d), 201 Z(0x2a), Z(0x41), Z(0xb2), Z(0x42), Z(0x0c), Z(0xed), Z(0x0c), Z(0x1d), 208 Z(0x17), Z(0xe4), Z(0x01), Z(0x1d), Z(0x4c), Z(0xa9), Z(0xcc), Z(0x85), 218 Z(0xd3), Z(0xb7), Z(0x95), Z(0x49), Z(0xcf), Z(0xc3), Z(0x1d), Z(0x8f),
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H A D | testmgr.h | 176 "\x5e\x32\x39\x6d\xc1\x1d\x7d\x50\x3b\x9f\x7a\xad\xf0\x2e\x25\x53" 349 .digest = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46" 389 .digest = "\xd4\x1d\x8c\xd9\x8f\x00\xb2\x04" 455 .digest = "\xfd\x2a\xa6\x07\xf7\x1d\xc8\xf5" 677 "\xe9\x15\xeb\x8f\xea\x1d\x05\x24\x95\x5f" 797 "\x4d\xe4\x58\xef\x86\x1d\x91\x28" 807 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56" 817 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84" 866 "\x1d\x91\x28\xbf\x33\xca\x61\xf8" 875 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4" 885 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2" 971 "\x4d\xe4\x58\xef\x86\x1d\x91\x28" 981 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56" 991 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84" 1040 "\x1d\x91\x28\xbf\x33\xca\x61\xf8" 1049 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4" 1059 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2" 1144 "\x4d\xe4\x58\xef\x86\x1d\x91\x28" 1154 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56" 1164 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84" 1213 "\x1d\x91\x28\xbf\x33\xca\x61\xf8" 1222 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4" 1232 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2" 1336 "\x4d\xe4\x58\xef\x86\x1d\x91\x28" 1346 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56" 1356 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84" 1405 "\x1d\x91\x28\xbf\x33\xca\x61\xf8" 1414 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4" 1424 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2" 1495 "\xaa\x1d\x3b\xea\x57\x78\x9c\xa0" 1496 "\x31\xad\x85\xc7\xa7\x1d\xd7\x03" 1506 "\x50\x1d\x28\x9e\x49\x00\xf7\xe4" 1540 "\x4d\xe4\x58\xef\x86\x1d\x91\x28" 1550 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56" 1560 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84" 1609 "\x1d\x91\x28\xbf\x33\xca\x61\xf8" 1618 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4" 1628 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2" 1961 "\xdd\x68\x15\x1d\x50\x39\x74\xfc", 2006 "\xdd\x68\x15\x1d", 2157 .digest = "\xad\xb1\xc1\xe9\x56\x70\x31\x1d" 2194 .digest = "\x56\xbe\x34\x52\x1d\x14\x4c\x88" 2295 "\x1c\x15\x5f\x0d\x55\x1d\x9a\x3a", 2375 .digest = "\x76\x19\x69\x39\x78\xf9\x1d\x90\x53\x9a" 2615 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20", 2627 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20", 2639 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20", 2688 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 2752 .digest = "\xbb\x1d\x69\x29\xe9\x59\x37\x28" 2877 .digest = "\x75\xf0\x25\x1d\x52\x8a\xc0\x1c" 2916 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 2927 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 3029 .digest = "\x25\x31\x98\xbc\x1d\xe8\x67\x60", 3156 "\x4f\xf0\xb4\x24\x1a\x1d\x6c\xb0" 3522 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d", 3545 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d" 3556 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d", 3564 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d" 3577 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d" 3591 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d" 3603 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d" 3613 .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d", 3694 .input = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d", 3708 .input = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d" 3719 .input = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d" 8699 .result = "\xd2\xaf\x69\x35\x24\x1d\x0e\x1c" 8734 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 8806 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 8835 "\xe7\x10\x7a\xdf\xb2\xbd\xf1\x1d" 8842 "\x31\x9d\xef\xb1\x1d\x27\x55\x04" 8847 "\x1d\x28\x14\xfd\xb1\x1a\x34\x18" 8849 "\x8e\xb2\x58\x1d\x28\x17\x13\x3d" 8867 "\x93\x51\x1d\x3d\x62\x59\x83\x82" 8949 .input = "\xd2\xaf\x69\x35\x24\x1d\x0e\x1c" 8987 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 9023 "\xe7\x10\x7a\xdf\xb2\xbd\xf1\x1d" 9030 "\x31\x9d\xef\xb1\x1d\x27\x55\x04" 9035 "\x1d\x28\x14\xfd\xb1\x1a\x34\x18" 9037 "\x8e\xb2\x58\x1d\x28\x17\x13\x3d" 9055 "\x93\x51\x1d\x3d\x62\x59\x83\x82" 9124 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 9215 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9247 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9285 "\x78\x1d\xc2\xa9\xc2\x73\x00\xc3" 9357 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9389 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9563 "\x78\x1d\xc2\xa9\xc2\x73\x00\xc3" 9623 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9655 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9765 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9797 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 9877 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 10066 .key = "\x1f\x1e\x1d\x1c\x1b\x1a\x19\x18" 10103 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 10279 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 11493 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 11565 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 11584 "\x15\xb1\x50\x8c\x9a\xd8\x99\x1d" 11605 "\x5c\x3c\x08\x1d\x4c\x06\x9f\xb8" 11746 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 11772 "\x15\xb1\x50\x8c\x9a\xd8\x99\x1d" 11793 "\x5c\x3c\x08\x1d\x4c\x06\x9f\xb8" 11883 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 11922 .result = "\xe1\x08\xb8\x1d\x2c\xf5\x33\x64" 11974 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 12006 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 12077 "\xb1\x10\x6e\x36\x1d\xe1\xc4\x80" 12097 "\xef\x91\x64\x1d\x18\x07\x4e\x31" 12116 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 12148 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 12190 "\x49\xb0\x1d\xea\x78\x9e\x00\xca" 12232 "\x45\xfb\xe9\xd3\x1d\x39\x2f\xd6" 12260 .input = "\xe1\x08\xb8\x1d\x2c\xf5\x33\x64" 12355 "\xb1\x10\x6e\x36\x1d\xe1\xc4\x80" 12375 "\xef\x91\x64\x1d\x18\x07\x4e\x31" 12382 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 12414 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 12468 "\x49\xb0\x1d\xea\x78\x9e\x00\xca" 12510 "\x45\xfb\xe9\xd3\x1d\x39\x2f\xd6" 12524 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 12556 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 13600 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 13812 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 13852 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 13884 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 14066 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 14098 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 14196 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 14368 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 14538 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 14561 .result = "\x4f\x02\x1d\xb2\x43\xbc\x63\x3d" 14765 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 14774 .input = "\x4f\x02\x1d\xb2\x43\xbc\x63\x3d" 15094 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 15175 "\x1d\xbe\xc6\xe9", 15202 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 15253 .result = "\x4f\x02\x1d\xb2\x43\xbc\x63\x3d" 15458 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 15499 "\xe7\xc6\xce\x10\x31\x2f\x9b\x1d" 15572 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 15625 .result = "\x4f\x02\x1d\xb2\x43\xbc\x63\x3d" 15753 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 15807 "\xac\x7f\x5c\x1d\xf5\xee\x22\x66" 15891 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 15952 .result = "\x4f\x02\x1d\xb2\x43\xbc\x63\x3d" 16065 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1" 16126 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1" 16188 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1" 16253 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1" 16322 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1" 16338 "\xd9\x1d\xc3\xe3\x05\xac\x76\xfb" 16772 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 16845 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 16863 .result = "\x1a\x1d\xa9\x30\xad\xf9\x2f\x9b" 16864 "\xb6\x1d\xae\xef\xf0\x2f\xf8\x5a" 16872 "\x0e\x84\x23\x1d\x16\xd4\x1c\x59" 16873 "\x9c\x1a\x02\x55\xab\x3a\x97\x1d" 16890 "\x41\x30\x58\xc5\x62\x74\x52\x1d" 17026 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 17052 .input = "\x1a\x1d\xa9\x30\xad\xf9\x2f\x9b" 17053 "\xb6\x1d\xae\xef\xf0\x2f\xf8\x5a" 17061 "\x0e\x84\x23\x1d\x16\xd4\x1c\x59" 17062 "\x9c\x1a\x02\x55\xab\x3a\x97\x1d" 17079 "\x41\x30\x58\xc5\x62\x74\x52\x1d" 17164 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 17255 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17287 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17397 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17429 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17662 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17694 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17804 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17836 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 17895 "\x1e\x03\x1d\xda\x2f\xbe\x03\xd1" 17919 "\xd1\xbd\x1d\x66\x56\x20\xab\xf7" 18241 "\x1e\x03\x1d\xda\x2f\xbe\x03\xd1" 18265 "\xd1\xbd\x1d\x66\x56\x20\xab\xf7" 18604 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 18633 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 18641 .key = "\x77\x6b\xef\xf2\x85\x1d\xb0\x6f" 18650 .result = "\x14\x5a\xd0\x1d\xbf\x82\x4e\xc7" 18664 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 18669 "\x55\x30\x83\x1d\x93\x44\xaf\x1c", 18676 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 18684 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 18724 "\x08\x0b\x0e\x11\x14\x17\x1a\x1d" 18752 "\x18\x1d\x22\x27\x2c\x31\x36\x3b" 18800 "\x08\x0f\x16\x1d\x24\x2b\x32\x39" 18823 "\xf0\xf9\x02\x0b\x14\x1d\x26\x2f" 18855 "\xd0\xdb\xe6\xf1\xfc\x07\x12\x1d" 18883 "\x10\x1d\x2a\x37\x44\x51\x5e\x6b" 18907 "\xf0\xff\x0e\x1d\x2c\x3b\x4a\x59" 18946 "\xc8\xd9\xea\xfb\x0c\x1d\x2e\x3f" 18970 "\x98\xab\xbe\xd1\xe4\xf7\x0a\x1d" 19030 "\x08\x1d\x32\x47\x5c\x71\x86\x9b" 19062 "\xd8\xef\x06\x1d\x34\x4b\x62\x79" 19085 "\xa0\xb9\xd2\xeb\x04\x1d\x36\x4f" 19101 "\x60\x7b\x96\xb1\xcc\xe7\x02\x1d" 19129 "\x00\x1d\x3a\x57\x74\x91\xae\xcb" 19169 "\xc0\xdf\xfe\x1d\x3c\x5b\x7a\x99" 19253 "\x93\x97\xc6\x48\x45\x1d\x9f\x83" 19284 "\xe0\x1d\x2a\x18\xd2\xc0\x54\xa8" 19287 "\x43\x2d\x9a\xcb\x92\x3f\x5a\x1d" 19292 "\xda\xf0\xbf\x9b\xc8\x1d\xe5\xf8" 19318 "\x58\xe1\x9f\x89\x35\x9d\x1d\x21" 19430 "\xa8\x89\x32\x5c\x37\x25\x1d\xb2" 19461 "\x57\xcd\x11\x4f\x11\x04\x8e\x1d" 19517 "\x66\x56\x5f\x1d\x02\x19\xe2\xf6" 19526 "\x64\x3b\x4b\x19\xa1\x13\x64\x1d" 19557 "\x4c\x21\x87\xcb\xc9\x1d\x16\x96" 19561 "\x92\x61\xd0\x48\x81\xed\x5e\x1d" 19588 "\x19\x1d\x41\x50\xe9\xd8\xf0\x32" 19603 "\x1d\x08\x57\xce\x09\xb8\xf6\xcd" 19633 "\x1f\xb7\x29\x0a\x45\xa1\x1d\x1e" 19634 "\x1d\xe2\x65\x61\x50\x9c\xd7\x05" 19651 "\x58\x27\x01\xc4\xbf\xa7\xa1\x1d" 19657 "\xb8\xb0\xd3\x86\xba\x1d\xd7\x90" 19705 "\x2a\xed\x7e\xb1\x1d\xd6\x4c\x6b" 19741 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 19770 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 19773 .key = "\x77\x6b\xef\xf2\x85\x1d\xb0\x6f" 19780 .input = "\x14\x5a\xd0\x1d\xbf\x82\x4e\xc7" 19796 "\x55\x30\x83\x1d\x93\x44\xaf\x1c", 19801 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 19869 "\x36\x7f\x1d\x57\xa4\xe7\x45\x5a", 21554 "\x18\x19\x1a\x1b\x1c\x1d\x1e", 21572 "\x1c\x1d\x1e\x1f", 21589 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 21609 "\x1c\x1d\x1e", 21631 "\xc5\x2e\xe8\x1d\x7d\x77\xc0\x8a", 21643 "\x2f\x07\x1d\x7c\xa4\xa5\xeb\xd9" 21681 .result = "\xab\x6f\xe1\x69\x1d\x19\x99\xa8" 21746 "\x66\x88\x1d\x4f\x9a\xda\xe0\x1e" 21766 "\x1d\xdc\x24\xae\x19\x2f\x98\x4c", 21792 .result = "\xb0\x88\x5a\x33\xaa\xe5\xc7\x1d" 21807 .assoc = "\xd4\xdb\x30\x1d\x03\xfe\xfd\x5f" 21843 "\x18\x19\x1a\x1b\x1c\x1d\x1e", 21861 "\x1c\x1d\x1e\x1f", 21879 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 21898 "\x1c\x1d\x1e", 21911 "\xc5\x2e\xe8\x1d\x7d\x77\xc0\x8a", 21932 "\x2f\x07\x1d\x7c\xa4\xa5\xeb\xd9" 22007 .assoc = "\x49\x5c\x50\x1f\x1d\x94\xcc\x81" 22084 "\x1d\xdd\x5a\xd9\xe4\xdb\x9c\x9c" 22115 "\xbc\xa8\xa3\xbd\x83\x7c\x1d\x2a", 22131 .assoc = "\x8f\x86\x6c\x4d\x1d\xc5\x39\x88" 23510 "\x49\xe6\x17\xd9\x1d\x36\x10\x94" 23607 "\x49\xe6\x17\xd9\x1d\x36\x10\x94" 23735 "\x49\xe6\x17\xd9\x1d\x36\x10\x94" 23788 "\x49\xe6\x17\xd9\x1d\x36\x10\x94" 23889 "\xd7\x1d\x4a\xfb\xb0\xe9\x22\xf9", 23903 "\xd7\x1d\x4a\xfb\xb0\xe9\x22\xfa", 23917 "\xd7\x1d\x4a\xfb\xb0\xe9\x22\xfb", 23931 "\xd7\x1d\x4a\xfb\xb0\xe9\x22\xfc", 23945 "\xd7\x1d\x4a\xfb\xb0\xe9\x22\xfd", 23985 "\x3f\x29\x2d\xec\xd3\x66\x51\x3f\x1d\x8d\x5b\x4e", 23989 "\x73\xd5\x22\xa9\x29\x63\x3a\x1d\xe5\x5d\x5e\x4f" 24046 "\xa9\xd0\x1d\x59\x02\xc4\xff\x70", 24071 "\xf6\x13\x05\xcb\x83\x60\x16\x42\x49\x1d\xc6\x25" 24072 "\x3b\x8c\x31\xa3\xbe\x8b\xbd\x1c\xe2\xec\x1d\xde" 24109 "\xa7\x09\xa1\x53\x64\x63\xa2\xc5\x1d\x84\x88\x65" 24114 "\xba\xa9\xfa\x49\xee\x1d\xdc\xfb\x50\xf6\x51\x9f" 24150 "\xc1\x1d\x45\x24\xc9\x07\x1b\xd3\x09\x60\x15\xfc" 24257 "\x7b\xa1\x91\x5b\x3c\x04\xc4\x1b\x1d\x19\x2f\x1a" 24267 "\x6c\x34\x7f\x7b\x1d\x0d\x63\x5e\x48\x9c\x69\xe6" 24399 "\x23\x6d\xad\x1d", 24435 "\x1f\xe8\xab\x1d\xa4\x66\x24\xed\x64\x15\xe5\x1c" 24449 "\x16\xfc\x42\xd2\x2d\xd5\x6f\x56\xcc\x1d\x30\xff" 24458 "\x81\x42\x2f\xf4\xdb\x0b\x23\xf8\x73\x27\xb8\x1d" 24481 "\x83\x9f\xf7\x88\xda\x84\xbf\x44\x28\xd9\x1d\xaa", 24506 "\x69\xed\x82\xa9\xc5\x7b\xbf\xe5\x1d\x2f\xcb\x7a" 24508 "\x33\x74\xba\xf1\x30\xdf\x8e\xdf\x87\x1d\x87\xbc" 24534 "\x74\xa6\xe0\x08\xf9\x27\xee\x1d\x6e\x3c\x28\x20" 24547 "\x60\x1d\xc6\x9f\xc9\x02\x94\x08\x05\xec\x0c\xa8", 24558 "\x96\x1d\xf8\x68\x03\x48\x2c\xb3\x7e\xd6\xd5\xc0" 24581 "\xef\xc8\xfe\x28\xa5\x1c\x9d\x42\x8e\x6d\x37\x1d" 24588 "\x51\x72\x89\xaf\xe4\x44\xa0\xfe\x5e\xd1\xa4\x1d" 24593 "\x1d\x74\x49\xfe\x75\x06\x26\x82\xe8\x9c\x57\x14" 24640 "\xde\x6b\xb1\x1d\x80\xbd\x87\x1a\x9a\xcd\x35\xc7" 24691 "\x21\x1d\x78\xa0\xb9\x38\x9a\x74\xe5\xbc\xcf\xec" 24701 "\xb4\xf0\x7e\x1d", 24739 "\x43\x2c\x71\x8b\xa2\x55\xd2\x0f\x1d\x7f\xe3\xe1" 24786 "\xf9\x01\xf8\x16\x7a\x1d\xff\xde\x8e\x3c\x83\xe2" 27187 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 27488 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 29183 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 29255 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 29280 "\x62\xdd\x78\x81\xea\x1d\xef\x04" 29281 "\x1d\x07\xc1\x67\xc8\xd6\x77\xa1" 29329 "\x2b\xa3\x95\xa6\xee\xd8\x74\x1d" 29335 "\xb2\x1a\xd8\x4c\xbd\x1d\x10\xe9" 29436 .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d" 29468 "\x62\xdd\x78\x81\xea\x1d\xef\x04" 29469 "\x1d\x07\xc1\x67\xc8\xd6\x77\xa1" 29517 "\x2b\xa3\x95\xa6\xee\xd8\x74\x1d" 29523 "\xb2\x1a\xd8\x4c\xbd\x1d\x10\xe9" 29573 "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a" 29630 .result = "\xc2\xb9\xdc\x44\x1d\xdf\xf2\x86" 29664 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 29696 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 29739 "\xdc\x8a\xdf\xc3\x1d\x1b\x41\x04" 29742 "\x1d\x16\x8a\x52\xbc\xa6\xbc\xa4" 29762 "\x43\xc1\xd4\xfc\xe4\x79\xc9\x1d" 29806 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 29838 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 29926 "\xf2\x7a\x1d\xf2\xaf\xa9\x48\x89" 29968 .input = "\xc2\xb9\xdc\x44\x1d\xdf\xf2\x86" 30017 "\xdc\x8a\xdf\xc3\x1d\x1b\x41\x04" 30020 "\x1d\x16\x8a\x52\xbc\xa6\xbc\xa4" 30040 "\x43\xc1\xd4\xfc\xe4\x79\xc9\x1d" 30072 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 30104 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 30204 "\xf2\x7a\x1d\xf2\xaf\xa9\x48\x89" 30214 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 30246 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 30319 "\xcf\xa5\x09\xb1\x1d\x42\x2b\xe7", 30361 "\xcf\xa5\x09\xb1\x1d\x42\x2b\xe7", 30503 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f", 30511 "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f" 30551 "\x08\x0b\x0e\x11\x14\x17\x1a\x1d" 30579 "\x18\x1d\x22\x27\x2c\x31\x36\x3b" 30627 "\x08\x0f\x16\x1d\x24\x2b\x32\x39" 30650 "\xf0\xf9\x02\x0b\x14\x1d\x26\x2f" 30682 "\xd0\xdb\xe6\xf1\xfc\x07\x12\x1d" 30710 "\x10\x1d\x2a\x37\x44\x51\x5e\x6b" 30734 "\xf0\xff\x0e\x1d\x2c\x3b\x4a\x59" 30773 "\xc8\xd9\xea\xfb\x0c\x1d\x2e\x3f" 30797 "\x98\xab\xbe\xd1\xe4\xf7\x0a\x1d" 30857 "\x08\x1d\x32\x47\x5c\x71\x86\x9b" 30889 "\xd8\xef\x06\x1d\x34\x4b\x62\x79" 30912 "\xa0\xb9\xd2\xeb\x04\x1d\x36\x4f" 30928 "\x60\x7b\x96\xb1\xcc\xe7\x02\x1d" 30956 "\x00\x1d\x3a\x57\x74\x91\xae\xcb" 30996 "\xc0\xdf\xfe\x1d\x3c\x5b\x7a\x99" 31044 "\xaf\xf6\x7d\x59\xb2\x44\x05\x1d" 31056 "\xfe\x2d\xc6\xc2\x94\x8c\x12\x1d" 31104 "\x1d\x57\x61\x9c\xd9\x4e\x54\x99" 31140 "\x9b\x1d\x72\x24\xda\xb7\x39\xbe" 31166 "\xac\x26\x80\x14\x1d\xc8\x3a\x35" 31261 "\x5d\x1d\x3f\x56\xf7\x2f\xbb\x90" 31280 "\x1d\xa7\x94\x18\x23\x50\x2c\xca" 31297 "\x1d\x55\x42\xe5\x49\xb0\xd0\x46" 31363 "\x0f\x3d\x83\x8c\xf1\x1d\x5b\x96" 31430 "\x1d\xa6\x32\x6a\x34\xe3\x55\xf8" 31441 "\x1d\xb3\xab\x3c\xb6\x3a\x13\x03" 31489 "\x85\xcf\xfe\x59\x20\xd4\x05\x1d" 31499 "\x75\x24\x6c\x54\xa7\x0e\x4d\x1d" 31629 "\x8c\xff\x2c\x1d\x4b\x79\x55\xec" 31670 "\x7a\xc6\x1d\xd2\x9c\x6f\x21\xba" 31775 "\xc6\x9c\x96\x9a\x12\x35\x95\x1d" 31798 "\xa3\x1d\x51\x41\xab\xce\xcb\xf6" 31887 "\xe8\x1d\x37\x96\x8a\xe3\x40\x35" 31896 "\xa1\x1d\x41\xe5\x08\xc1\x1c\x11" 31917 "\xc8\x43\xdc\xf8\x1d\x62\x5e\x5b" 31926 "\x84\x9b\x8c\xce\x1d\x6b\x93\x21" 31944 "\xa2\xdb\x29\x1d\xae\xb2\xc4\xfb" 31968 "\x90\x27\xbd\x5b\x1d\xb9\x21\x02" 32316 "\xd9\x4e\xe8\x7a\x76\x1d\x02\x98" 32339 "\xd9\x4e\xe8\x7a\x76\x1d\x02\x98" 32445 "\xd9\x4e\xe8\x7a\x76\x1d\x02\x98" 32470 "\xd9\x4e\xe8\x7a\x76\x1d\x02\x98" 32644 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 32716 .key = "\xf3\x4a\x1d\x5d", 32765 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 32828 "\x86\x1d\x91\x28\xbf\x33\xca\x61" 32837 "\x42\xd9\x4d\xe4\x7b\x12\x86\x1d" 32847 "\x70\x07\x7b\x12\xa9\x1d\xb4\x4b" 32896 "\xe4\x58\xef\x86\x1d\x91\x28\xbf" 32906 "\x12\x86\x1d\xb4\x28\xbf\x56\xed" 32916 "\x1d\xb4\x4b\xe2\x56\xed\x84\x1b" 32964 "\x1f\xb6\x4d\xe4\x58\xef\x86\x1d" 32974 "\x4d\xe4\x7b\x12\x86\x1d\xb4\x28" 32984 "\x7b\x12\xa9\x1d\xb4\x4b\xe2\x56" 33033 "\xef\x86\x1d\x91\x28\xbf\x33\xca" 33043 "\x1d\xb4\x28\xbf\x56\xed\x61\xf8" 33052 "\xd9\x70\x07\x7b\x12\xa9\x1d\xb4" 33082 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 33154 .key = "\xf3\x4a\x1d\x5d", 33203 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 33266 "\x86\x1d\x91\x28\xbf\x33\xca\x61" 33275 "\x42\xd9\x4d\xe4\x7b\x12\x86\x1d" 33285 "\x70\x07\x7b\x12\xa9\x1d\xb4\x4b" 33334 "\xe4\x58\xef\x86\x1d\x91\x28\xbf" 33344 "\x12\x86\x1d\xb4\x28\xbf\x56\xed" 33354 "\x1d\xb4\x4b\xe2\x56\xed\x84\x1b" 33402 "\x1f\xb6\x4d\xe4\x58\xef\x86\x1d" 33412 "\x4d\xe4\x7b\x12\x86\x1d\xb4\x28" 33422 "\x7b\x12\xa9\x1d\xb4\x4b\xe2\x56" 33471 "\xef\x86\x1d\x91\x28\xbf\x33\xca" 33481 "\x1d\xb4\x28\xbf\x56\xed\x61\xf8" 33490 "\xd9\x70\x07\x7b\x12\xa9\x1d\xb4" 33520 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 33531 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 33542 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20" 33553 "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
|
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_5_0_enum.h | 161 DBG_CLIENT_BLKID_sx20 = 0x1d, 321 DBG_BLOCK_ID_UVDM = 0x1d, 555 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 673 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 883 FMT_24_8_FLOAT = 0x1d, 967 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
|
H A D | bif_5_1_enum.h | 57 DBG_BLOCK_ID_VGT1 = 0x1d, 314 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 436 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 498 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 753 FMT_24_8_FLOAT = 0x1d, 837 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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/linux-4.4.14/drivers/media/pci/solo6x10/ |
H A D | solo6x10-jpeg.h | 115 0x0f, 0x14, 0x1d, 0x1a, 0x1f, 0x1e, 0x1d, 0x1a, 134 0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33,
|
/linux-4.4.14/drivers/staging/speakup/ |
H A D | spk_priv_keyinfo.h | 58 #define SAY_FROM_TOP 0x1d
|
/linux-4.4.14/drivers/scsi/bnx2i/ |
H A D | 57xx_iscsi_constants.h | 95 #define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_BURST_LEN (0x1d)
|
/linux-4.4.14/drivers/macintosh/ |
H A D | windfarm_mpu.h | 41 u8 reserved2[3]; /* 0x1d - */
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/linux-4.4.14/drivers/gpu/drm/tegra/ |
H A D | dsi.h | 59 #define DSI_INIT_SEQ_DATA_2 0x1d
|
H A D | hdmi.h | 68 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d 275 #define DRIVE_CURRENT_12_375_mA 0x1d 339 #define DRIVE_CURRENT_11_600_mA_T114 0x1d 519 #define PEAK_CURRENT_5_800_mA 0x1d
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/linux-4.4.14/drivers/media/firewire/ |
H A D | firedtv-rc.c | 100 [0x1d] = KEY_PLAYPAUSE,
|
/linux-4.4.14/drivers/net/wireless/realtek/rtl818x/rtl8187/ |
H A D | rtl8225.c | 227 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 258 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 267 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 429 rtl8225_write_phy_ofdm(dev, 0x1d, rtl8225_gain[2 * 4 + 3]); rtl8225_rf_init() 476 rtl8225_write_phy_ofdm(dev, 0x1d, rtl8225_gain[2 * 4 + 3]); rtl8225_rf_init() 485 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 528 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 781 rtl8225_write_phy_ofdm(dev, 0x1d, 0xc5); rtl8225z2_rf_init() 795 rtl8225_write_phy_ofdm(dev, 0x1d, rtl8225z2_gain_bg[4 * 3 + 2]); rtl8225z2_rf_init()
|
/linux-4.4.14/drivers/net/phy/ |
H A D | national.c | 45 #define NS_EXP_MEM_DATA 0x1d
|
H A D | realtek.c | 28 #define RTL8211F_INSR 0x1d
|
H A D | marvell.c | 214 err = phy_write(phydev, 0x1d, 0x1f); marvell_config_aneg() 222 err = phy_write(phydev, 0x1d, 0x5); marvell_config_aneg() 699 err = phy_write(phydev, 0x1d, 0x001b); m88e1145_config_init() 707 err = phy_write(phydev, 0x1d, 0x0016); m88e1145_config_init() 727 err = phy_write(phydev, 0x1d, 0x0012); m88e1145_config_init() 743 err = phy_write(phydev, 0x1d, 0x3); m88e1145_config_init()
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/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_3_0_1_enum.h | 83 IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, 125 SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x1d, 362 SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, 453 DBG_BLOCK_ID_VGT1 = 0x1d, 710 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 832 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 894 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 1149 FMT_24_8_FLOAT = 0x1d, 1233 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
|
H A D | oss_2_4_enum.h | 83 IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, 183 SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, 346 DBG_CLIENT_BLKID_smu_2 = 0x1d, 486 DBG_BLOCK_ID_UVDM = 0x1d, 720 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 838 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 1048 FMT_24_8_FLOAT = 0x1d, 1132 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
|
H A D | oss_3_0_enum.h | 83 IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, 297 SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, 460 DBG_CLIENT_BLKID_sx20 = 0x1d, 620 DBG_BLOCK_ID_UVDM = 0x1d, 854 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 972 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 1182 FMT_24_8_FLOAT = 0x1d, 1266 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
|
/linux-4.4.14/drivers/gpu/drm/msm/dsi/phy/ |
H A D | dsi_phy_20nm.c | 60 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); dsi_20nm_phy_regulator_ctrl()
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/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/iio/ |
H A D | qcom,spmi-vadc.h | 48 #define VADC_P_MUX14_1_1 0x1d
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/linux-4.4.14/include/dt-bindings/iio/ |
H A D | qcom,spmi-vadc.h | 48 #define VADC_P_MUX14_1_1 0x1d
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/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/iio/ |
H A D | qcom,spmi-vadc.h | 48 #define VADC_P_MUX14_1_1 0x1d
|
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/iio/ |
H A D | qcom,spmi-vadc.h | 48 #define VADC_P_MUX14_1_1 0x1d
|
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/iio/ |
H A D | qcom,spmi-vadc.h | 48 #define VADC_P_MUX14_1_1 0x1d
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/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/iio/ |
H A D | qcom,spmi-vadc.h | 48 #define VADC_P_MUX14_1_1 0x1d
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/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/iio/ |
H A D | qcom,spmi-vadc.h | 48 #define VADC_P_MUX14_1_1 0x1d
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/linux-4.4.14/drivers/scsi/ |
H A D | aha152x.h | 44 #define STACK (HOSTIOPORT1+0x1d) /* stack */ 53 #define O_STACK 0x1d /* stack */
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/linux-4.4.14/drivers/net/ieee802154/ |
H A D | at86rf230.h | 133 #define RG_VERSION_NUM (0x1d) 134 #define SR_VERSION_NUM 0x1d, 0xff, 0
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/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/ |
H A D | iop_mpu_macros.h | 53 #define MPU_I13 (0x1d) 77 #define MPU_P29 (0x1d)
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/linux-4.4.14/include/sound/ |
H A D | cs4231-regs.h | 73 #define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ 74 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
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/linux-4.4.14/include/linux/mfd/ |
H A D | max8997-private.h | 59 MAX8997_REG_BUCK1DVS5 = 0x1d, 304 MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d,
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H A D | max8925.h | 98 #define MAX8925_RTC_IRQ_MASK (0x1d)
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/linux-4.4.14/drivers/media/i2c/ |
H A D | saa7127.c | 183 { SAA7127_REG_BURST_END, 0x1d }, 205 { SAA7127_REG_BURST_END, 0x1d }, 227 { SAA7127_REG_BURST_END, 0x1d }, 749 0x1d after a reset and not expected to ever change. */ saa7127_probe() 751 (saa7127_read(sd, 0x29) & 0x3f) != 0x1d) { saa7127_probe()
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H A D | ths8200_regs.h | 51 #define THS8200_DTG1_Y_SYNC1_LSB 0x1d
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H A D | tvp5150_reg.h | 43 #define TVP5150_INT_ENABLE_REG_B 0x1d /* Interrupt enable register B */
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H A D | tvp7002_reg.h | 87 #define TVP7002_FINE_OFF_LSBS 0x1d
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H A D | saa7185.c | 133 0x49, 0x1d, /* OVLU2=29 cyan */ 210 0x61, 0x1d, /* FISE=1, PAL=0, SCBW=1, RTCE=1,
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/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/dce/ |
H A D | dce_10_0_enum.h | 447 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d, 736 DBG_CLIENT_BLKID_sx20 = 0x1d, 896 DBG_BLOCK_ID_UVDM = 0x1d, 1130 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 1248 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 1458 FMT_24_8_FLOAT = 0x1d, 1542 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
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/linux-4.4.14/drivers/staging/media/mn88473/ |
H A D | mn88473.c | 136 ret = regmap_write(dev->regmap[0], 0x1d, 0xb0); mn88473_set_frontend() 149 ret = regmap_write(dev->regmap[1], 0x14, 0x1d); mn88473_set_frontend() 153 ret = regmap_write(dev->regmap[2], 0x08, 0x1d); mn88473_set_frontend()
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/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | gt215.c | 167 return read_clk(clk, 0x1d, false); gt215_clk_read() 296 ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); calc_host() 426 prog_clk(clk, 0x1d, nv_clk_src_host); prog_host()
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/linux-4.4.14/drivers/staging/gdm72xx/ |
H A D | hci.h | 140 #define T_FW_REVISION (0x1d | (4 << 16))
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/linux-4.4.14/drivers/video/backlight/ |
H A D | bd6107.c | 58 #define BD6107_STATE1 0x1d
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H A D | ams369fg06.c | 112 0x1d, 0xa0, 130 0x00, 0x3f, 0x28, 0x27, 0x25, 0x1d, 0x53,
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/linux-4.4.14/drivers/media/i2c/soc_camera/ |
H A D | ov9640.h | 44 #define OV9640_MIDL 0x1d
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/linux-4.4.14/drivers/media/pci/mantis/ |
H A D | mantis_vp1033.c | 63 0x1d, 0x27,
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/linux-4.4.14/drivers/input/touchscreen/ |
H A D | touchit213.c | 65 * and y values from 0x1d to 0x7e9, so the actual measurement is
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/linux-4.4.14/drivers/media/platform/sti/c8sectpfe/ |
H A D | c8sectpfe-dvb.c | 93 .demod_address = 0x1d,
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/linux-4.4.14/drivers/media/usb/gspca/stv06xx/ |
H A D | stv06xx_pb0100.h | 69 #define PB_R29 0x1d /* Reserved */
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/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/ |
H A D | dm.c | 87 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, 90 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, 123 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, 126 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
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/linux-4.4.14/drivers/net/usb/ |
H A D | sr9800.h | 83 #define SR_CMD_WRITE_MONITOR_MODE 0x1d
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/linux-4.4.14/drivers/ata/ |
H A D | pata_ninja32.c | 99 iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */ ninja32_program()
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/linux-4.4.14/drivers/block/paride/ |
H A D | friq.c | 240 CMD(0x1d); CMD(0x1e); friq_release_proto()
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/linux-4.4.14/arch/sparc/include/uapi/asm/ |
H A D | traps.h | 57 #define SP_TRAP_IRQ13 0x1d /* IRQ level 13 */
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/linux-4.4.14/arch/mips/ath25/ |
H A D | board.c | 171 mac_addr = &radio_data[0x1d * 2]; ath25_find_config()
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/linux-4.4.14/arch/ia64/include/asm/ |
H A D | hw_irq.h | 45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
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/linux-4.4.14/tools/firewire/ |
H A D | decode-fcp.c | 36 [0x0d] = "(reserved 0x0d)", [0x1d] = "all subunit types",
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/linux-4.4.14/drivers/media/pci/pt1/ |
H A D | va1j5jf8007t.c | 452 {0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, 459 {0x03, 0x90}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, {0x22, 0x83},
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/linux-4.4.14/drivers/media/usb/em28xx/ |
H A D | em28xx-camera.c | 212 /* Read manufacturer ID from registers 0x1c-0x1d (BE) */ em28xx_probe_sensor_omnivision() 222 reg = 0x1d; em28xx_probe_sensor_omnivision()
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/linux-4.4.14/arch/sparc/kernel/ |
H A D | ttable_64.S | 28 tl0_resv018: BTRAP(0x18) BTRAP(0x19) BTRAP(0x1a) BTRAP(0x1b) BTRAP(0x1c) BTRAP(0x1d) 193 tl1_resv01a: BTRAPTL1(0x1a) BTRAPTL1(0x1b) BTRAPTL1(0x1c) BTRAPTL1(0x1d)
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/linux-4.4.14/arch/arm/boot/dts/ |
H A D | imx1-pinfunc.h | 102 #define MX1_PAD_A21__A21 0x1d 0x004 103 #define MX1_PAD_A21__GPIO1_29 0x1d 0x032
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/linux-4.4.14/arch/powerpc/include/asm/ |
H A D | mpc52xx.h | 126 u8 reserved2[3]; /* GPIO + 0x1d */ 217 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
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