Searched refs:reg1 (Results 1 - 119 of 119) sorted by relevance

/linux-4.4.14/arch/nios2/include/asm/
H A Dasm-macros.h25 * ANDs reg2 with mask and places the result in reg1.
27 * You cannnot use the same register for reg1 & reg2.
30 .macro ANDI32 reg1, reg2, mask
33 movhi \reg1, %hi(\mask)
34 movui \reg1, %lo(\mask) variable
35 and \reg1, \reg1, \reg2 variable
37 andi \reg1, \reg2, %lo(\mask)
40 andhi \reg1, \reg2, %hi(\mask)
45 * ORs reg2 with mask and places the result in reg1.
47 * It is safe to use the same register for reg1 & reg2.
50 .macro ORI32 reg1, reg2, mask
53 orhi \reg1, \reg2, %hi(\mask)
54 ori \reg1, \reg2, %lo(\mask) variable
56 ori \reg1, \reg2, %lo(\mask)
59 orhi \reg1, \reg2, %hi(\mask)
64 * XORs reg2 with mask and places the result in reg1.
66 * It is safe to use the same register for reg1 & reg2.
69 .macro XORI32 reg1, reg2, mask
72 xorhi \reg1, \reg2, %hi(\mask)
73 xori \reg1, \reg1, %lo(\mask) variable
75 xori \reg1, \reg2, %lo(\mask)
78 xorhi \reg1, \reg2, %hi(\mask)
86 * It is safe to use the same register for reg1 & reg2.
89 .macro BT reg1, reg2, bit
94 andi \reg1, \reg2, (1 << \bit)
96 andhi \reg1, \reg2, (1 << (\bit - 16))
103 * bit is zero. The result of the bit test is stored in reg1.
105 * It is safe to use the same register for reg1 & reg2.
108 .macro BTBZ reg1, reg2, bit, label
109 BT \reg1, \reg2, \bit
110 beq \reg1, r0, \label
115 * bit is non-zero. The result of the bit test is stored in reg1.
117 * It is safe to use the same register for reg1 & reg2.
120 .macro BTBNZ reg1, reg2, bit, label
121 BT \reg1, \reg2, \bit
122 bne \reg1, r0, \label
127 * The result of the bit test is stored in reg1.
129 * It is NOT safe to use the same register for reg1 & reg2.
132 .macro BTC reg1, reg2, bit
137 andi \reg1, \reg2, (1 << \bit)
140 andhi \reg1, \reg2, (1 << (\bit - 16))
148 * The result of the bit test is stored in reg1.
150 * It is NOT safe to use the same register for reg1 & reg2.
153 .macro BTS reg1, reg2, bit
158 andi \reg1, \reg2, (1 << \bit)
161 andhi \reg1, \reg2, (1 << (\bit - 16))
169 * The result of the bit test is stored in reg1.
171 * It is NOT safe to use the same register for reg1 & reg2.
174 .macro BTR reg1, reg2, bit
179 andi \reg1, \reg2, (1 << \bit)
182 andhi \reg1, \reg2, (1 << (\bit - 16))
190 * The result of the bit test is stored in reg1. If the
193 * It is NOT safe to use the same register for reg1 & reg2.
196 .macro BTCBZ reg1, reg2, bit, label
197 BTC \reg1, \reg2, \bit
198 beq \reg1, r0, \label
203 * The result of the bit test is stored in reg1. If the
206 * It is NOT safe to use the same register for reg1 & reg2.
209 .macro BTCBNZ reg1, reg2, bit, label
210 BTC \reg1, \reg2, \bit
211 bne \reg1, r0, \label
216 * The result of the bit test is stored in reg1. If the
219 * It is NOT safe to use the same register for reg1 & reg2.
222 .macro BTSBZ reg1, reg2, bit, label
223 BTS \reg1, \reg2, \bit
224 beq \reg1, r0, \label
229 * The result of the bit test is stored in reg1. If the
232 * It is NOT safe to use the same register for reg1 & reg2.
235 .macro BTSBNZ reg1, reg2, bit, label
236 BTS \reg1, \reg2, \bit
237 bne \reg1, r0, \label
242 * The result of the bit test is stored in reg1. If the
245 * It is NOT safe to use the same register for reg1 & reg2.
248 .macro BTRBZ reg1, reg2, bit, label
249 BTR \reg1, \reg2, \bit
250 bne \reg1, r0, \label
255 * The result of the bit test is stored in reg1. If the
258 * It is NOT safe to use the same register for reg1 & reg2.
261 .macro BTRBNZ reg1, reg2, bit, label
262 BTR \reg1, \reg2, \bit
263 bne \reg1, r0, \label
267 * Tests the bits in mask against reg2 stores the result in reg1.
270 * It is safe to use the same register for reg1 & reg2.
273 .macro TSTBZ reg1, reg2, mask, label
274 ANDI32 \reg1, \reg2, \mask
275 beq \reg1, r0, \label
279 * Tests the bits in mask against reg2 stores the result in reg1.
282 * It is safe to use the same register for reg1 & reg2.
285 .macro TSTBNZ reg1, reg2, mask, label
286 ANDI32 \reg1, \reg2, \mask
287 bne \reg1, r0, \label
/linux-4.4.14/arch/m32r/include/asm/
H A Ddcache_clear.h13 #define DCACHE_CLEAR(reg0, reg1, addr) \
14 "seth "reg1", #high(dcache_dummy); \n\t" \
15 "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
16 "lock "reg0", @"reg1"; \n\t" \
21 "unlock "reg0", @"reg1"; \n\t"
26 #define DCACHE_CLEAR(reg0, reg1, addr)
/linux-4.4.14/arch/arm/lib/
H A Dcsumpartialcopy.S28 .macro load1b, reg1
29 ldrb \reg1, [r0], #1
32 .macro load2b, reg1, reg2
33 ldrb \reg1, [r0], #1
37 .macro load1l, reg1
38 ldr \reg1, [r0], #4
41 .macro load2l, reg1, reg2
42 ldr \reg1, [r0], #4
46 .macro load4l, reg1, reg2, reg3, reg4
47 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dmemcpy.S24 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
28 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
29 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
40 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
41 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
48 .macro enter reg1 reg2
49 stmdb sp!, {r0, \reg1, \reg2}
52 .macro usave reg1 reg2
53 UNWIND( .save {r0, \reg1, \reg2} )
56 .macro exit reg1 reg2
57 ldmfd sp!, {r0, \reg1, \reg2}
H A Dcopy_from_user.S48 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
49 ldr1w \ptr, \reg1, \abort
55 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
56 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
68 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
69 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
76 .macro enter reg1 reg2
78 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
81 .macro usave reg1 reg2
82 UNWIND( .save {r0, r2, r3, \reg1, \reg2} )
85 .macro exit reg1 reg2
87 ldmfd sp!, {r0, \reg1, \reg2}
H A Dcopy_to_user.S48 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
49 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
52 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
53 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
79 .macro enter reg1 reg2
81 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
84 .macro usave reg1 reg2
85 UNWIND( .save {r0, r2, r3, \reg1, \reg2} )
88 .macro exit reg1 reg2
90 ldmfd sp!, {r0, \reg1, \reg2}
H A Dcsumpartialcopyuser.S42 .macro load1b, reg1
43 ldrusr \reg1, r0, 1
46 .macro load2b, reg1, reg2
47 ldrusr \reg1, r0, 1
51 .macro load1l, reg1
52 ldrusr \reg1, r0, 4
55 .macro load2l, reg1, reg2
56 ldrusr \reg1, r0, 4
60 .macro load4l, reg1, reg2, reg3, reg4
61 ldrusr \reg1, r0, 4
/linux-4.4.14/drivers/s390/cio/
H A Dioasm.h30 register struct subchannel_id reg1 asm ("1") = schid; stsch_err()
40 : "d" (reg1), "a" (addr) stsch_err()
47 register struct subchannel_id reg1 asm ("1") = schid; msch()
55 : "d" (reg1), "a" (addr), "m" (*addr) msch()
62 register struct subchannel_id reg1 asm ("1") = schid; msch_err()
72 : "d" (reg1), "a" (addr), "m" (*addr) msch_err()
79 register struct subchannel_id reg1 asm ("1") = schid; tsch()
87 : "d" (reg1), "a" (addr) tsch()
94 register struct subchannel_id reg1 asm("1") = schid; ssch()
104 : "d" (reg1), "a" (addr), "m" (*addr) ssch()
111 register struct subchannel_id reg1 asm("1") = schid; csch()
119 : "d" (reg1) csch()
155 register struct chp_id reg1 asm ("1") = chpid; rchp()
163 : "=d" (ccode) : "d" (reg1) : "cc"); rchp()
H A Dio_sch.h174 register struct subchannel_id reg1 asm("1") = schid; rsch()
182 : "d" (reg1) rsch()
189 register struct subchannel_id reg1 asm("1") = schid; hsch()
197 : "d" (reg1) hsch()
204 register struct subchannel_id reg1 asm("1") = schid; xsch()
212 : "d" (reg1) xsch()
/linux-4.4.14/arch/arm/probes/kprobes/
H A Dtest-core.h241 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \
242 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
243 TEST_ARG_REG(reg1, val1) \
246 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
249 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
250 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
251 TEST_ARG_REG(reg1, val1) \
255 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
258 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \
259 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
260 TEST_ARG_REG(reg1, val1) \
265 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
268 #define TEST_P(code1, reg1, val1, code2) \
269 TESTCASE_START(code1 #reg1 code2) \
270 TEST_ARG_PTR(reg1, val1) \
272 TEST_INSTRUCTION(code1 #reg1 code2) \
275 #define TEST_PR(code1, reg1, val1, code2, reg2, val2, code3) \
276 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
277 TEST_ARG_PTR(reg1, val1) \
280 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
283 #define TEST_RP(code1, reg1, val1, code2, reg2, val2, code3) \
284 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
285 TEST_ARG_REG(reg1, val1) \
288 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
291 #define TEST_PRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
292 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
293 TEST_ARG_PTR(reg1, val1) \
297 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
300 #define TEST_RPR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
301 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
302 TEST_ARG_REG(reg1, val1) \
306 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
309 #define TEST_RRP(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
310 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
311 TEST_ARG_REG(reg1, val1) \
315 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
318 #define TEST_BF_P(code1, reg1, val1, code2) \
319 TESTCASE_START(code1 #reg1 code2) \
320 TEST_ARG_PTR(reg1, val1) \
322 TEST_BRANCH_F(code1 #reg1 code2) \
351 #define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \
352 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
353 TEST_ARG_REG(reg1, val1) \
356 TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3) \
395 #define TEST_RRX(code1, reg1, val1, code2, reg2, val2, code3, codex) \
396 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
397 TEST_ARG_REG(reg1, val1) \
400 TEST_INSTRUCTION(code1 __stringify(reg1) code2 __stringify(reg2) code3) \
/linux-4.4.14/arch/x86/kernel/cpu/
H A Dperf_event_intel_uncore_nhmex.c346 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_bbox_hw_config() local
361 reg1->reg = NHMEX_B0_MSR_MATCH; nhmex_bbox_hw_config()
363 reg1->reg = NHMEX_B1_MSR_MATCH; nhmex_bbox_hw_config()
364 reg1->idx = 0; nhmex_bbox_hw_config()
365 reg1->config = event->attr.config1; nhmex_bbox_hw_config()
373 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_bbox_msr_enable_event() local
376 if (reg1->idx != EXTRA_REG_NONE) { nhmex_bbox_msr_enable_event()
377 wrmsrl(reg1->reg, reg1->config); nhmex_bbox_msr_enable_event()
378 wrmsrl(reg1->reg + 1, reg2->config); nhmex_bbox_msr_enable_event()
437 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_sbox_hw_config() local
446 reg1->reg = NHMEX_S0_MSR_MM_CFG; nhmex_sbox_hw_config()
448 reg1->reg = NHMEX_S1_MSR_MM_CFG; nhmex_sbox_hw_config()
449 reg1->idx = 0; nhmex_sbox_hw_config()
450 reg1->config = event->attr.config1; nhmex_sbox_hw_config()
458 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_sbox_msr_enable_event() local
461 if (reg1->idx != EXTRA_REG_NONE) { nhmex_sbox_msr_enable_event()
462 wrmsrl(reg1->reg, 0); nhmex_sbox_msr_enable_event()
463 wrmsrl(reg1->reg + 1, reg1->config); nhmex_sbox_msr_enable_event()
464 wrmsrl(reg1->reg + 2, reg2->config); nhmex_sbox_msr_enable_event()
465 wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN); nhmex_sbox_msr_enable_event()
625 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_mbox_alter_er() local
626 u64 idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8); nhmex_mbox_alter_er()
627 u64 config = reg1->config; nhmex_mbox_alter_er()
645 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; nhmex_mbox_alter_er()
647 config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; nhmex_mbox_alter_er()
648 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; nhmex_mbox_alter_er()
655 reg1->config = config; nhmex_mbox_alter_er()
656 reg1->idx = ~0xff | new_idx; nhmex_mbox_alter_er()
664 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; nhmex_mbox_get_constraint() local
667 u64 config1 = reg1->config; nhmex_mbox_get_constraint()
669 idx[0] = __BITS_VALUE(reg1->idx, 0, 8); nhmex_mbox_get_constraint()
670 idx[1] = __BITS_VALUE(reg1->idx, 1, 8); nhmex_mbox_get_constraint()
673 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) nhmex_mbox_get_constraint()
698 if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) nhmex_mbox_get_constraint()
700 reg1->alloc |= alloc; nhmex_mbox_get_constraint()
714 BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff); nhmex_mbox_get_constraint()
718 if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) { nhmex_mbox_get_constraint()
733 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; nhmex_mbox_put_constraint() local
739 if (reg1->alloc & 0x1) nhmex_mbox_put_constraint()
740 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8)); nhmex_mbox_put_constraint()
741 if (reg1->alloc & 0x2) nhmex_mbox_put_constraint()
742 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8)); nhmex_mbox_put_constraint()
743 reg1->alloc = 0; nhmex_mbox_put_constraint()
761 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; nhmex_mbox_hw_config() local
787 reg1->idx &= ~(0xff << (reg_idx * 8)); nhmex_mbox_hw_config()
788 reg1->reg &= ~(0xffff << (reg_idx * 16)); nhmex_mbox_hw_config()
789 reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8); nhmex_mbox_hw_config()
790 reg1->reg |= msr << (reg_idx * 16); nhmex_mbox_hw_config()
791 reg1->config = event->attr.config1; nhmex_mbox_hw_config()
831 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_mbox_msr_enable_event() local
835 idx = __BITS_VALUE(reg1->idx, 0, 8); nhmex_mbox_msr_enable_event()
837 wrmsrl(__BITS_VALUE(reg1->reg, 0, 16), nhmex_mbox_msr_enable_event()
839 idx = __BITS_VALUE(reg1->idx, 1, 8); nhmex_mbox_msr_enable_event()
841 wrmsrl(__BITS_VALUE(reg1->reg, 1, 16), nhmex_mbox_msr_enable_event()
940 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_rbox_alter_er() local
943 if (reg1->idx % 2) { nhmex_rbox_alter_er()
944 reg1->idx--; nhmex_rbox_alter_er()
947 reg1->idx++; nhmex_rbox_alter_er()
952 switch (reg1->idx % 6) { nhmex_rbox_alter_er()
955 reg1->config >>= 8; nhmex_rbox_alter_er()
959 reg1->config <<= 8; nhmex_rbox_alter_er()
974 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_rbox_get_constraint() local
982 if (!uncore_box_is_fake(box) && reg1->alloc) nhmex_rbox_get_constraint()
985 idx = reg1->idx % 6; nhmex_rbox_get_constraint()
986 config1 = reg1->config; nhmex_rbox_get_constraint()
992 er_idx += (reg1->idx / 6) * 5; nhmex_rbox_get_constraint()
997 if (!atomic_read(&er->ref) || er->config == reg1->config) { nhmex_rbox_get_constraint()
999 er->config = reg1->config; nhmex_rbox_get_constraint()
1018 er->config1 == reg1->config && nhmex_rbox_get_constraint()
1022 er->config1 = reg1->config; nhmex_rbox_get_constraint()
1037 if (idx != reg1->idx % 6) { nhmex_rbox_get_constraint()
1046 if (idx != reg1->idx % 6) nhmex_rbox_get_constraint()
1048 reg1->alloc = 1; nhmex_rbox_get_constraint()
1058 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; nhmex_rbox_put_constraint() local
1061 if (uncore_box_is_fake(box) || !reg1->alloc) nhmex_rbox_put_constraint()
1064 idx = reg1->idx % 6; nhmex_rbox_put_constraint()
1068 er_idx += (reg1->idx / 6) * 5; nhmex_rbox_put_constraint()
1076 reg1->alloc = 0; nhmex_rbox_put_constraint()
1082 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; nhmex_rbox_hw_config() local
1091 reg1->idx = idx; nhmex_rbox_hw_config()
1092 reg1->config = event->attr.config1; nhmex_rbox_hw_config()
1107 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; nhmex_rbox_msr_enable_event() local
1111 idx = reg1->idx; nhmex_rbox_msr_enable_event()
1116 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config); nhmex_rbox_msr_enable_event()
1119 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config); nhmex_rbox_msr_enable_event()
1129 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config); nhmex_rbox_msr_enable_event()
1135 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config); nhmex_rbox_msr_enable_event()
H A Dperf_event_intel_uncore_snbep.c351 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; snbep_uncore_msr_enable_event() local
353 if (reg1->idx != EXTRA_REG_NONE) snbep_uncore_msr_enable_event()
354 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); snbep_uncore_msr_enable_event()
642 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; snbep_cbox_put_constraint() local
650 if (reg1->alloc & (0x1 << i)) snbep_cbox_put_constraint()
653 reg1->alloc = 0; snbep_cbox_put_constraint()
660 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; __snbep_cbox_get_constraint() local
666 if (reg1->idx == EXTRA_REG_NONE) __snbep_cbox_get_constraint()
671 if (!(reg1->idx & (0x1 << i))) __snbep_cbox_get_constraint()
673 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) __snbep_cbox_get_constraint()
678 !((reg1->config ^ er->config) & mask)) { __snbep_cbox_get_constraint()
681 er->config |= reg1->config & mask; __snbep_cbox_get_constraint()
692 reg1->alloc |= alloc; __snbep_cbox_get_constraint()
727 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; snbep_cbox_hw_config() local
738 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + snbep_cbox_hw_config()
740 reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx); snbep_cbox_hw_config()
741 reg1->idx = idx; snbep_cbox_hw_config()
772 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; snbep_pcu_alter_er() local
773 u64 config = reg1->config; snbep_pcu_alter_er()
775 if (new_idx > reg1->idx) snbep_pcu_alter_er()
776 config <<= 8 * (new_idx - reg1->idx); snbep_pcu_alter_er()
778 config >>= 8 * (reg1->idx - new_idx); snbep_pcu_alter_er()
781 hwc->config += new_idx - reg1->idx; snbep_pcu_alter_er()
782 reg1->config = config; snbep_pcu_alter_er()
783 reg1->idx = new_idx; snbep_pcu_alter_er()
791 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; snbep_pcu_get_constraint() local
794 int idx = reg1->idx; snbep_pcu_get_constraint()
795 u64 mask, config1 = reg1->config; snbep_pcu_get_constraint()
798 if (reg1->idx == EXTRA_REG_NONE || snbep_pcu_get_constraint()
799 (!uncore_box_is_fake(box) && reg1->alloc)) snbep_pcu_get_constraint()
815 if (idx != reg1->idx) { snbep_pcu_get_constraint()
823 if (idx != reg1->idx) snbep_pcu_get_constraint()
825 reg1->alloc = 1; snbep_pcu_get_constraint()
832 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; snbep_pcu_put_constraint() local
835 if (uncore_box_is_fake(box) || !reg1->alloc) snbep_pcu_put_constraint()
838 atomic_sub(1 << (reg1->idx * 8), &er->ref); snbep_pcu_put_constraint()
839 reg1->alloc = 0; snbep_pcu_put_constraint()
845 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; snbep_pcu_hw_config() local
849 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER; snbep_pcu_hw_config()
850 reg1->idx = ev_sel - 0xb; snbep_pcu_hw_config()
851 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); snbep_pcu_hw_config()
900 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; snbep_qpi_hw_config() local
904 reg1->idx = 0; snbep_qpi_hw_config()
905 reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0; snbep_qpi_hw_config()
906 reg1->config = event->attr.config1; snbep_qpi_hw_config()
917 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; snbep_qpi_enable_event() local
920 if (reg1->idx != EXTRA_REG_NONE) { snbep_qpi_enable_event()
924 pci_write_config_dword(filter_pdev, reg1->reg, snbep_qpi_enable_event()
925 (u32)reg1->config); snbep_qpi_enable_event()
926 pci_write_config_dword(filter_pdev, reg1->reg + 4, snbep_qpi_enable_event()
927 (u32)(reg1->config >> 32)); snbep_qpi_enable_event()
1397 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; ivbep_cbox_hw_config() local
1408 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + ivbep_cbox_hw_config()
1410 reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx); ivbep_cbox_hw_config()
1411 reg1->idx = idx; ivbep_cbox_hw_config()
1419 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; ivbep_cbox_enable_event() local
1421 if (reg1->idx != EXTRA_REG_NONE) { ivbep_cbox_enable_event()
1423 wrmsrl(reg1->reg, filter & 0xffffffff); ivbep_cbox_enable_event()
1424 wrmsrl(reg1->reg + 6, filter >> 32); ivbep_cbox_enable_event()
1750 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; hswep_ubox_hw_config() local
1751 reg1->reg = HSWEP_U_MSR_PMON_FILTER; hswep_ubox_hw_config()
1752 reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK; hswep_ubox_hw_config()
1753 reg1->idx = 0; hswep_ubox_hw_config()
1883 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; hswep_cbox_hw_config() local
1894 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + hswep_cbox_hw_config()
1896 reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx); hswep_cbox_hw_config()
1897 reg1->idx = idx; hswep_cbox_hw_config()
1906 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; hswep_cbox_enable_event() local
1908 if (reg1->idx != EXTRA_REG_NONE) { hswep_cbox_enable_event()
1910 wrmsrl(reg1->reg, filter & 0xffffffff); hswep_cbox_enable_event()
1911 wrmsrl(reg1->reg + 1, filter >> 32); hswep_cbox_enable_event()
2001 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; hswep_pcu_hw_config() local
2005 reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER; hswep_pcu_hw_config()
2006 reg1->idx = ev_sel - 0xb; hswep_pcu_hw_config()
2007 reg1->config = event->attr.config1 & (0xff << reg1->idx); hswep_pcu_hw_config()
H A Dperf_event_intel_uncore.c140 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; uncore_get_constraint() local
150 if (reg1->idx == EXTRA_REG_NONE || uncore_get_constraint()
151 (!uncore_box_is_fake(box) && reg1->alloc)) uncore_get_constraint()
154 er = &box->shared_regs[reg1->idx]; uncore_get_constraint()
157 (er->config1 == reg1->config && er->config2 == reg2->config)) { uncore_get_constraint()
159 er->config1 = reg1->config; uncore_get_constraint()
167 reg1->alloc = 1; uncore_get_constraint()
177 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; uncore_put_constraint() local
187 if (uncore_box_is_fake(box) || !reg1->alloc) uncore_put_constraint()
190 er = &box->shared_regs[reg1->idx]; uncore_put_constraint()
192 reg1->alloc = 0; uncore_put_constraint()
/linux-4.4.14/sound/pci/ice1712/
H A Dwm8776.c151 .reg1 = WM8776_REG_DACLVOL,
161 .reg1 = WM8776_REG_DACCTRL1,
170 .reg1 = WM8776_REG_DACCTRL1,
177 .reg1 = WM8776_REG_HPLVOL,
188 .reg1 = WM8776_REG_PWRDOWN,
195 .reg1 = WM8776_REG_HPLVOL,
204 .reg1 = WM8776_REG_OUTMUX,
210 .reg1 = WM8776_REG_OUTMUX,
216 .reg1 = WM8776_REG_DACCTRL1,
222 .reg1 = WM8776_REG_PHASESWAP,
231 .reg1 = WM8776_REG_DACCTRL2,
238 .reg1 = WM8776_REG_ADCLVOL,
248 .reg1 = WM8776_REG_ADCMUX,
257 .reg1 = WM8776_REG_ADCMUX,
263 .reg1 = WM8776_REG_ADCMUX,
269 .reg1 = WM8776_REG_ADCMUX,
275 .reg1 = WM8776_REG_ADCMUX,
281 .reg1 = WM8776_REG_ADCMUX,
297 .reg1 = WM8776_REG_ALCCTRL1,
308 .reg1 = WM8776_REG_ALCCTRL3,
319 .reg1 = WM8776_REG_ALCCTRL3,
329 .reg1 = WM8776_REG_LIMITER,
337 .reg1 = WM8776_REG_LIMITER,
347 .reg1 = WM8776_REG_ALCCTRL1,
359 .reg1 = WM8776_REG_ALCCTRL3,
370 .reg1 = WM8776_REG_ALCCTRL3,
378 .reg1 = WM8776_REG_ALCCTRL1,
388 .reg1 = WM8776_REG_LIMITER,
402 .reg1 = WM8776_REG_ALCCTRL2,
409 .reg1 = WM8776_REG_NOISEGATE,
417 .reg1 = WM8776_REG_NOISEGATE,
503 val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; snd_wm8776_ctl_get()
541 val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; snd_wm8776_ctl_put()
545 wm->ctl[n].reg1 == wm->ctl[n].reg2) { snd_wm8776_ctl_put()
549 snd_wm8776_write(wm, wm->ctl[n].reg1, val); snd_wm8776_ctl_put()
552 wm->ctl[n].reg1 != wm->ctl[n].reg2) { snd_wm8776_ctl_put()
H A Dwm8766.c48 .reg1 = WM8766_REG_DACL1,
59 .reg1 = WM8766_REG_DACL2,
70 .reg1 = WM8766_REG_DACL3,
80 .reg1 = WM8766_REG_DACCTRL2,
87 .reg1 = WM8766_REG_DACCTRL2,
94 .reg1 = WM8766_REG_DACCTRL2,
101 .reg1 = WM8766_REG_IFCTRL,
107 .reg1 = WM8766_REG_IFCTRL,
113 .reg1 = WM8766_REG_IFCTRL,
119 .reg1 = WM8766_REG_DACCTRL2,
125 .reg1 = WM8766_REG_DACCTRL2,
131 .reg1 = WM8766_REG_DACCTRL2,
137 .reg1 = WM8766_REG_DACCTRL1,
143 .reg1 = WM8766_REG_DACCTRL2,
229 val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; snd_wm8766_ctl_get()
267 val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; snd_wm8766_ctl_put()
271 wm->ctl[n].reg1 == wm->ctl[n].reg2) { snd_wm8766_ctl_put()
275 snd_wm8766_write(wm, wm->ctl[n].reg1, val); snd_wm8766_ctl_put()
278 wm->ctl[n].reg1 != wm->ctl[n].reg2) { snd_wm8766_ctl_put()
H A Dwm8766.h138 u16 reg1, reg2, mask1, mask2, min, max, flags; member in struct:snd_wm8766_ctl
H A Dwm8776.h194 u16 reg1, reg2, mask1, mask2, min, max, flags; member in struct:snd_wm8776_ctl
/linux-4.4.14/arch/s390/include/asm/
H A Dsigp.h42 register unsigned long reg1 asm ("1") = parm; __pcpu_sigp()
49 : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); __pcpu_sigp()
51 *status = reg1; __pcpu_sigp()
H A Dprocessor.h246 unsigned int reg1, reg2; __extract_psw() local
248 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); __extract_psw()
249 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); __extract_psw()
H A Detr.h192 register unsigned long reg1 asm("1") = (unsigned long) ptff_block; etr_ptff()
200 : "d" (reg0), "d" (reg1), "m" (ptff_block) : "cc"); etr_ptff()
/linux-4.4.14/drivers/mcb/
H A Dmcb-parse.c45 __le32 reg1; chameleon_parse_gdd() local
52 reg1 = readl(&gdd->reg1); chameleon_parse_gdd()
57 mdev->id = GDD_DEV(reg1); chameleon_parse_gdd()
58 mdev->rev = GDD_REV(reg1); chameleon_parse_gdd()
59 mdev->var = GDD_VAR(reg1); chameleon_parse_gdd()
66 mdev->irq.start = GDD_IRQ(reg1); chameleon_parse_gdd()
67 mdev->irq.end = GDD_IRQ(reg1); chameleon_parse_gdd()
H A Dmcb-internal.h66 __le32 reg1; member in struct:chameleon_gdd
/linux-4.4.14/drivers/media/dvb-frontends/
H A Dtua6100.c77 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; tua6100_set_params() local
80 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; tua6100_set_params()
95 reg1[1] = 0x2c; tua6100_set_params()
97 reg1[1] = 0x0c; tua6100_set_params()
100 reg1[1] |= 0x40; tua6100_set_params()
102 reg1[1] |= 0x80; tua6100_set_params()
120 reg1[1] |= (div >> 9) & 0x03; tua6100_set_params()
121 reg1[2] = div >> 1; tua6100_set_params()
122 reg1[3] = (div << 7); tua6100_set_params()
126 reg1[3] |= (prediv - (div*_P)) & 0x7f; tua6100_set_params()
H A Da8293.c30 u8 reg0, reg1; a8293_set_voltage() local
59 reg1 = 0x82; a8293_set_voltage()
60 if (reg1 != dev->reg[1]) { a8293_set_voltage()
61 ret = i2c_master_send(client, &reg1, 1); a8293_set_voltage()
64 dev->reg[1] = reg1; a8293_set_voltage()
H A Dsi21xx.c227 static int si21_writeregs(struct si21xx_state *state, u8 reg1, si21_writeregs() argument
231 u8 buf[60];/* = { reg1, data };*/ si21_writeregs()
242 msg.buf[0] = reg1; si21_writeregs()
248 dprintk("%s: writereg error (reg1 == 0x%02x, data == 0x%02x, " si21_writeregs()
249 "ret == %i)\n", __func__, reg1, data[0], ret); si21_writeregs()
312 static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len) si21_readregs() argument
319 .buf = &reg1, si21_readregs()
486 u8 reg1; si21xx_init() local
493 reg1 = serit_sp1511lhb_inittab[i]; si21xx_init()
495 if (reg1 == 0xff && val == 0xff) si21xx_init()
497 si21_writeregs(state, reg1, &val, 1); si21xx_init()
501 reg1 = 0x08; si21xx_init()
502 si21_writeregs(state, SYSTEM_MODE_REG, &reg1, 0x01); si21xx_init()
H A Dm88rs2000.c253 u8 reg0, reg1; m88rs2000_send_diseqc_burst() local
258 reg1 = m88rs2000_readreg(state, 0xb2); m88rs2000_send_diseqc_burst()
260 m88rs2000_writereg(state, 0xb2, reg1); m88rs2000_send_diseqc_burst()
271 u8 reg0, reg1; m88rs2000_set_tone() local
274 reg1 = m88rs2000_readreg(state, 0xb2); m88rs2000_set_tone()
276 reg1 &= 0x3f; m88rs2000_set_tone()
284 reg1 |= 0x80; m88rs2000_set_tone()
289 m88rs2000_writereg(state, 0xb2, reg1); m88rs2000_set_tone()
H A Dstv0297.c107 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len) stv0297_readregs() argument
111 &reg1,.len = 1}, stv0297_readregs()
118 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); stv0297_readregs()
122 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); stv0297_readregs()
127 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); stv0297_readregs()
H A Ds5h1409.c568 u16 reg, reg1, reg2; s5h1409_set_qam_interleave_mode() local
583 reg1 = s5h1409_readreg(state, 0xb2); s5h1409_set_qam_interleave_mode()
588 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); s5h1409_set_qam_interleave_mode()
606 u16 reg, reg1, reg2; s5h1409_set_qam_interleave_mode_legacy() local
614 reg1 = s5h1409_readreg(state, 0xb2); s5h1409_set_qam_interleave_mode_legacy()
619 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); s5h1409_set_qam_interleave_mode_legacy()
H A Dtda8083.c76 static int tda8083_readregs (struct tda8083_state* state, u8 reg1, u8 *b, u8 len) tda8083_readregs() argument
79 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = &reg1, .len = 1 }, tda8083_readregs()
86 __func__, reg1, ret); tda8083_readregs()
H A Dstv0299.c124 static int stv0299_readregs (struct stv0299_state* state, u8 reg1, u8 *b, u8 len) stv0299_readregs() argument
127 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = &reg1, .len = 1 }, stv0299_readregs()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); nv04_clk_pll_prog()
H A Dpriv.h25 int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
/linux-4.4.14/arch/arm/kernel/
H A Dhyp-stub.S40 .macro store_primary_cpu_mode reg1, reg2, reg3
41 mrs \reg1, cpsr
42 and \reg1, \reg1, #MODE_MASK
45 str \reg1, [\reg2, \reg3]
54 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
57 ldr \reg1, [\reg2, \reg3]
58 cmp \mode, \reg1 @ matches primary CPU boot mode?
59 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
60 strne \reg1, [\reg2, \reg3] @ record what happened and give up
65 .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req
72 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
/linux-4.4.14/drivers/usb/phy/
H A Dphy-rcar-usb.c68 void __iomem *reg1; member in struct:rcar_usb_phy_priv
88 void __iomem *reg1 = priv->reg1; rcar_usb_phy_init() local
108 if (reg1) { rcar_usb_phy_init()
112 iowrite32(hsqctl1, reg1 + HSQCTL1); rcar_usb_phy_init()
113 iowrite32(hsqctl2, reg1 + HSQCTL2); rcar_usb_phy_init()
184 void __iomem *reg0, *reg1 = NULL; rcar_usb_phy_probe() local
198 reg1 = devm_ioremap_resource(dev, res1); rcar_usb_phy_probe()
199 if (IS_ERR(reg1)) rcar_usb_phy_probe()
200 return PTR_ERR(reg1); rcar_usb_phy_probe()
207 priv->reg1 = reg1; rcar_usb_phy_probe()
/linux-4.4.14/arch/s390/kvm/
H A Dtrace.h284 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
285 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
290 __field(int, reg1)
298 __entry->reg1 = reg1;
305 __entry->reg1, __entry->reg3, __entry->addr)
309 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
310 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
315 __field(int, reg1)
323 __entry->reg1 = reg1;
330 __entry->reg1, __entry->reg3, __entry->addr)
H A Dpriv.c629 int reg1, reg2; handle_epsw() local
631 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); handle_epsw()
634 vcpu->run->s.regs.gprs[reg1] &= 0xffffffff00000000UL; handle_epsw()
635 vcpu->run->s.regs.gprs[reg1] |= vcpu->arch.sie_block->gpsw.mask >> 32; handle_epsw()
656 int reg1, reg2; handle_pfmf() local
661 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); handle_pfmf()
669 if (vcpu->run->s.regs.gprs[reg1] & PFMF_RESERVED) handle_pfmf()
673 if (vcpu->run->s.regs.gprs[reg1] & PFMF_NQ && !test_facility(14)) handle_pfmf()
677 if (vcpu->run->s.regs.gprs[reg1] & (PFMF_MR | PFMF_MC)) handle_pfmf()
683 switch (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { handle_pfmf()
702 if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { handle_pfmf()
711 if ((vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) == 0) handle_pfmf()
719 if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { handle_pfmf()
724 if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK) { handle_pfmf()
730 vcpu->run->s.regs.gprs[reg1] & PFMF_KEY, handle_pfmf()
731 vcpu->run->s.regs.gprs[reg1] & PFMF_NQ)) handle_pfmf()
737 if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) handle_pfmf()
804 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; kvm_s390_handle_lctl() local
821 VCPU_EVENT(vcpu, 4, "LCTL: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); kvm_s390_handle_lctl()
822 trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, ga); kvm_s390_handle_lctl()
824 nr_regs = ((reg3 - reg1) & 0xf) + 1; kvm_s390_handle_lctl()
828 reg = reg1; kvm_s390_handle_lctl()
843 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; kvm_s390_handle_stctl() local
860 VCPU_EVENT(vcpu, 4, "STCTL r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); kvm_s390_handle_stctl()
861 trace_kvm_s390_handle_stctl(vcpu, 0, reg1, reg3, ga); kvm_s390_handle_stctl()
863 reg = reg1; kvm_s390_handle_stctl()
877 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; handle_lctlg() local
894 VCPU_EVENT(vcpu, 4, "LCTLG: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); handle_lctlg()
895 trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, ga); handle_lctlg()
897 nr_regs = ((reg3 - reg1) & 0xf) + 1; handle_lctlg()
901 reg = reg1; handle_lctlg()
915 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; handle_stctg() local
932 VCPU_EVENT(vcpu, 4, "STCTG r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); handle_stctg()
933 trace_kvm_s390_handle_stctl(vcpu, 1, reg1, reg3, ga); handle_stctg()
935 reg = reg1; handle_stctg()
H A Dintercept.c302 int reg1, reg2, rc; handle_mvpg_pei() local
304 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); handle_mvpg_pei()
316 rc = guest_translate_address(vcpu, vcpu->run->s.regs.gprs[reg1], handle_mvpg_pei()
317 reg1, &dstaddr, 1); handle_mvpg_pei()
/linux-4.4.14/arch/m32r/kernel/
H A Dalign.c277 int reg1, reg2; emu_mul() local
279 reg1 = get_reg(regs, dest); emu_mul()
284 : "+r" (reg1) : "r" (reg2) emu_mul()
287 set_reg(regs, dest, reg1); emu_mul()
294 int reg1, reg2; emu_mullo_a0() local
296 reg1 = get_reg(regs, REG1(insn)); emu_mullo_a0()
303 : "+r" (reg1), "+r" (reg2) emu_mullo_a0()
306 regs->acc0h = reg1; emu_mullo_a0()
314 int reg1, reg2; emu_mullo_a1() local
316 reg1 = get_reg(regs, REG1(insn)); emu_mullo_a1()
323 : "+r" (reg1), "+r" (reg2) emu_mullo_a1()
326 regs->acc1h = reg1; emu_mullo_a1()
H A Dptrace.c225 unsigned long reg1, reg2; check_condition_src() local
231 reg1 = get_stack_long(child, reg_offset[regno1]); check_condition_src()
232 return reg1 == reg2; check_condition_src()
234 reg1 = get_stack_long(child, reg_offset[regno1]); check_condition_src()
235 return reg1 != reg2; check_condition_src()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c185 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) new_ramdac580() argument
187 bool head_a = (reg1 == 0x680508); new_ramdac580()
198 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, setPLL_double_highregs() argument
204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); setPLL_double_highregs()
205 uint32_t oldpll1 = nvkm_rd32(device, reg1); setPLL_double_highregs()
212 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); setPLL_double_highregs()
220 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ setPLL_double_highregs()
222 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); setPLL_double_highregs()
246 switch (reg1) { setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); setPLL_double_highregs()
/linux-4.4.14/sound/pci/
H A Dak4531_codec.c213 #define AK4531_INPUT_SW(xname, xindex, reg1, reg2, left_shift, right_shift) \
217 .private_value = reg1 | (reg2 << 8) | (left_shift << 16) | (right_shift << 24) }
231 int reg1 = kcontrol->private_value & 0xff; snd_ak4531_get_input_sw() local
237 ucontrol->value.integer.value[0] = (ak4531->regs[reg1] >> left_shift) & 1; snd_ak4531_get_input_sw()
239 ucontrol->value.integer.value[2] = (ak4531->regs[reg1] >> right_shift) & 1; snd_ak4531_get_input_sw()
248 int reg1 = kcontrol->private_value & 0xff; snd_ak4531_put_input_sw() local
256 val1 = ak4531->regs[reg1] & ~((1 << left_shift) | (1 << right_shift)); snd_ak4531_put_input_sw()
262 change = val1 != ak4531->regs[reg1] || val2 != ak4531->regs[reg2]; snd_ak4531_put_input_sw()
263 ak4531->write(ak4531, reg1, ak4531->regs[reg1] = val1); snd_ak4531_put_input_sw()
/linux-4.4.14/drivers/mfd/
H A Drtl8411.c52 u32 reg1 = 0; rtl8411_fetch_vendor_settings() local
55 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg1); rtl8411_fetch_vendor_settings()
56 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); rtl8411_fetch_vendor_settings()
58 if (!rtsx_vendor_setting_valid(reg1)) rtl8411_fetch_vendor_settings()
61 pcr->aspm_en = rtsx_reg_to_aspm(reg1); rtl8411_fetch_vendor_settings()
63 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); rtl8411_fetch_vendor_settings()
65 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); rtl8411_fetch_vendor_settings()
H A Drdc321x-southbridge.c46 .name = "gpio-reg1",
/linux-4.4.14/drivers/pci/host/
H A Dpcie-altera.c80 u32 reg1; member in struct:tlp_rp_regpair_t
137 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); tlp_write_tx()
174 u32 reg0, reg1; tlp_read_packet() local
185 reg1 = cra_readl(pcie, RP_RXCPL_REG1); tlp_read_packet()
189 comp_status = TLP_COMP_STATUS(reg1); tlp_read_packet()
214 tlp_rp_regdata.reg1 = headers[1]; tlp_write_packet()
220 tlp_rp_regdata.reg1 = 0; tlp_write_packet()
225 tlp_rp_regdata.reg1 = 0; tlp_write_packet()
228 tlp_rp_regdata.reg1 = data; tlp_write_packet()
/linux-4.4.14/arch/ia64/include/asm/native/
H A Dinst.h86 #define THASH(pred, reg0, reg1, clob) \
87 (pred) thash reg0 = reg1
/linux-4.4.14/drivers/gpu/ipu-v3/
H A Dipu-dc.c134 u32 reg1, reg2; dc_write_tmpl() local
137 reg1 = (operand << 20) & 0xfff00000; dc_write_tmpl()
140 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); dc_write_tmpl()
143 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); dc_write_tmpl()
146 writel(reg1, priv->dc_tmpl_reg + word * 8); dc_write_tmpl()
/linux-4.4.14/drivers/s390/crypto/
H A Dap_bus.c139 register unsigned long reg1 asm ("1") = -ENODEV; ap_instructions_available()
147 : "+d" (reg0), "+d" (reg1), "+d" (reg2) : : "cc" ); ap_instructions_available()
148 return reg1; ap_instructions_available()
183 register struct ap_queue_status reg1 asm ("1"); ap_test_queue()
189 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc"); ap_test_queue()
192 return reg1; ap_test_queue()
204 register struct ap_queue_status reg1 asm ("1"); ap_reset_queue()
209 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc"); ap_reset_queue()
210 return reg1; ap_reset_queue()
243 register unsigned long reg1 asm ("1") = -EINVAL; ap_query_configuration()
253 : "+d" (reg0), "+d" (reg1), "+d" (reg2) ap_query_configuration()
257 return reg1; ap_query_configuration()
368 register struct ap_queue_status reg1 asm ("1"); __ap_send()
380 : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3) __ap_send()
383 return reg1; __ap_send()
428 register struct ap_queue_status reg1 asm ("1"); __ap_recv()
439 : "+d" (reg0), "=d" (reg1), "+d" (reg2), __ap_recv()
443 return reg1; __ap_recv()
/linux-4.4.14/drivers/net/wireless/ath/ath10k/
H A Dspectral.c67 u32 reg0, reg1; ath10k_spectral_process_fft() local
86 reg1 = __le32_to_cpu(fftr->reg1); ath10k_spectral_process_fft()
117 fft_sample->relpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB); ath10k_spectral_process_fft()
118 fft_sample->avgpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB); ath10k_spectral_process_fft()
120 peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG); ath10k_spectral_process_fft()
H A Dwmi.c3402 u32 reg0, reg1, tsf32l; ath10k_dfs_radar_report() local
3409 reg1 = __le32_to_cpu(rr->reg1); ath10k_dfs_radar_report()
3421 MS(reg1, RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID), ath10k_dfs_radar_report()
3422 MS(reg1, RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN), ath10k_dfs_radar_report()
3423 MS(reg1, RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK)); ath10k_dfs_radar_report()
3426 MS(reg1, RADAR_REPORT_REG1_PULSE_TSF_OFFSET), ath10k_dfs_radar_report()
3427 MS(reg1, RADAR_REPORT_REG1_PULSE_DUR)); ath10k_dfs_radar_report()
3446 width = MS(reg1, RADAR_REPORT_REG1_PULSE_DUR); ath10k_dfs_radar_report()
3491 u32 reg0, reg1; ath10k_dfs_fft_report() local
3495 reg1 = __le32_to_cpu(fftr->reg1); ath10k_dfs_fft_report()
3506 MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB), ath10k_dfs_fft_report()
3507 MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB), ath10k_dfs_fft_report()
3508 MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG), ath10k_dfs_fft_report()
3509 MS(reg1, SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB)); ath10k_dfs_fft_report()
3511 peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG); ath10k_dfs_fft_report()
H A Dwmi.h3058 __le32 reg1; /* REDAR_REPORT_REG1_* */ member in struct:phyerr_radar_report
3096 __le32 reg1; /* SEARCH_FFT_REPORT_REG1_ * */ member in struct:phyerr_fft_report
/linux-4.4.14/drivers/power/
H A Dwm831x_power.c223 int ret, reg1, reg2; wm831x_config_battery() local
233 reg1 = 0; wm831x_config_battery()
241 reg1 |= WM831X_CHG_ENA; wm831x_config_battery()
245 reg1 |= WM831X_CHG_FAST; wm831x_config_battery()
261 pdata->eoc_iterm, &reg1, wm831x_config_battery()
278 reg1); wm831x_config_battery()
/linux-4.4.14/arch/xtensa/lib/
H A Dmemset.S33 #define EX(insn,reg1,reg2,offset,handler) \
34 9: insn reg1, reg2, offset; \
H A Dstrnlen_user.S18 #define EX(insn,reg1,reg2,offset,handler) \
19 9: insn reg1, reg2, offset; \
H A Dstrncpy_user.S19 #define EX(insn,reg1,reg2,offset,handler) \
20 9: insn reg1, reg2, offset; \
H A Dusercopy.S68 #define EX(insn,reg1,reg2,offset,handler) \
69 9: insn reg1, reg2, offset; \
/linux-4.4.14/drivers/gpio/
H A Dgpio-rdc321x.c149 r = platform_get_resource_byname(pdev, IORESOURCE_IO, "gpio-reg1"); rdc321x_gpio_probe()
151 dev_err(&pdev->dev, "failed to get gpio-reg1 resource\n"); rdc321x_gpio_probe()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dclk.h103 int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
/linux-4.4.14/include/sound/
H A Dsb.h343 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
344 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
365 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
368 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
/linux-4.4.14/include/linux/mfd/
H A Dtps6105x.h22 /* These defines for both reg0 and reg1 */
/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, nouveau_hw_decode_pll() argument
143 if (reg1 <= 0x405c) { nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; nouveau_hw_get_pllvals() local
175 if (ret || !(reg1 = pll_lim.reg)) nouveau_hw_get_pllvals()
178 pll1 = nvif_rd32(device, reg1); nouveau_hw_get_pllvals()
179 if (reg1 <= 0x405c) nouveau_hw_get_pllvals()
180 pll2 = nvif_rd32(device, reg1 + 4); nouveau_hw_get_pllvals()
182 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); nouveau_hw_get_pllvals()
187 if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { nouveau_hw_get_pllvals()
191 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { nouveau_hw_get_pllvals()
199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); nouveau_hw_get_pllvals()
/linux-4.4.14/sound/soc/codecs/
H A Dwm8993.c474 u16 reg1, reg4, reg5; _wm8993_set_fll() local
489 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); _wm8993_set_fll()
490 reg1 &= ~WM8993_FLL_ENA; _wm8993_set_fll()
491 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); _wm8993_set_fll()
522 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); _wm8993_set_fll()
523 reg1 &= ~WM8993_FLL_ENA; _wm8993_set_fll()
524 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); _wm8993_set_fll()
528 reg1 |= WM8993_FLL_FRAC_MASK; _wm8993_set_fll()
530 reg1 &= ~WM8993_FLL_FRAC_MASK; _wm8993_set_fll()
531 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); _wm8993_set_fll()
558 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA); _wm8993_set_fll()
H A Dwm9081.c553 u16 reg1, reg4, reg5; wm9081_set_fll() local
596 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1); wm9081_set_fll()
597 reg1 &= ~WM9081_FLL_ENA; wm9081_set_fll()
598 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1); wm9081_set_fll()
602 reg1 |= WM9081_FLL_FRAC_MASK; wm9081_set_fll()
604 reg1 &= ~WM9081_FLL_FRAC_MASK; wm9081_set_fll()
605 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1); wm9081_set_fll()
626 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); wm9081_set_fll()
H A Dwm8995.c676 int reg1 = 0; configure_aif_clock() local
691 reg1 |= 0x8; configure_aif_clock()
695 reg1 |= 0x10; configure_aif_clock()
699 reg1 |= 0x18; configure_aif_clock()
708 reg1 |= WM8995_AIF1CLK_DIV; configure_aif_clock()
718 reg1); configure_aif_clock()
H A Dwm8994.c164 int reg1 = 0; configure_aif_clock() local
178 reg1 |= 0x8; configure_aif_clock()
183 reg1 |= 0x10; configure_aif_clock()
188 reg1 |= 0x18; configure_aif_clock()
198 reg1 |= WM8994_AIF1CLK_DIV; configure_aif_clock()
208 reg1); configure_aif_clock()
/linux-4.4.14/drivers/ata/
H A Dpata_hpt366.c356 u32 reg1; hpt36x_init_one() local
370 pci_read_config_dword(dev, 0x40, &reg1); hpt36x_init_one()
374 switch ((reg1 & 0x700) >> 8) { hpt36x_init_one()
H A Dpata_macio.c260 u32 reg1; /* Bits to set in first timing reg */ member in struct:pata_macio_timing
416 priv->treg[adev->devno][0] |= t->reg1; pata_macio_set_timings()
420 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { pata_macio_set_timings()
427 priv->treg[adev->devno][0] |= t->reg1; pata_macio_set_timings()
/linux-4.4.14/drivers/scsi/
H A Dmac_esp.c313 #define MAC_ESP_PIO_LOOP(operands, reg1) \
318 : "+a" (addr), "+r" (reg1) \
321 #define MAC_ESP_PIO_FILL(operands, reg1) \
341 : "+a" (addr), "+r" (reg1) \
/linux-4.4.14/drivers/ide/
H A Dali14xx.c72 static struct { u8 reg1, reg2, reg3, reg4; } regTab[4] = { member in struct:__anon5092
138 outReg(param1, regTab[driveNum].reg1); ali14xx_set_pio_mode()
/linux-4.4.14/arch/sparc/lib/
H A Dcopy_page.S36 #define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7) \
37 fsrc2 %reg0, %f48; fsrc2 %reg1, %f50; \
/linux-4.4.14/arch/arc/include/asm/
H A Dentry.h29 * LD.a reg1, [reg2, x] => Pre Incr
32 * LD.ab reg1, [reg2, x] => Post Incr
/linux-4.4.14/arch/arm64/include/asm/
H A Dinsn.h309 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
345 enum aarch64_insn_register reg1,
/linux-4.4.14/sound/isa/sb/
H A Dsb_mixer.c403 int reg1 = kcontrol->private_value & 0xff; snd_sb16mixer_get_input_sw() local
410 val1 = snd_sbmixer_read(sb, reg1); snd_sb16mixer_get_input_sw()
424 int reg1 = kcontrol->private_value & 0xff; snd_sb16mixer_put_input_sw() local
432 oval1 = snd_sbmixer_read(sb, reg1); snd_sb16mixer_put_input_sw()
442 snd_sbmixer_write(sb, reg1, val1); snd_sb16mixer_put_input_sw()
/linux-4.4.14/drivers/input/touchscreen/
H A Dbcm_iproc_tsc.c67 /* Bit values for CONTROLLER_STATUS reg1 */
70 /* Shift values for control reg1 */
286 /* Initialize control reg1 */ iproc_ts_start()
H A Drohm_bu21023.c332 u8 reg1, reg2, reg3; rohm_ts_manual_calibration() local
417 reg1 = reg_x >> 3; rohm_ts_manual_calibration()
422 CALIBRATION_REG1, reg1); rohm_ts_manual_calibration()
/linux-4.4.14/drivers/net/ethernet/8390/
H A Dwd.c245 outb(tmp, ioaddr+1); /* Restore original reg1 value. */ wd_probe1()
281 int reg1 = inb(ioaddr+1); wd_probe1() local
283 if (ancient || reg1 == 0xff) { /* Ack!! No way to read the IRQ! */ wd_probe1()
308 dev->irq = irqmap[((reg4 >> 5) & 0x03) + (reg1 & 0x04)]; wd_probe1()
/linux-4.4.14/arch/mips/include/asm/octeon/
H A Dcvmx-pko.h177 * The size of the reg1 operation - could be 8, 16,
192 * The register, subtract will be done if reg1 is
195 uint64_t reg1:11; member in struct:__anon1989::__anon1990
258 uint64_t reg1:11;
/linux-4.4.14/arch/mips/mm/
H A Dpage.c106 pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) pg_addiu() argument
114 uasm_i_daddu(buf, reg1, reg2, T9); pg_addiu()
119 UASM_i_ADDU(buf, reg1, reg2, T9); pg_addiu()
121 UASM_i_ADDIU(buf, reg1, reg2, off); pg_addiu()
H A Duasm.c548 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, uasm_il_bne() argument
552 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); uasm_il_bne()
/linux-4.4.14/arch/arm64/kernel/
H A Dinsn.c624 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, aarch64_insn_gen_load_store_pair() argument
672 reg1); aarch64_insn_gen_load_store_pair()
964 enum aarch64_insn_register reg1, aarch64_insn_gen_data3()
999 reg1); aarch64_insn_gen_data3()
962 aarch64_insn_gen_data3(enum aarch64_insn_register dst, enum aarch64_insn_register src, enum aarch64_insn_register reg1, enum aarch64_insn_register reg2, enum aarch64_insn_variant variant, enum aarch64_insn_data3_type type) aarch64_insn_gen_data3() argument
/linux-4.4.14/drivers/iio/adc/
H A Dtwl6030-gpadc.c696 unsigned int reg1, unsigned int mask0, unsigned int mask1, twl6032_get_trim_value()
702 val |= (trim_regs[reg1] & mask1) >> 1; twl6032_get_trim_value()
703 if (trim_regs[reg1] & 0x01) twl6032_get_trim_value()
695 twl6032_get_trim_value(u8 *trim_regs, unsigned int reg0, unsigned int reg1, unsigned int mask0, unsigned int mask1, unsigned int shift0) twl6032_get_trim_value() argument
/linux-4.4.14/drivers/usb/serial/
H A Dch341.c390 dev_dbg(&port->dev, "%s - initial ch341 break register contents - reg1: %x, reg2: %x\n", ch341_break_ctl()
401 dev_dbg(&port->dev, "%s - New ch341 break register contents - reg1: %x, reg2: %x\n", ch341_break_ctl()
/linux-4.4.14/drivers/gpu/drm/r128/
H A Dr128_drv.h410 #define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \
411 (((reg1) >> 2) << 11) | ((reg0) >> 2))
/linux-4.4.14/drivers/net/ethernet/qlogic/qed/
H A Dqed_hsi.h294 __le32 reg1 /* reg1 */; member in struct:xstorm_core_conn_ag_ctx
853 __le32 reg1 /* reg1 */; member in struct:mstorm_core_conn_ag_ctx
1043 __le32 reg1 /* reg1 */; member in struct:tstorm_core_conn_ag_ctx
1125 __le32 reg1 /* reg1 */; member in struct:ustorm_core_conn_ag_ctx
1167 __le32 reg1 /* reg1 */; member in struct:ystorm_core_conn_ag_ctx
2525 __le32 reg1 /* reg1 */; member in struct:xstorm_eth_conn_ag_ctx
2922 __le32 reg1 /* reg1 */; member in struct:mstorm_eth_conn_ag_ctx
3009 __le32 reg1 /* reg1 */; member in struct:tstorm_eth_conn_ag_ctx
3091 __le32 reg1 /* reg1 */; member in struct:ustorm_eth_conn_ag_ctx
/linux-4.4.14/drivers/gpu/drm/mga/
H A Dmga_drv.h321 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
324 (DMAREG(reg1) << 8) | \
/linux-4.4.14/drivers/staging/rts5208/
H A Drtsx_card.c94 u8 reg1 = 0, reg2 = 0; try_to_switch_sdio_ctrl() local
96 rtsx_read_register(chip, 0xFF34, &reg1); try_to_switch_sdio_ctrl()
99 reg1, reg2); try_to_switch_sdio_ctrl() local
100 if ((reg1 & 0xC0) && (reg2 & 0xC0)) { try_to_switch_sdio_ctrl()
H A Drtsx_chip.c1103 u8 reg0 = 0, reg1 = 0; rtsx_monitor_aspm_config() local
1114 reg1 = (u8)tmp; rtsx_monitor_aspm_config()
1115 if (chip->aspm_level[1] != reg1) { rtsx_monitor_aspm_config()
1117 chip->aspm_level[1] = reg1; rtsx_monitor_aspm_config()
1120 if ((reg0 & 0x03) && (reg1 & 0x03)) rtsx_monitor_aspm_config()
/linux-4.4.14/drivers/net/wireless/zd1211rw/
H A Dzd_rf_rf2959.c70 PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
/linux-4.4.14/net/iucv/
H A Diucv.c326 register unsigned long reg1 asm ("1"); iucv_call_b2f0()
330 reg1 = virt_to_phys(parm); iucv_call_b2f0()
335 : "=d" (ccode), "=m" (*parm), "+d" (reg0), "+a" (reg1) iucv_call_b2f0()
351 register unsigned long reg1 asm ("1"); iucv_query_maxconn()
359 reg1 = (unsigned long) param; iucv_query_maxconn()
364 : "=d" (ccode), "+d" (reg0), "+d" (reg1) : : "cc"); iucv_query_maxconn()
366 iucv_max_pathid = reg1; iucv_query_maxconn()
/linux-4.4.14/drivers/media/i2c/
H A Dov9650.c861 u8 reg0, reg1, reg2; __g_volatile_ctrl() local
874 ret = ov965x_read(client, REG_VREF, &reg1); __g_volatile_ctrl()
877 gain = ((reg1 >> 6) << 8) | reg0; __g_volatile_ctrl()
887 ret = ov965x_read(client, REG_AECH, &reg1); __g_volatile_ctrl()
892 exposure = ((reg2 & 0x3f) << 10) | (reg1 << 2) | __g_volatile_ctrl()
/linux-4.4.14/drivers/media/usb/gspca/
H A Dsonixj.c151 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
162 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
173 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
184 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
195 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
206 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
217 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
228 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
239 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
250 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
261 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
272 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
283 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
294 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
305 /* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */
H A Dsonixb.c1152 clock is set to 12 Mhz (reg1 == 0x04), rather then 24. sd_start()
/linux-4.4.14/drivers/hwmon/
H A Dw83795.c308 u8 reg0, reg1; pwm_freq_to_reg() local
320 reg1 = clamp_val(DIV_ROUND_CLOSEST(base_clock, val), 1, 128); pwm_freq_to_reg()
321 best1 = base_clock / reg1; pwm_freq_to_reg()
322 reg1 = 0x80 | (reg1 - 1); pwm_freq_to_reg()
326 return reg1; pwm_freq_to_reg()
/linux-4.4.14/arch/c6x/platforms/
H A Ddscr.c317 * reg1 b3 b2 b1 b0>
319 * reg0 and reg1 are the offsets of the two fuse registers.
/linux-4.4.14/drivers/staging/xgifb/
H A DXGI_main_26.c1650 u8 reg, reg1; xgifb_probe() local
1699 reg1 = xgifb_reg_get(XGISR, IND_SIS_PASSWORD); xgifb_probe()
1701 if (reg1 != 0xa1) { /*I/O error */ xgifb_probe()
1842 reg1 = xgifb_reg_get(XGIPART4, 0x23); xgifb_probe()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dmpc52xx.h199 u32 rstcfg; /* CDM + 0x04 reg1 read only */
/linux-4.4.14/arch/mips/include/asm/
H A Duasm.h301 void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dsky2.c708 u32 reg1; sky2_phy_power_up() local
711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); sky2_phy_power_up()
712 reg1 &= ~phy_power[port]; sky2_phy_power_up()
715 reg1 |= coma_mode[port]; sky2_phy_power_up()
717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); sky2_phy_power_up()
729 u32 reg1; sky2_phy_power_down() local
776 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); sky2_phy_power_down()
777 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ sky2_phy_power_down()
778 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); sky2_phy_power_down()
879 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); sky2_wol_init() local
880 reg1 |= PCI_Y2_PME_LEGACY; sky2_wol_init()
881 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); sky2_wol_init()
/linux-4.4.14/arch/mips/net/
H A Dbpf_jit.c476 static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2, emit_bcond() argument
484 uasm_i_beq(&p, reg1, reg2, imm); emit_bcond()
487 uasm_i_bne(&p, reg1, reg2, imm); emit_bcond()
/linux-4.4.14/drivers/video/fbdev/sis/
H A Dsis_main.c815 u8 idx, reg1, reg2, reg3, reg4; sisfb_setupvbblankflags() local
832 reg1 = SiS_GetReg(SISPART1, (idx+0)); /* 30 */ sisfb_setupvbblankflags()
836 if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING; sisfb_setupvbblankflags()
837 if(reg1 & 0x02) ret |= FB_VBLANK_VSYNCING; sisfb_setupvbblankflags()
848 reg1 = SiS_GetRegByte(SISINPSTAT); sisfb_setupvbblankflags()
849 if(reg1 & 0x08) ret |= FB_VBLANK_VSYNCING; sisfb_setupvbblankflags()
850 if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING; sisfb_setupvbblankflags()
851 reg1 = SiS_GetReg(SISCR, 0x20); sisfb_setupvbblankflags()
852 reg1 = SiS_GetReg(SISCR, 0x1b); sisfb_setupvbblankflags()
856 (*hcount) = (reg1 | ((reg3 & 0x10) << 4)) << 3; sisfb_setupvbblankflags()
3779 u8 reg1; sisfb_post_setmode() local
3814 reg1 = 0xc0; sisfb_post_setmode()
3818 reg1 = 0x00; sisfb_post_setmode()
3821 SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, reg1); sisfb_post_setmode()
H A Dinit301.c7348 unsigned short vclkindex, temp, reg1, reg2; SiS_SetCRT2VCLK() local
7351 reg1 = SiS_Pr->CSR2B; SiS_SetCRT2VCLK()
7355 reg1 = SiS_Pr->SiS_VBVCLKData[vclkindex].Part4_A; SiS_SetCRT2VCLK()
7365 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1); SiS_SetCRT2VCLK()
7371 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1); SiS_SetCRT2VCLK()
/linux-4.4.14/drivers/thermal/ti-soc-thermal/
H A Dti-bandgap.c1054 u32 temp1, temp2, reg1, reg2; ti_bandgap_get_trend() local
1073 reg1 = tsr->ctrl_dtemp_1; ti_bandgap_get_trend()
1077 temp1 = ti_bandgap_readl(bgp, reg1); ti_bandgap_get_trend()
/linux-4.4.14/arch/ia64/kernel/
H A Dhead.S98 #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
99 movl reg1=sal_state_for_booting_cpu;; \
100 ld8 reg2=[reg1];;
/linux-4.4.14/drivers/video/fbdev/i810/
H A Di810_main.c402 u32 reg1; i810_load_color() local
405 reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27); i810_load_color()
408 reg1 |= 0x8000 | par->pixconf; i810_load_color()
410 i810_writel(PIXCONF, mmio, reg1); i810_load_color()
/linux-4.4.14/drivers/net/irda/
H A Dnsc-ircc.c875 int reg1, reg2, irq, irqt, dma1, dma2; nsc_ircc_probe_39x() local
890 reg1 = inb(cfg_base+1); nsc_ircc_probe_39x()
893 info->fir_base = (reg1 << 8) | reg2; nsc_ircc_probe_39x()
914 __func__, reg1, reg2, irq, irqt, dma1, dma2, enabled, susp); nsc_ircc_probe_39x()
/linux-4.4.14/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_init.c539 u32 reg, reg1, reg2, i, j, owner, class; qlcnic_83xx_idc_find_reset_owner_id() local
541 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); qlcnic_83xx_idc_find_reset_owner_id()
546 reg = reg1; qlcnic_83xx_idc_find_reset_owner_id()
566 reg = reg1; qlcnic_83xx_idc_find_reset_owner_id()
/linux-4.4.14/arch/sparc/kernel/
H A Dprom_64.c264 /* "name@reg0[,reg1]" */ usb_path_component()
/linux-4.4.14/arch/s390/kernel/
H A Dsmp.c318 register unsigned long reg1 asm ("1") = (unsigned long) mtid; pcpu_set_smt()
327 : "=d" (cc) : "d" (reg1), "K" (SIGP_SET_MULTI_THREADING) pcpu_set_smt()
/linux-4.4.14/drivers/net/ethernet/qlogic/
H A Dqla3xxx.c972 u16 reg1; PHY_Setup() local
979 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1); PHY_Setup()
992 if ((reg1 == 0xffff) || (reg2 == 0xffff)) { PHY_Setup()
1001 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr); PHY_Setup()
1020 qdev->phyType = getPhyType(qdev, reg1, reg2); PHY_Setup()
/linux-4.4.14/drivers/net/ethernet/adaptec/
H A Dstarfire.c1588 u16 reg0, reg1, reg4, reg5; netdev_media_change() local
1597 reg1 = mdio_read(dev, np->phys[0], MII_BMSR); netdev_media_change()
1599 if (reg1 & BMSR_LSTATUS) { netdev_media_change()
/linux-4.4.14/drivers/edac/
H A Damd64_edac.c803 int reg1 = DCSB1 + (cs * 4); read_dct_base_mask() local
816 cs, *base1, (pvt->fam == 0x10) ? reg1 read_dct_base_mask()
822 int reg1 = DCSM1 + (cs * 4); read_dct_base_mask() local
835 cs, *mask1, (pvt->fam == 0x10) ? reg1 read_dct_base_mask()
/linux-4.4.14/sound/sparc/
H A Ddbri.c1935 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", snd_dbri_interrupt()
1939 "DBRI: Multiple Late Error on SBus reg1=0x%x\n", snd_dbri_interrupt()
1943 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); snd_dbri_interrupt()
1946 "DBRI: Burst Error on SBus reg1=0x%x\n", x); snd_dbri_interrupt()
/linux-4.4.14/drivers/infiniband/hw/qib/
H A Dqib_iba7322.c6809 u64 reg, reg1, reg2; dump_sdma_7322_state() local
6824 reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1); dump_sdma_7322_state()
6828 reg, reg1, reg2); dump_sdma_7322_state()
6833 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); dump_sdma_7322_state()
6834 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1); dump_sdma_7322_state()
6840 reg, reg1, reg2); dump_sdma_7322_state()
6842 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); dump_sdma_7322_state()
6847 reg, reg1, reg2); dump_sdma_7322_state()
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_drv.h1918 #define CP_PACKET1( reg0, reg1 ) \
1919 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
H A Devergreen.c4294 * dw0: (reg2 << 16) | reg1 sumo_rlc_init()
4295 * dw1: reg1 save space sumo_rlc_init()
/linux-4.4.14/drivers/mtd/devices/
H A Dspear_smi.c588 /* restore ctrl reg1 */ spear_mtd_read()
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dniu.c2626 u16 reg1 = addr[2] << 8 | addr[3]; niu_set_primary_mac() local
2631 nw64_mac(XMAC_ADDR1, reg1); niu_set_primary_mac()
2635 nw64_mac(BMAC_ADDR1, reg1); niu_set_primary_mac()
2651 u16 reg1 = addr[2] << 8 | addr[3]; niu_set_alt_mac() local
2659 nw64_mac(XMAC_ALT_ADDR1(index), reg1); niu_set_alt_mac() local
2663 nw64_mac(BMAC_ALT_ADDR1(index), reg1); niu_set_alt_mac() local
/linux-4.4.14/drivers/usb/storage/
H A Dshuttle_usbat.c683 * gets packed in this sequence: reg0, data0, reg1, data1, ..., regN, dataN
/linux-4.4.14/sound/pci/emu10k1/
H A Demu10k1_main.c867 dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg); snd_emu10k1_emu1010_init()
/linux-4.4.14/fs/xfs/
H A Dxfs_log.c3574 * <oph><trans-hdr><start-oph><reg1-oph><reg1><reg2-oph>...<commit-oph> xfs_log_calc_unit_res()

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