Lines Matching refs:reg1
151 .reg1 = WM8776_REG_DACLVOL,
161 .reg1 = WM8776_REG_DACCTRL1,
170 .reg1 = WM8776_REG_DACCTRL1,
177 .reg1 = WM8776_REG_HPLVOL,
188 .reg1 = WM8776_REG_PWRDOWN,
195 .reg1 = WM8776_REG_HPLVOL,
204 .reg1 = WM8776_REG_OUTMUX,
210 .reg1 = WM8776_REG_OUTMUX,
216 .reg1 = WM8776_REG_DACCTRL1,
222 .reg1 = WM8776_REG_PHASESWAP,
231 .reg1 = WM8776_REG_DACCTRL2,
238 .reg1 = WM8776_REG_ADCLVOL,
248 .reg1 = WM8776_REG_ADCMUX,
257 .reg1 = WM8776_REG_ADCMUX,
263 .reg1 = WM8776_REG_ADCMUX,
269 .reg1 = WM8776_REG_ADCMUX,
275 .reg1 = WM8776_REG_ADCMUX,
281 .reg1 = WM8776_REG_ADCMUX,
297 .reg1 = WM8776_REG_ALCCTRL1,
308 .reg1 = WM8776_REG_ALCCTRL3,
319 .reg1 = WM8776_REG_ALCCTRL3,
329 .reg1 = WM8776_REG_LIMITER,
337 .reg1 = WM8776_REG_LIMITER,
347 .reg1 = WM8776_REG_ALCCTRL1,
359 .reg1 = WM8776_REG_ALCCTRL3,
370 .reg1 = WM8776_REG_ALCCTRL3,
378 .reg1 = WM8776_REG_ALCCTRL1,
388 .reg1 = WM8776_REG_LIMITER,
402 .reg1 = WM8776_REG_ALCCTRL2,
409 .reg1 = WM8776_REG_NOISEGATE,
417 .reg1 = WM8776_REG_NOISEGATE,
503 val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; in snd_wm8776_ctl_get()
541 val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; in snd_wm8776_ctl_put()
545 wm->ctl[n].reg1 == wm->ctl[n].reg2) { in snd_wm8776_ctl_put()
549 snd_wm8776_write(wm, wm->ctl[n].reg1, val); in snd_wm8776_ctl_put()
552 wm->ctl[n].reg1 != wm->ctl[n].reg2) { in snd_wm8776_ctl_put()