| /linux-4.4.14/drivers/edac/ |
| H A D | amd64_edac.c | 91 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) f15h_select_dct() argument
95 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); f15h_select_dct()
96 reg &= (pvt->model == 0x30) ? ~3 : ~1; f15h_select_dct()
98 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); f15h_select_dct()
115 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, amd64_read_dct_pci_cfg() argument
118 switch (pvt->fam) { amd64_read_dct_pci_cfg()
131 if (dct_ganging_enabled(pvt)) amd64_read_dct_pci_cfg()
143 dct = (dct && pvt->model == 0x30) ? 3 : dct; amd64_read_dct_pci_cfg()
144 f15h_select_dct(pvt, dct); amd64_read_dct_pci_cfg()
155 return amd64_read_pci_cfg(pvt->F2, offset, val); amd64_read_dct_pci_cfg()
176 static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) __set_scrub_rate() argument
204 if (pvt->fam == 0x15 && pvt->model == 0x60) { __set_scrub_rate()
205 f15h_select_dct(pvt, 0); __set_scrub_rate()
206 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); __set_scrub_rate()
207 f15h_select_dct(pvt, 1); __set_scrub_rate()
208 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); __set_scrub_rate()
210 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); __set_scrub_rate()
221 struct amd64_pvt *pvt = mci->pvt_info; set_scrub_rate() local
224 if (pvt->fam == 0xf) set_scrub_rate()
227 if (pvt->fam == 0x15) { set_scrub_rate()
229 if (pvt->model < 0x10) set_scrub_rate()
230 f15h_select_dct(pvt, 0); set_scrub_rate()
232 if (pvt->model == 0x60) set_scrub_rate()
235 return __set_scrub_rate(pvt, bw, min_scrubrate); set_scrub_rate()
240 struct amd64_pvt *pvt = mci->pvt_info; get_scrub_rate() local
244 if (pvt->fam == 0x15) { get_scrub_rate()
246 if (pvt->model < 0x10) get_scrub_rate()
247 f15h_select_dct(pvt, 0); get_scrub_rate()
249 if (pvt->model == 0x60) get_scrub_rate()
250 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); get_scrub_rate()
252 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); get_scrub_rate()
269 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) base_limit_match() argument
281 return ((addr >= get_dram_base(pvt, nid)) && base_limit_match()
282 (addr <= get_dram_limit(pvt, nid))); base_limit_match()
294 struct amd64_pvt *pvt; find_mc_by_sys_addr() local
302 pvt = mci->pvt_info; find_mc_by_sys_addr()
309 intlv_en = dram_intlv_en(pvt, 0); find_mc_by_sys_addr()
313 if (base_limit_match(pvt, sys_addr, node_id)) find_mc_by_sys_addr()
329 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) find_mc_by_sys_addr()
337 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { find_mc_by_sys_addr()
358 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, get_cs_base_and_mask() argument
364 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { get_cs_base_and_mask()
365 csbase = pvt->csels[dct].csbases[csrow]; get_cs_base_and_mask()
366 csmask = pvt->csels[dct].csmasks[csrow]; get_cs_base_and_mask()
375 } else if (pvt->fam == 0x16 || get_cs_base_and_mask()
376 (pvt->fam == 0x15 && pvt->model >= 0x30)) { get_cs_base_and_mask()
377 csbase = pvt->csels[dct].csbases[csrow]; get_cs_base_and_mask()
378 csmask = pvt->csels[dct].csmasks[csrow >> 1]; get_cs_base_and_mask()
393 csbase = pvt->csels[dct].csbases[csrow]; get_cs_base_and_mask()
394 csmask = pvt->csels[dct].csmasks[csrow >> 1]; get_cs_base_and_mask()
397 if (pvt->fam == 0x15) get_cs_base_and_mask()
414 #define for_each_chip_select(i, dct, pvt) \
415 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
417 #define chip_select_base(i, dct, pvt) \
418 pvt->csels[dct].csbases[i]
420 #define for_each_chip_select_mask(i, dct, pvt) \
421 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
429 struct amd64_pvt *pvt; input_addr_to_csrow() local
433 pvt = mci->pvt_info; input_addr_to_csrow()
435 for_each_chip_select(csrow, 0, pvt) { input_addr_to_csrow()
436 if (!csrow_enabled(csrow, 0, pvt)) input_addr_to_csrow()
439 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); input_addr_to_csrow()
446 pvt->mc_node_id); input_addr_to_csrow()
452 (unsigned long)input_addr, pvt->mc_node_id); input_addr_to_csrow()
476 struct amd64_pvt *pvt = mci->pvt_info; amd64_get_dram_hole_info() local
479 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { amd64_get_dram_hole_info()
481 pvt->ext_model, pvt->mc_node_id); amd64_get_dram_hole_info()
486 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { amd64_get_dram_hole_info()
491 if (!dhar_valid(pvt)) { amd64_get_dram_hole_info()
493 pvt->mc_node_id); amd64_get_dram_hole_info()
515 *hole_base = dhar_base(pvt); amd64_get_dram_hole_info()
518 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) amd64_get_dram_hole_info()
519 : k8_dhar_offset(pvt); amd64_get_dram_hole_info()
522 pvt->mc_node_id, (unsigned long)*hole_base, amd64_get_dram_hole_info()
560 struct amd64_pvt *pvt = mci->pvt_info; sys_addr_to_dram_addr() local
564 dram_base = get_dram_base(pvt, pvt->mc_node_id); sys_addr_to_dram_addr()
616 struct amd64_pvt *pvt; dram_addr_to_input_addr() local
620 pvt = mci->pvt_info; dram_addr_to_input_addr()
626 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); dram_addr_to_input_addr()
688 static unsigned long determine_edac_cap(struct amd64_pvt *pvt) determine_edac_cap() argument
693 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) determine_edac_cap()
697 if (pvt->dclr0 & BIT(bit)) determine_edac_cap()
705 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) debug_dump_dramcfg_low() argument
709 if (pvt->dram_type == MEM_LRDDR3) { debug_dump_dramcfg_low()
710 u32 dcsm = pvt->csels[chan].csmasks[0]; debug_dump_dramcfg_low()
726 if (pvt->fam == 0x10) debug_dump_dramcfg_low()
738 static void dump_misc_regs(struct amd64_pvt *pvt) dump_misc_regs() argument
740 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); dump_misc_regs()
743 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); dump_misc_regs()
746 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", dump_misc_regs()
747 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); dump_misc_regs()
749 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); dump_misc_regs()
751 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); dump_misc_regs()
754 pvt->dhar, dhar_base(pvt), dump_misc_regs()
755 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) dump_misc_regs()
756 : f10_dhar_offset(pvt)); dump_misc_regs()
758 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); dump_misc_regs()
760 debug_display_dimm_sizes(pvt, 0); dump_misc_regs()
763 if (pvt->fam == 0xf) dump_misc_regs()
766 debug_display_dimm_sizes(pvt, 1); dump_misc_regs()
768 amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4")); dump_misc_regs()
771 if (!dct_ganging_enabled(pvt)) dump_misc_regs()
772 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); dump_misc_regs()
778 static void prep_chip_selects(struct amd64_pvt *pvt) prep_chip_selects() argument
780 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { prep_chip_selects()
781 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; prep_chip_selects()
782 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; prep_chip_selects()
783 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { prep_chip_selects()
784 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; prep_chip_selects()
785 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; prep_chip_selects()
787 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; prep_chip_selects()
788 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; prep_chip_selects()
795 static void read_dct_base_mask(struct amd64_pvt *pvt) read_dct_base_mask() argument
799 prep_chip_selects(pvt); read_dct_base_mask()
801 for_each_chip_select(cs, 0, pvt) { read_dct_base_mask()
804 u32 *base0 = &pvt->csels[0].csbases[cs]; read_dct_base_mask()
805 u32 *base1 = &pvt->csels[1].csbases[cs]; read_dct_base_mask()
807 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) read_dct_base_mask()
811 if (pvt->fam == 0xf) read_dct_base_mask()
814 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) read_dct_base_mask()
816 cs, *base1, (pvt->fam == 0x10) ? reg1 read_dct_base_mask()
820 for_each_chip_select_mask(cs, 0, pvt) { read_dct_base_mask()
823 u32 *mask0 = &pvt->csels[0].csmasks[cs]; read_dct_base_mask()
824 u32 *mask1 = &pvt->csels[1].csmasks[cs]; read_dct_base_mask()
826 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) read_dct_base_mask()
830 if (pvt->fam == 0xf) read_dct_base_mask()
833 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) read_dct_base_mask()
835 cs, *mask1, (pvt->fam == 0x10) ? reg1 read_dct_base_mask()
840 static void determine_memory_type(struct amd64_pvt *pvt) determine_memory_type() argument
844 switch (pvt->fam) { determine_memory_type()
846 if (pvt->ext_model >= K8_REV_F) determine_memory_type()
849 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; determine_memory_type()
853 if (pvt->dchr0 & DDR3_MODE) determine_memory_type()
856 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; determine_memory_type()
860 if (pvt->model < 0x60) determine_memory_type()
872 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); determine_memory_type()
873 dcsm = pvt->csels[0].csmasks[0]; determine_memory_type()
876 pvt->dram_type = MEM_DDR4; determine_memory_type()
877 else if (pvt->dclr0 & BIT(16)) determine_memory_type()
878 pvt->dram_type = MEM_DDR3; determine_memory_type()
880 pvt->dram_type = MEM_LRDDR3; determine_memory_type()
882 pvt->dram_type = MEM_RDDR3; determine_memory_type()
890 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); determine_memory_type()
891 pvt->dram_type = MEM_EMPTY; determine_memory_type()
896 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; determine_memory_type()
900 static int k8_early_channel_count(struct amd64_pvt *pvt) k8_early_channel_count() argument
904 if (pvt->ext_model >= K8_REV_F) k8_early_channel_count()
906 flag = pvt->dclr0 & WIDTH_128; k8_early_channel_count()
909 flag = pvt->dclr0 & REVE_WIDTH_128; k8_early_channel_count()
912 pvt->dclr1 = 0; k8_early_channel_count()
918 static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) get_error_address() argument
930 pvt = mci->pvt_info; get_error_address()
932 if (pvt->fam == 0xf) { get_error_address()
942 if (pvt->fam == 0x15) { get_error_address()
951 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); get_error_address()
966 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); get_error_address()
999 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) read_dram_base_limit_regs() argument
1007 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); read_dram_base_limit_regs()
1008 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); read_dram_base_limit_regs()
1010 if (pvt->fam == 0xf) read_dram_base_limit_regs()
1013 if (!dram_rw(pvt, range)) read_dram_base_limit_regs()
1016 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); read_dram_base_limit_regs()
1017 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); read_dram_base_limit_regs()
1020 if (pvt->fam != 0x15) read_dram_base_limit_regs()
1023 nb = node_to_amd_nb(dram_dst_node(pvt, range)); read_dram_base_limit_regs()
1027 if (pvt->model == 0x60) read_dram_base_limit_regs()
1029 else if (pvt->model == 0x30) read_dram_base_limit_regs()
1040 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); read_dram_base_limit_regs()
1043 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; read_dram_base_limit_regs()
1045 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); read_dram_base_limit_regs()
1048 pvt->ranges[range].lim.hi |= llim >> 13; read_dram_base_limit_regs()
1056 struct amd64_pvt *pvt = mci->pvt_info; k8_map_sysaddr_to_csrow() local
1080 if (pvt->nbcfg & NBCFG_CHIPKILL) { k8_map_sysaddr_to_csrow()
1121 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, k8_dbam_to_chip_select() argument
1124 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; k8_dbam_to_chip_select()
1126 if (pvt->ext_model >= K8_REV_F) { k8_dbam_to_chip_select()
1130 else if (pvt->ext_model >= K8_REV_D) { k8_dbam_to_chip_select()
1176 static int f1x_early_channel_count(struct amd64_pvt *pvt) f1x_early_channel_count() argument
1181 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) f1x_early_channel_count()
1200 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); f1x_early_channel_count()
1275 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, f10_dbam_to_chip_select() argument
1278 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; f10_dbam_to_chip_select()
1282 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) f10_dbam_to_chip_select()
1291 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, f15_dbam_to_chip_select() argument
1300 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, f15_m60h_dbam_to_chip_select() argument
1304 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; f15_m60h_dbam_to_chip_select()
1308 if (pvt->dram_type == MEM_DDR4) { f15_m60h_dbam_to_chip_select()
1313 } else if (pvt->dram_type == MEM_LRDDR3) { f15_m60h_dbam_to_chip_select()
1333 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, f16_dbam_to_chip_select() argument
1345 static void read_dram_ctl_register(struct amd64_pvt *pvt) read_dram_ctl_register() argument
1348 if (pvt->fam == 0xf) read_dram_ctl_register()
1351 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { read_dram_ctl_register()
1353 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); read_dram_ctl_register()
1356 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); read_dram_ctl_register()
1358 if (!dct_ganging_enabled(pvt)) read_dram_ctl_register()
1360 (dct_high_range_enabled(pvt) ? "yes" : "no")); read_dram_ctl_register()
1363 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), read_dram_ctl_register()
1364 (dct_memory_cleared(pvt) ? "yes" : "no")); read_dram_ctl_register()
1368 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), read_dram_ctl_register()
1369 dct_sel_interleave_addr(pvt)); read_dram_ctl_register()
1372 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); read_dram_ctl_register()
1379 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, f15_m30h_determine_channel() argument
1393 u8 intlv_addr = dct_sel_interleave_addr(pvt); f15_m30h_determine_channel()
1410 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, f1x_determine_channel() argument
1413 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; f1x_determine_channel()
1415 if (dct_ganging_enabled(pvt)) f1x_determine_channel()
1424 if (dct_interleave_enabled(pvt)) { f1x_determine_channel()
1425 u8 intlv_addr = dct_sel_interleave_addr(pvt); f1x_determine_channel()
1441 if (dct_high_range_enabled(pvt)) f1x_determine_channel()
1448 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, f1x_get_norm_dct_addr() argument
1453 u64 dram_base = get_dram_base(pvt, range); f1x_get_norm_dct_addr()
1454 u64 hole_off = f10_dhar_offset(pvt); f1x_get_norm_dct_addr()
1455 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; f1x_get_norm_dct_addr()
1470 dct_sel_base_addr < dhar_base(pvt)) && f1x_get_norm_dct_addr()
1471 dhar_valid(pvt) && f1x_get_norm_dct_addr()
1486 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) f1x_get_norm_dct_addr()
1499 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) f10_process_possible_spare() argument
1503 if (online_spare_swap_done(pvt, dct) && f10_process_possible_spare()
1504 csrow == online_spare_bad_dramcs(pvt, dct)) { f10_process_possible_spare()
1506 for_each_chip_select(tmp_cs, dct, pvt) { for_each_chip_select()
1507 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { for_each_chip_select()
1527 struct amd64_pvt *pvt; f1x_lookup_addr_in_dct() local
1536 pvt = mci->pvt_info; f1x_lookup_addr_in_dct()
1540 for_each_chip_select(csrow, dct, pvt) { for_each_chip_select()
1541 if (!csrow_enabled(csrow, dct, pvt)) for_each_chip_select()
1544 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); for_each_chip_select()
1555 if (pvt->fam == 0x15 && pvt->model >= 0x30) { for_each_chip_select()
1559 cs_found = f10_process_possible_spare(pvt, dct, csrow); for_each_chip_select()
1573 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) f1x_swap_interleaved_region() argument
1577 if (pvt->fam == 0x10) { f1x_swap_interleaved_region()
1579 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) f1x_swap_interleaved_region()
1583 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); f1x_swap_interleaved_region()
1603 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, f1x_match_to_this_node() argument
1612 u8 node_id = dram_dst_node(pvt, range); f1x_match_to_this_node()
1613 u8 intlv_en = dram_intlv_en(pvt, range); f1x_match_to_this_node()
1614 u32 intlv_sel = dram_intlv_sel(pvt, range); f1x_match_to_this_node()
1617 range, sys_addr, get_dram_limit(pvt, range)); f1x_match_to_this_node()
1619 if (dhar_valid(pvt) && f1x_match_to_this_node()
1620 dhar_base(pvt) <= sys_addr && f1x_match_to_this_node()
1630 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); f1x_match_to_this_node()
1632 dct_sel_base = dct_sel_baseaddr(pvt); f1x_match_to_this_node()
1638 if (dct_high_range_enabled(pvt) && f1x_match_to_this_node()
1639 !dct_ganging_enabled(pvt) && f1x_match_to_this_node()
1643 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); f1x_match_to_this_node()
1645 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, f1x_match_to_this_node()
1654 if (dct_interleave_enabled(pvt) && f1x_match_to_this_node()
1655 !dct_high_range_enabled(pvt) && f1x_match_to_this_node()
1656 !dct_ganging_enabled(pvt)) { f1x_match_to_this_node()
1658 if (dct_sel_interleave_addr(pvt) != 1) { f1x_match_to_this_node()
1659 if (dct_sel_interleave_addr(pvt) == 0x3) f1x_match_to_this_node()
1683 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, f15_m30h_match_to_this_node() argument
1693 u64 dhar_offset = f10_dhar_offset(pvt); f15_m30h_match_to_this_node()
1694 u8 intlv_addr = dct_sel_interleave_addr(pvt); f15_m30h_match_to_this_node()
1695 u8 node_id = dram_dst_node(pvt, range); f15_m30h_match_to_this_node()
1696 u8 intlv_en = dram_intlv_en(pvt, range); f15_m30h_match_to_this_node()
1698 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); f15_m30h_match_to_this_node()
1699 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); f15_m30h_match_to_this_node()
1705 range, sys_addr, get_dram_limit(pvt, range)); f15_m30h_match_to_this_node()
1707 if (!(get_dram_base(pvt, range) <= sys_addr) && f15_m30h_match_to_this_node()
1708 !(get_dram_limit(pvt, range) >= sys_addr)) f15_m30h_match_to_this_node()
1711 if (dhar_valid(pvt) && f15_m30h_match_to_this_node()
1712 dhar_base(pvt) <= sys_addr && f15_m30h_match_to_this_node()
1720 dct_base = (u64) dct_sel_baseaddr(pvt); f15_m30h_match_to_this_node()
1734 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, f15_m30h_match_to_this_node()
1774 amd64_read_pci_cfg(pvt->F1, f15_m30h_match_to_this_node()
1780 f15h_select_dct(pvt, channel); f15_m30h_match_to_this_node()
1789 * pvt->csels[1]. So we need to use '1' here to get correct info. f15_m30h_match_to_this_node()
1802 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, f1x_translate_sysaddr_to_cs() argument
1810 if (!dram_rw(pvt, range)) f1x_translate_sysaddr_to_cs()
1813 if (pvt->fam == 0x15 && pvt->model >= 0x30) f1x_translate_sysaddr_to_cs()
1814 cs_found = f15_m30h_match_to_this_node(pvt, range, f1x_translate_sysaddr_to_cs()
1818 else if ((get_dram_base(pvt, range) <= sys_addr) && f1x_translate_sysaddr_to_cs()
1819 (get_dram_limit(pvt, range) >= sys_addr)) { f1x_translate_sysaddr_to_cs()
1820 cs_found = f1x_match_to_this_node(pvt, range, f1x_translate_sysaddr_to_cs()
1839 struct amd64_pvt *pvt = mci->pvt_info; f1x_map_sysaddr_to_csrow() local
1843 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); f1x_map_sysaddr_to_csrow()
1854 if (dct_ganging_enabled(pvt)) f1x_map_sysaddr_to_csrow()
1862 static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) debug_display_dimm_sizes() argument
1865 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; debug_display_dimm_sizes()
1866 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; debug_display_dimm_sizes()
1868 if (pvt->fam == 0xf) { debug_display_dimm_sizes()
1870 if (pvt->ext_model < K8_REV_F) debug_display_dimm_sizes()
1876 if (pvt->fam == 0x10) { debug_display_dimm_sizes()
1877 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 debug_display_dimm_sizes()
1878 : pvt->dbam0; debug_display_dimm_sizes()
1879 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? debug_display_dimm_sizes()
1880 pvt->csels[1].csbases : debug_display_dimm_sizes()
1881 pvt->csels[0].csbases; debug_display_dimm_sizes()
1883 dbam = pvt->dbam0; debug_display_dimm_sizes()
1884 dcsb = pvt->csels[1].csbases; debug_display_dimm_sizes()
1901 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, debug_display_dimm_sizes()
1907 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, debug_display_dimm_sizes()
2135 struct amd64_pvt *pvt = mci->pvt_info; get_channel_from_ecc_syndrome() local
2138 if (pvt->ecc_sym_sz == 8) get_channel_from_ecc_syndrome()
2141 pvt->ecc_sym_sz); get_channel_from_ecc_syndrome()
2142 else if (pvt->ecc_sym_sz == 4) get_channel_from_ecc_syndrome()
2145 pvt->ecc_sym_sz); get_channel_from_ecc_syndrome()
2147 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); get_channel_from_ecc_syndrome()
2151 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); get_channel_from_ecc_syndrome()
2196 struct amd64_pvt *pvt; decode_bus_error() local
2207 pvt = mci->pvt_info; decode_bus_error()
2219 sys_addr = get_error_address(pvt, m); decode_bus_error()
2224 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); decode_bus_error()
2230 * Use pvt->F2 which contains the F2 CPU PCI device to get the related
2233 static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id) reserve_mc_sibling_devs() argument
2236 pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2); reserve_mc_sibling_devs()
2237 if (!pvt->F1) { reserve_mc_sibling_devs()
2245 pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2); reserve_mc_sibling_devs()
2246 if (!pvt->F3) { reserve_mc_sibling_devs()
2247 pci_dev_put(pvt->F1); reserve_mc_sibling_devs()
2248 pvt->F1 = NULL; reserve_mc_sibling_devs()
2256 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); reserve_mc_sibling_devs()
2257 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); reserve_mc_sibling_devs()
2258 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); reserve_mc_sibling_devs()
2263 static void free_mc_sibling_devs(struct amd64_pvt *pvt) free_mc_sibling_devs() argument
2265 pci_dev_put(pvt->F1); free_mc_sibling_devs()
2266 pci_dev_put(pvt->F3); free_mc_sibling_devs()
2273 static void read_mc_regs(struct amd64_pvt *pvt) read_mc_regs() argument
2283 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); read_mc_regs()
2284 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); read_mc_regs()
2289 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); read_mc_regs()
2290 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); read_mc_regs()
2294 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); read_mc_regs()
2296 read_dram_ctl_register(pvt); read_mc_regs()
2302 read_dram_base_limit_regs(pvt, range); read_mc_regs()
2304 rw = dram_rw(pvt, range); read_mc_regs()
2310 get_dram_base(pvt, range), read_mc_regs()
2311 get_dram_limit(pvt, range)); read_mc_regs()
2314 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", read_mc_regs()
2317 dram_intlv_sel(pvt, range), read_mc_regs()
2318 dram_dst_node(pvt, range)); read_mc_regs()
2321 read_dct_base_mask(pvt); read_mc_regs()
2323 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); read_mc_regs()
2324 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); read_mc_regs()
2326 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); read_mc_regs()
2328 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); read_mc_regs()
2329 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); read_mc_regs()
2331 if (!dct_ganging_enabled(pvt)) { read_mc_regs()
2332 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); read_mc_regs()
2333 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); read_mc_regs()
2336 pvt->ecc_sym_sz = 4; read_mc_regs()
2337 determine_memory_type(pvt); read_mc_regs()
2338 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); read_mc_regs()
2340 if (pvt->fam >= 0x10) { read_mc_regs()
2341 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); read_mc_regs()
2343 if (pvt->fam != 0x16) read_mc_regs()
2344 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); read_mc_regs()
2347 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) read_mc_regs()
2348 pvt->ecc_sym_sz = 8; read_mc_regs()
2350 dump_misc_regs(pvt); read_mc_regs()
2387 static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) get_csrow_nr_pages() argument
2390 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; get_csrow_nr_pages()
2402 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, (csrow_nr / 2)) get_csrow_nr_pages()
2418 struct amd64_pvt *pvt = mci->pvt_info; init_csrows() local
2426 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); init_csrows()
2428 pvt->nbcfg = val; init_csrows()
2431 pvt->mc_node_id, val, init_csrows()
2437 for_each_chip_select(i, 0, pvt) { init_csrows()
2438 bool row_dct0 = !!csrow_enabled(i, 0, pvt); init_csrows()
2441 if (pvt->fam != 0xf) init_csrows()
2442 row_dct1 = !!csrow_enabled(i, 1, pvt); init_csrows()
2451 pvt->mc_node_id, i); init_csrows()
2454 nr_pages = get_csrow_nr_pages(pvt, 0, i); init_csrows()
2459 if (pvt->fam != 0xf && row_dct1) { init_csrows()
2460 int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i); init_csrows()
2471 if (pvt->nbcfg & NBCFG_ECC_ENABLE) init_csrows()
2472 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) ? init_csrows()
2477 for (j = 0; j < pvt->channel_count; j++) { init_csrows()
2479 dimm->mtype = pvt->dram_type; init_csrows()
2687 struct amd64_pvt *pvt = mci->pvt_info; setup_mci_misc_attrs() local
2692 if (pvt->nbcap & NBCAP_SECDED) setup_mci_misc_attrs()
2695 if (pvt->nbcap & NBCAP_CHIPKILL) setup_mci_misc_attrs()
2698 mci->edac_cap = determine_edac_cap(pvt); setup_mci_misc_attrs()
2702 mci->dev_name = pci_name(pvt->F2); setup_mci_misc_attrs()
2713 static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) per_family_init() argument
2717 pvt->ext_model = boot_cpu_data.x86_model >> 4; per_family_init()
2718 pvt->stepping = boot_cpu_data.x86_mask; per_family_init()
2719 pvt->model = boot_cpu_data.x86_model; per_family_init()
2720 pvt->fam = boot_cpu_data.x86; per_family_init()
2722 switch (pvt->fam) { per_family_init()
2725 pvt->ops = &family_types[K8_CPUS].ops; per_family_init()
2730 pvt->ops = &family_types[F10_CPUS].ops; per_family_init()
2734 if (pvt->model == 0x30) { per_family_init()
2736 pvt->ops = &family_types[F15_M30H_CPUS].ops; per_family_init()
2738 } else if (pvt->model == 0x60) { per_family_init()
2740 pvt->ops = &family_types[F15_M60H_CPUS].ops; per_family_init()
2745 pvt->ops = &family_types[F15_CPUS].ops; per_family_init()
2749 if (pvt->model == 0x30) { per_family_init()
2751 pvt->ops = &family_types[F16_M30H_CPUS].ops; per_family_init()
2755 pvt->ops = &family_types[F16_CPUS].ops; per_family_init()
2764 (pvt->fam == 0xf ? per_family_init()
2765 (pvt->ext_model >= K8_REV_F ? "revF or later " per_family_init()
2767 : ""), pvt->mc_node_id); per_family_init()
2783 struct amd64_pvt *pvt = NULL; init_one_instance() local
2791 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); init_one_instance()
2792 if (!pvt) init_one_instance()
2795 pvt->mc_node_id = nid; init_one_instance()
2796 pvt->F2 = F2; init_one_instance()
2799 fam_type = per_family_init(pvt); init_one_instance()
2804 err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id); init_one_instance()
2808 read_mc_regs(pvt); init_one_instance()
2816 pvt->channel_count = pvt->ops->early_channel_count(pvt); init_one_instance()
2817 if (pvt->channel_count < 0) init_one_instance()
2822 layers[0].size = pvt->csels[0].b_cnt; init_one_instance()
2838 mci->pvt_info = pvt; init_one_instance()
2839 mci->pdev = &pvt->F2->dev; init_one_instance()
2866 free_mc_sibling_devs(pvt); init_one_instance()
2869 kfree(pvt); init_one_instance()
2927 struct amd64_pvt *pvt; remove_one_instance() local
2940 pvt = mci->pvt_info; remove_one_instance()
2944 free_mc_sibling_devs(pvt); remove_one_instance()
2956 kfree(pvt); remove_one_instance()
2988 struct amd64_pvt *pvt; setup_pci_device() local
2997 pvt = mci->pvt_info; setup_pci_device()
2998 pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR); setup_pci_device()
|
| H A D | sb_edac.c | 273 u64 (*get_tolm)(struct sbridge_pvt *pvt);
274 u64 (*get_tohm)(struct sbridge_pvt *pvt);
281 u8 (*get_node_id)(struct sbridge_pvt *pvt);
282 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
283 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
681 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) sbridge_get_tolm() argument
686 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); sbridge_get_tolm()
690 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) sbridge_get_tohm() argument
694 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); sbridge_get_tohm()
698 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) ibridge_get_tolm() argument
702 pci_read_config_dword(pvt->pci_br1, TOLM, ®); ibridge_get_tolm()
707 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) ibridge_get_tohm() argument
711 pci_read_config_dword(pvt->pci_br1, TOHM, ®); ibridge_get_tohm()
721 static enum mem_type get_memory_type(struct sbridge_pvt *pvt) get_memory_type() argument
726 if (pvt->pci_ddrio) { get_memory_type()
727 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, get_memory_type()
740 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) haswell_get_memory_type() argument
746 if (!pvt->pci_ddrio) haswell_get_memory_type()
749 pci_read_config_dword(pvt->pci_ddrio, haswell_get_memory_type()
755 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); haswell_get_memory_type()
772 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) sbridge_get_width() argument
800 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) ibridge_get_width() argument
809 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) broadwell_get_width() argument
815 static u8 get_node_id(struct sbridge_pvt *pvt) get_node_id() argument
818 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); get_node_id()
822 static u8 haswell_get_node_id(struct sbridge_pvt *pvt) haswell_get_node_id() argument
826 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); haswell_get_node_id()
830 static u64 haswell_get_tolm(struct sbridge_pvt *pvt) haswell_get_tolm() argument
834 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); haswell_get_tolm()
838 static u64 haswell_get_tohm(struct sbridge_pvt *pvt) haswell_get_tohm() argument
843 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); haswell_get_tohm()
845 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); haswell_get_tohm()
930 struct sbridge_pvt *pvt = mci->pvt_info; get_dimm_config() local
938 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) get_dimm_config()
939 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); get_dimm_config()
941 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); get_dimm_config()
943 pvt->sbridge_dev->source_id = SOURCE_ID(reg); get_dimm_config()
945 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); get_dimm_config()
947 pvt->sbridge_dev->mc, get_dimm_config()
948 pvt->sbridge_dev->node_id, get_dimm_config()
949 pvt->sbridge_dev->source_id); get_dimm_config()
951 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); get_dimm_config()
954 pvt->is_mirrored = true; get_dimm_config()
957 pvt->is_mirrored = false; get_dimm_config()
960 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); get_dimm_config()
961 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { get_dimm_config()
964 pvt->is_lockstep = true; get_dimm_config()
968 pvt->is_lockstep = false; get_dimm_config()
970 if (IS_CLOSE_PG(pvt->info.mcmtr)) { get_dimm_config()
972 pvt->is_close_pg = true; get_dimm_config()
975 pvt->is_close_pg = false; get_dimm_config()
978 mtype = pvt->info.get_memory_type(pvt); get_dimm_config()
994 if (!pvt->pci_tad[i]) get_dimm_config()
999 pci_read_config_dword(pvt->pci_tad[i], get_dimm_config()
1003 pvt->channel[i].dimms++; get_dimm_config()
1005 ranks = numrank(pvt->info.type, mtr); get_dimm_config()
1013 pvt->sbridge_dev->mc, i/4, i%4, j, get_dimm_config()
1019 dimm->dtype = pvt->info.get_width(pvt, mtr); get_dimm_config()
1024 pvt->sbridge_dev->source_id, i/4, i%4, j); get_dimm_config()
1034 struct sbridge_pvt *pvt = mci->pvt_info; get_memory_layout() local
1046 pvt->tolm = pvt->info.get_tolm(pvt); get_memory_layout()
1047 tmp_mb = (1 + pvt->tolm) >> 20; get_memory_layout()
1051 gb, (mb*1000)/1024, (u64)pvt->tolm); get_memory_layout()
1054 pvt->tohm = pvt->info.get_tohm(pvt); get_memory_layout()
1055 tmp_mb = (1 + pvt->tohm) >> 20; get_memory_layout()
1059 gb, (mb*1000)/1024, (u64)pvt->tohm); get_memory_layout()
1068 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { get_memory_layout()
1070 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], get_memory_layout()
1091 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], get_memory_layout()
1093 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); get_memory_layout()
1095 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); get_memory_layout()
1109 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], get_memory_layout()
1134 if (!pvt->channel[i].dimms) get_memory_layout()
1137 pci_read_config_dword(pvt->pci_tad[i], get_memory_layout()
1154 if (!pvt->channel[i].dimms) get_memory_layout()
1157 pci_read_config_dword(pvt->pci_tad[i], get_memory_layout()
1164 tmp_mb = pvt->info.rir_limit(reg) >> 20; get_memory_layout()
1175 pci_read_config_dword(pvt->pci_tad[i], get_memory_layout()
1211 struct sbridge_pvt *pvt = mci->pvt_info; get_memory_error_data() local
1216 unsigned sad_interleave[pvt->info.max_interleave]; get_memory_error_data()
1232 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { get_memory_error_data()
1236 if (addr >= (u64)pvt->tohm) { get_memory_error_data()
1244 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { get_memory_error_data()
1245 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], get_memory_error_data()
1260 if (n_sads == pvt->info.max_sad) { get_memory_error_data()
1268 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], get_memory_error_data()
1271 if (pvt->info.type == SANDY_BRIDGE) { get_memory_error_data()
1272 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); get_memory_error_data()
1274 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); get_memory_error_data()
1282 pvt->sbridge_dev->mc, get_memory_error_data()
1311 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { get_memory_error_data()
1328 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); get_memory_error_data()
1336 pci_read_config_dword(pvt->pci_ha0, get_memory_error_data()
1346 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); get_memory_error_data()
1368 pvt = mci->pvt_info; get_memory_error_data()
1374 if (pvt->info.type == SANDY_BRIDGE) get_memory_error_data()
1375 pci_ha = pvt->pci_ha0; get_memory_error_data()
1378 pci_ha = pvt->pci_ha1; get_memory_error_data()
1380 pci_ha = pvt->pci_ha0; get_memory_error_data()
1429 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], get_memory_error_data()
1433 if (pvt->is_mirrored) { get_memory_error_data()
1447 if (pvt->is_lockstep) get_memory_error_data()
1482 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], get_memory_error_data()
1489 limit = pvt->info.rir_limit(reg); get_memory_error_data()
1506 if (pvt->is_close_pg) get_memory_error_data()
1512 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], get_memory_error_data()
1683 struct sbridge_pvt *pvt = mci->pvt_info; sbridge_mci_bind_devs() local
1695 pvt->pci_sad0 = pdev; sbridge_mci_bind_devs()
1698 pvt->pci_sad1 = pdev; sbridge_mci_bind_devs()
1701 pvt->pci_br0 = pdev; sbridge_mci_bind_devs()
1704 pvt->pci_ha0 = pdev; sbridge_mci_bind_devs()
1707 pvt->pci_ta = pdev; sbridge_mci_bind_devs()
1710 pvt->pci_ras = pdev; sbridge_mci_bind_devs()
1718 pvt->pci_tad[id] = pdev; sbridge_mci_bind_devs()
1723 pvt->pci_ddrio = pdev; sbridge_mci_bind_devs()
1736 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || sbridge_mci_bind_devs()
1737 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) sbridge_mci_bind_devs()
1757 struct sbridge_pvt *pvt = mci->pvt_info; ibridge_mci_bind_devs() local
1769 pvt->pci_ha0 = pdev; ibridge_mci_bind_devs()
1772 pvt->pci_ta = pdev; ibridge_mci_bind_devs()
1774 pvt->pci_ras = pdev; ibridge_mci_bind_devs()
1782 pvt->pci_tad[id] = pdev; ibridge_mci_bind_devs()
1787 pvt->pci_ddrio = pdev; ibridge_mci_bind_devs()
1790 pvt->pci_ddrio = pdev; ibridge_mci_bind_devs()
1793 pvt->pci_sad0 = pdev; ibridge_mci_bind_devs()
1796 pvt->pci_br0 = pdev; ibridge_mci_bind_devs()
1799 pvt->pci_br1 = pdev; ibridge_mci_bind_devs()
1802 pvt->pci_ha1 = pdev; ibridge_mci_bind_devs()
1810 pvt->pci_tad[id] = pdev; ibridge_mci_bind_devs()
1825 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 || ibridge_mci_bind_devs()
1826 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras || ibridge_mci_bind_devs()
1827 !pvt->pci_ta) ibridge_mci_bind_devs()
1850 struct sbridge_pvt *pvt = mci->pvt_info; haswell_mci_bind_devs() local
1856 if (pvt->info.pci_vtd == NULL) haswell_mci_bind_devs()
1858 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, haswell_mci_bind_devs()
1869 pvt->pci_sad0 = pdev; haswell_mci_bind_devs()
1872 pvt->pci_sad1 = pdev; haswell_mci_bind_devs()
1875 pvt->pci_ha0 = pdev; haswell_mci_bind_devs()
1878 pvt->pci_ta = pdev; haswell_mci_bind_devs()
1881 pvt->pci_ras = pdev; haswell_mci_bind_devs()
1890 pvt->pci_tad[id] = pdev; haswell_mci_bind_devs()
1901 pvt->pci_tad[id] = pdev; haswell_mci_bind_devs()
1909 if (!pvt->pci_ddrio) haswell_mci_bind_devs()
1910 pvt->pci_ddrio = pdev; haswell_mci_bind_devs()
1913 pvt->pci_ha1 = pdev; haswell_mci_bind_devs()
1916 pvt->pci_ha1_ta = pdev; haswell_mci_bind_devs()
1929 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || haswell_mci_bind_devs()
1930 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) haswell_mci_bind_devs()
1947 struct sbridge_pvt *pvt = mci->pvt_info; broadwell_mci_bind_devs() local
1953 if (pvt->info.pci_vtd == NULL) broadwell_mci_bind_devs()
1955 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, broadwell_mci_bind_devs()
1966 pvt->pci_sad0 = pdev; broadwell_mci_bind_devs()
1969 pvt->pci_sad1 = pdev; broadwell_mci_bind_devs()
1972 pvt->pci_ha0 = pdev; broadwell_mci_bind_devs()
1975 pvt->pci_ta = pdev; broadwell_mci_bind_devs()
1978 pvt->pci_ras = pdev; broadwell_mci_bind_devs()
1986 pvt->pci_tad[id] = pdev; broadwell_mci_bind_devs()
1996 pvt->pci_tad[id] = pdev; broadwell_mci_bind_devs()
2001 pvt->pci_ddrio = pdev; broadwell_mci_bind_devs()
2004 pvt->pci_ha1 = pdev; broadwell_mci_bind_devs()
2007 pvt->pci_ha1_ta = pdev; broadwell_mci_bind_devs()
2020 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || broadwell_mci_bind_devs()
2021 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) broadwell_mci_bind_devs()
2049 struct sbridge_pvt *pvt = mci->pvt_info; sbridge_mce_output_error() local
2066 if (pvt->info.type != SANDY_BRIDGE) sbridge_mce_output_error()
2134 pvt = mci->pvt_info; sbridge_mce_output_error()
2152 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg) sbridge_mce_output_error()
2191 struct sbridge_pvt *pvt = mci->pvt_info; sbridge_check_error() local
2202 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) sbridge_check_error()
2207 m = pvt->mce_outentry; sbridge_check_error()
2208 if (pvt->mce_in + count > MCE_LOG_LEN) { sbridge_check_error()
2209 unsigned l = MCE_LOG_LEN - pvt->mce_in; sbridge_check_error()
2211 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); sbridge_check_error()
2213 pvt->mce_in = 0; sbridge_check_error()
2217 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); sbridge_check_error()
2219 pvt->mce_in += count; sbridge_check_error()
2222 if (pvt->mce_overrun) { sbridge_check_error()
2224 pvt->mce_overrun); sbridge_check_error()
2226 pvt->mce_overrun = 0; sbridge_check_error()
2233 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); sbridge_check_error()
2249 struct sbridge_pvt *pvt; sbridge_mce_check_error() local
2258 pvt = mci->pvt_info; sbridge_mce_check_error()
2288 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { sbridge_mce_check_error()
2290 pvt->mce_overrun++; sbridge_mce_check_error()
2295 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); sbridge_mce_check_error()
2297 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; sbridge_mce_check_error()
2318 struct sbridge_pvt *pvt; sbridge_unregister_mci() local
2327 pvt = mci->pvt_info; sbridge_unregister_mci()
2345 struct sbridge_pvt *pvt; sbridge_register_mci() local
2362 sizeof(*pvt)); sbridge_register_mci()
2370 pvt = mci->pvt_info; sbridge_register_mci()
2371 memset(pvt, 0, sizeof(*pvt)); sbridge_register_mci()
2374 pvt->sbridge_dev = sbridge_dev; sbridge_register_mci()
2388 pvt->info.type = type; sbridge_register_mci()
2391 pvt->info.rankcfgr = IB_RANK_CFG_A; sbridge_register_mci()
2392 pvt->info.get_tolm = ibridge_get_tolm; sbridge_register_mci()
2393 pvt->info.get_tohm = ibridge_get_tohm; sbridge_register_mci()
2394 pvt->info.dram_rule = ibridge_dram_rule; sbridge_register_mci()
2395 pvt->info.get_memory_type = get_memory_type; sbridge_register_mci()
2396 pvt->info.get_node_id = get_node_id; sbridge_register_mci()
2397 pvt->info.rir_limit = rir_limit; sbridge_register_mci()
2398 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); sbridge_register_mci()
2399 pvt->info.interleave_list = ibridge_interleave_list; sbridge_register_mci()
2400 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); sbridge_register_mci()
2401 pvt->info.interleave_pkg = ibridge_interleave_pkg; sbridge_register_mci()
2402 pvt->info.get_width = ibridge_get_width; sbridge_register_mci()
2411 pvt->info.rankcfgr = SB_RANK_CFG_A; sbridge_register_mci()
2412 pvt->info.get_tolm = sbridge_get_tolm; sbridge_register_mci()
2413 pvt->info.get_tohm = sbridge_get_tohm; sbridge_register_mci()
2414 pvt->info.dram_rule = sbridge_dram_rule; sbridge_register_mci()
2415 pvt->info.get_memory_type = get_memory_type; sbridge_register_mci()
2416 pvt->info.get_node_id = get_node_id; sbridge_register_mci()
2417 pvt->info.rir_limit = rir_limit; sbridge_register_mci()
2418 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); sbridge_register_mci()
2419 pvt->info.interleave_list = sbridge_interleave_list; sbridge_register_mci()
2420 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); sbridge_register_mci()
2421 pvt->info.interleave_pkg = sbridge_interleave_pkg; sbridge_register_mci()
2422 pvt->info.get_width = sbridge_get_width; sbridge_register_mci()
2432 pvt->info.get_tolm = haswell_get_tolm; sbridge_register_mci()
2433 pvt->info.get_tohm = haswell_get_tohm; sbridge_register_mci()
2434 pvt->info.dram_rule = ibridge_dram_rule; sbridge_register_mci()
2435 pvt->info.get_memory_type = haswell_get_memory_type; sbridge_register_mci()
2436 pvt->info.get_node_id = haswell_get_node_id; sbridge_register_mci()
2437 pvt->info.rir_limit = haswell_rir_limit; sbridge_register_mci()
2438 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); sbridge_register_mci()
2439 pvt->info.interleave_list = ibridge_interleave_list; sbridge_register_mci()
2440 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); sbridge_register_mci()
2441 pvt->info.interleave_pkg = ibridge_interleave_pkg; sbridge_register_mci()
2442 pvt->info.get_width = ibridge_get_width; sbridge_register_mci()
2452 pvt->info.get_tolm = haswell_get_tolm; sbridge_register_mci()
2453 pvt->info.get_tohm = haswell_get_tohm; sbridge_register_mci()
2454 pvt->info.dram_rule = ibridge_dram_rule; sbridge_register_mci()
2455 pvt->info.get_memory_type = haswell_get_memory_type; sbridge_register_mci()
2456 pvt->info.get_node_id = haswell_get_node_id; sbridge_register_mci()
2457 pvt->info.rir_limit = haswell_rir_limit; sbridge_register_mci()
2458 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); sbridge_register_mci()
2459 pvt->info.interleave_list = ibridge_interleave_list; sbridge_register_mci()
2460 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); sbridge_register_mci()
2461 pvt->info.interleave_pkg = ibridge_interleave_pkg; sbridge_register_mci()
2462 pvt->info.get_width = broadwell_get_width; sbridge_register_mci()
|
| H A D | i7core_edac.c | 408 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
409 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
412 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
413 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
501 struct i7core_pvt *pvt = mci->pvt_info; get_dimm_config() local
509 pdev = pvt->pci_mcr[0]; get_dimm_config()
514 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); get_dimm_config()
515 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); get_dimm_config()
516 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); get_dimm_config()
517 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); get_dimm_config()
520 pvt->i7core_dev->socket, pvt->info.mc_control, get_dimm_config()
521 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map); get_dimm_config()
523 if (ECC_ENABLED(pvt)) { get_dimm_config()
524 edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); get_dimm_config()
525 if (ECCx8(pvt)) get_dimm_config()
536 numdimms(pvt->info.max_dod), get_dimm_config()
537 numrank(pvt->info.max_dod >> 2), get_dimm_config()
538 numbank(pvt->info.max_dod >> 4), get_dimm_config()
539 numrow(pvt->info.max_dod >> 6), get_dimm_config()
540 numcol(pvt->info.max_dod >> 9)); get_dimm_config()
545 if (!pvt->pci_ch[i][0]) get_dimm_config()
548 if (!CH_ACTIVE(pvt, i)) { get_dimm_config()
552 if (CH_DISABLED(pvt, i)) { get_dimm_config()
558 pci_read_config_dword(pvt->pci_ch[i][0], get_dimm_config()
563 pvt->channel[i].is_3dimms_present = true; get_dimm_config()
566 pvt->channel[i].is_single_4rank = true; get_dimm_config()
569 pvt->channel[i].has_4rank = true; get_dimm_config()
577 pci_read_config_dword(pvt->pci_ch[i][1], get_dimm_config()
579 pci_read_config_dword(pvt->pci_ch[i][1], get_dimm_config()
581 pci_read_config_dword(pvt->pci_ch[i][1], get_dimm_config()
586 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), get_dimm_config()
588 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "", get_dimm_config()
589 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "", get_dimm_config()
590 pvt->channel[i].has_4rank ? "HAS_4R " : "", get_dimm_config()
635 pvt->i7core_dev->socket, i, j); get_dimm_config()
675 struct i7core_pvt *pvt = mci->pvt_info; disable_inject() local
677 pvt->inject.enable = 0; disable_inject()
679 if (!pvt->pci_ch[pvt->inject.channel][0]) disable_inject()
682 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], disable_inject()
700 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_section_store() local
704 if (pvt->inject.enable) i7core_inject_section_store()
711 pvt->inject.section = (u32) value; i7core_inject_section_store()
720 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_section_show() local
721 return sprintf(data, "0x%08x\n", pvt->inject.section); i7core_inject_section_show()
737 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_type_store() local
741 if (pvt->inject.enable) i7core_inject_type_store()
748 pvt->inject.type = (u32) value; i7core_inject_type_store()
757 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_type_show() local
759 return sprintf(data, "0x%08x\n", pvt->inject.type); i7core_inject_type_show()
777 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_eccmask_store() local
781 if (pvt->inject.enable) i7core_inject_eccmask_store()
788 pvt->inject.eccmask = (u32) value; i7core_inject_eccmask_store()
797 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_eccmask_show() local
799 return sprintf(data, "0x%08x\n", pvt->inject.eccmask); i7core_inject_eccmask_show()
820 struct i7core_pvt *pvt; \
825 pvt = mci->pvt_info; \
827 if (pvt->inject.enable) \
838 pvt->inject.param = value; \
849 struct i7core_pvt *pvt; \
851 pvt = mci->pvt_info; \
852 edac_dbg(1, "pvt=%p\n", pvt); \
853 if (pvt->inject.param < 0) \
856 return sprintf(data, "%d\n", pvt->inject.param);\
928 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_enable_store() local
934 if (!pvt->pci_ch[pvt->inject.channel][0]) i7core_inject_enable_store()
942 pvt->inject.enable = 1; i7core_inject_enable_store()
948 /* Sets pvt->inject.dimm mask */ i7core_inject_enable_store()
949 if (pvt->inject.dimm < 0) i7core_inject_enable_store()
952 if (pvt->channel[pvt->inject.channel].dimms > 2) i7core_inject_enable_store()
953 mask |= (pvt->inject.dimm & 0x3LL) << 35; i7core_inject_enable_store()
955 mask |= (pvt->inject.dimm & 0x1LL) << 36; i7core_inject_enable_store()
958 /* Sets pvt->inject.rank mask */ i7core_inject_enable_store()
959 if (pvt->inject.rank < 0) i7core_inject_enable_store()
962 if (pvt->channel[pvt->inject.channel].dimms > 2) i7core_inject_enable_store()
963 mask |= (pvt->inject.rank & 0x1LL) << 34; i7core_inject_enable_store()
965 mask |= (pvt->inject.rank & 0x3LL) << 34; i7core_inject_enable_store()
968 /* Sets pvt->inject.bank mask */ i7core_inject_enable_store()
969 if (pvt->inject.bank < 0) i7core_inject_enable_store()
972 mask |= (pvt->inject.bank & 0x15LL) << 30; i7core_inject_enable_store()
974 /* Sets pvt->inject.page mask */ i7core_inject_enable_store()
975 if (pvt->inject.page < 0) i7core_inject_enable_store()
978 mask |= (pvt->inject.page & 0xffff) << 14; i7core_inject_enable_store()
980 /* Sets pvt->inject.column mask */ i7core_inject_enable_store()
981 if (pvt->inject.col < 0) i7core_inject_enable_store()
984 mask |= (pvt->inject.col & 0x3fff); i7core_inject_enable_store()
993 injectmask = (pvt->inject.type & 1) | i7core_inject_enable_store()
994 (pvt->inject.section & 0x3) << 1 | i7core_inject_enable_store()
995 (pvt->inject.type & 0x6) << (3 - 1); i7core_inject_enable_store()
998 pci_write_config_dword(pvt->pci_noncore, i7core_inject_enable_store()
1001 write_and_test(pvt->pci_ch[pvt->inject.channel][0], i7core_inject_enable_store()
1003 write_and_test(pvt->pci_ch[pvt->inject.channel][0], i7core_inject_enable_store()
1006 write_and_test(pvt->pci_ch[pvt->inject.channel][0], i7core_inject_enable_store()
1007 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); i7core_inject_enable_store()
1009 write_and_test(pvt->pci_ch[pvt->inject.channel][0], i7core_inject_enable_store()
1017 pci_write_config_dword(pvt->pci_noncore, i7core_inject_enable_store()
1021 mask, pvt->inject.eccmask, injectmask); i7core_inject_enable_store()
1032 struct i7core_pvt *pvt = mci->pvt_info; i7core_inject_enable_show() local
1035 if (!pvt->pci_ch[pvt->inject.channel][0]) i7core_inject_enable_show()
1038 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], i7core_inject_enable_show()
1044 pvt->inject.enable = 1; i7core_inject_enable_show()
1046 return sprintf(data, "%d\n", pvt->inject.enable); i7core_inject_enable_show()
1056 struct i7core_pvt *pvt = mci->pvt_info; \
1059 if (!pvt->ce_count_available || (pvt->is_registered)) \
1062 pvt->udimm_ce_count[param]); \
1172 struct i7core_pvt *pvt = mci->pvt_info; i7core_create_sysfs_devices() local
1175 pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL); i7core_create_sysfs_devices()
1176 if (!pvt->addrmatch_dev) i7core_create_sysfs_devices()
1179 pvt->addrmatch_dev->type = &addrmatch_type; i7core_create_sysfs_devices()
1180 pvt->addrmatch_dev->bus = mci->dev.bus; i7core_create_sysfs_devices()
1181 device_initialize(pvt->addrmatch_dev); i7core_create_sysfs_devices()
1182 pvt->addrmatch_dev->parent = &mci->dev; i7core_create_sysfs_devices()
1183 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch"); i7core_create_sysfs_devices()
1184 dev_set_drvdata(pvt->addrmatch_dev, mci); i7core_create_sysfs_devices()
1186 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev)); i7core_create_sysfs_devices()
1188 rc = device_add(pvt->addrmatch_dev); i7core_create_sysfs_devices()
1192 if (!pvt->is_registered) { i7core_create_sysfs_devices()
1193 pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev), i7core_create_sysfs_devices()
1195 if (!pvt->chancounts_dev) { i7core_create_sysfs_devices()
1196 put_device(pvt->addrmatch_dev); i7core_create_sysfs_devices()
1197 device_del(pvt->addrmatch_dev); i7core_create_sysfs_devices()
1201 pvt->chancounts_dev->type = &all_channel_counts_type; i7core_create_sysfs_devices()
1202 pvt->chancounts_dev->bus = mci->dev.bus; i7core_create_sysfs_devices()
1203 device_initialize(pvt->chancounts_dev); i7core_create_sysfs_devices()
1204 pvt->chancounts_dev->parent = &mci->dev; i7core_create_sysfs_devices()
1205 dev_set_name(pvt->chancounts_dev, "all_channel_counts"); i7core_create_sysfs_devices()
1206 dev_set_drvdata(pvt->chancounts_dev, mci); i7core_create_sysfs_devices()
1208 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev)); i7core_create_sysfs_devices()
1210 rc = device_add(pvt->chancounts_dev); i7core_create_sysfs_devices()
1219 struct i7core_pvt *pvt = mci->pvt_info; i7core_delete_sysfs_devices() local
1223 if (!pvt->is_registered) { i7core_delete_sysfs_devices()
1224 put_device(pvt->chancounts_dev); i7core_delete_sysfs_devices()
1225 device_del(pvt->chancounts_dev); i7core_delete_sysfs_devices()
1227 put_device(pvt->addrmatch_dev); i7core_delete_sysfs_devices()
1228 device_del(pvt->addrmatch_dev); i7core_delete_sysfs_devices()
1460 struct i7core_pvt *pvt = mci->pvt_info; mci_bind_devs() local
1465 pvt->is_registered = false; mci_bind_devs()
1466 pvt->enable_scrub = false; mci_bind_devs()
1477 pvt->pci_mcr[func] = pdev; mci_bind_devs()
1481 pvt->pci_ch[slot - 4][func] = pdev; mci_bind_devs()
1483 pvt->pci_noncore = pdev; mci_bind_devs()
1489 pvt->enable_scrub = false; mci_bind_devs()
1493 pvt->enable_scrub = false; mci_bind_devs()
1497 pvt->enable_scrub = false; mci_bind_devs()
1501 pvt->enable_scrub = true; mci_bind_devs()
1505 pvt->enable_scrub = true; mci_bind_devs()
1509 pvt->enable_scrub = false; mci_bind_devs()
1521 pvt->is_registered = true; mci_bind_devs()
1543 struct i7core_pvt *pvt = mci->pvt_info; i7core_rdimm_update_ce_count() local
1546 if (pvt->ce_count_available) { i7core_rdimm_update_ce_count()
1549 add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; i7core_rdimm_update_ce_count()
1550 add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; i7core_rdimm_update_ce_count()
1551 add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; i7core_rdimm_update_ce_count()
1555 pvt->rdimm_ce_count[chan][2] += add2; i7core_rdimm_update_ce_count()
1559 pvt->rdimm_ce_count[chan][1] += add1; i7core_rdimm_update_ce_count()
1563 pvt->rdimm_ce_count[chan][0] += add0; i7core_rdimm_update_ce_count()
1565 pvt->ce_count_available = 1; i7core_rdimm_update_ce_count()
1568 pvt->rdimm_last_ce_count[chan][2] = new2; i7core_rdimm_update_ce_count()
1569 pvt->rdimm_last_ce_count[chan][1] = new1; i7core_rdimm_update_ce_count()
1570 pvt->rdimm_last_ce_count[chan][0] = new0; i7core_rdimm_update_ce_count()
1589 struct i7core_pvt *pvt = mci->pvt_info; i7core_rdimm_check_mc_ecc_err() local
1594 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, i7core_rdimm_check_mc_ecc_err()
1596 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, i7core_rdimm_check_mc_ecc_err()
1598 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, i7core_rdimm_check_mc_ecc_err()
1600 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, i7core_rdimm_check_mc_ecc_err()
1602 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, i7core_rdimm_check_mc_ecc_err()
1604 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, i7core_rdimm_check_mc_ecc_err()
1610 if (pvt->channel[i].dimms > 2) { i7core_rdimm_check_mc_ecc_err()
1634 struct i7core_pvt *pvt = mci->pvt_info; i7core_udimm_check_mc_ecc_err() local
1638 if (!pvt->pci_mcr[4]) { i7core_udimm_check_mc_ecc_err()
1644 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); i7core_udimm_check_mc_ecc_err()
1645 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); i7core_udimm_check_mc_ecc_err()
1653 if (pvt->ce_count_available) { i7core_udimm_check_mc_ecc_err()
1657 add2 = new2 - pvt->udimm_last_ce_count[2]; i7core_udimm_check_mc_ecc_err()
1658 add1 = new1 - pvt->udimm_last_ce_count[1]; i7core_udimm_check_mc_ecc_err()
1659 add0 = new0 - pvt->udimm_last_ce_count[0]; i7core_udimm_check_mc_ecc_err()
1663 pvt->udimm_ce_count[2] += add2; i7core_udimm_check_mc_ecc_err()
1667 pvt->udimm_ce_count[1] += add1; i7core_udimm_check_mc_ecc_err()
1671 pvt->udimm_ce_count[0] += add0; i7core_udimm_check_mc_ecc_err()
1678 pvt->ce_count_available = 1; i7core_udimm_check_mc_ecc_err()
1681 pvt->udimm_last_ce_count[2] = new2; i7core_udimm_check_mc_ecc_err()
1682 pvt->udimm_last_ce_count[1] = new1; i7core_udimm_check_mc_ecc_err()
1683 pvt->udimm_last_ce_count[0] = new0; i7core_udimm_check_mc_ecc_err()
1702 struct i7core_pvt *pvt = mci->pvt_info; i7core_mce_output_error() local
1782 if (uncorrected_error || !pvt->is_registered) i7core_mce_output_error()
1797 struct i7core_pvt *pvt = mci->pvt_info; i7core_check_error() local
1808 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) i7core_check_error()
1813 m = pvt->mce_outentry; i7core_check_error()
1814 if (pvt->mce_in + count > MCE_LOG_LEN) { i7core_check_error()
1815 unsigned l = MCE_LOG_LEN - pvt->mce_in; i7core_check_error()
1817 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); i7core_check_error()
1819 pvt->mce_in = 0; i7core_check_error()
1823 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); i7core_check_error()
1825 pvt->mce_in += count; i7core_check_error()
1828 if (pvt->mce_overrun) { i7core_check_error()
1830 pvt->mce_overrun); i7core_check_error()
1832 pvt->mce_overrun = 0; i7core_check_error()
1839 i7core_mce_output_error(mci, &pvt->mce_outentry[i]); i7core_check_error()
1845 if (!pvt->is_registered) i7core_check_error()
1865 struct i7core_pvt *pvt; i7core_mce_check_error() local
1872 pvt = mci->pvt_info; i7core_mce_check_error()
1886 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { i7core_mce_check_error()
1888 pvt->mce_overrun++; i7core_mce_check_error()
1893 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); i7core_mce_check_error()
1895 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; i7core_mce_check_error()
2022 struct i7core_pvt *pvt = mci->pvt_info; set_sdram_scrub_rate() local
2028 pdev = pvt->pci_mcr[2]; set_sdram_scrub_rate()
2047 const u32 freq_dclk_mhz = pvt->dclk_freq; set_sdram_scrub_rate()
2084 struct i7core_pvt *pvt = mci->pvt_info; get_sdram_scrub_rate() local
2087 const u32 freq_dclk_mhz = pvt->dclk_freq; get_sdram_scrub_rate()
2092 pdev = pvt->pci_mcr[2]; get_sdram_scrub_rate()
2113 struct i7core_pvt *pvt = mci->pvt_info; enable_sdram_scrub_setting() local
2117 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); enable_sdram_scrub_setting()
2119 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, enable_sdram_scrub_setting()
2128 struct i7core_pvt *pvt = mci->pvt_info; disable_sdram_scrub_setting() local
2132 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); disable_sdram_scrub_setting()
2134 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, disable_sdram_scrub_setting()
2138 static void i7core_pci_ctl_create(struct i7core_pvt *pvt) i7core_pci_ctl_create() argument
2140 pvt->i7core_pci = edac_pci_create_generic_ctl( i7core_pci_ctl_create()
2141 &pvt->i7core_dev->pdev[0]->dev, i7core_pci_ctl_create()
2143 if (unlikely(!pvt->i7core_pci)) i7core_pci_ctl_create()
2148 static void i7core_pci_ctl_release(struct i7core_pvt *pvt) i7core_pci_ctl_release() argument
2150 if (likely(pvt->i7core_pci)) i7core_pci_ctl_release()
2151 edac_pci_release_generic_ctl(pvt->i7core_pci); i7core_pci_ctl_release()
2155 pvt->i7core_dev->socket); i7core_pci_ctl_release()
2156 pvt->i7core_pci = NULL; i7core_pci_ctl_release()
2162 struct i7core_pvt *pvt; i7core_unregister_mci() local
2171 pvt = mci->pvt_info; i7core_unregister_mci()
2176 if (pvt->enable_scrub) i7core_unregister_mci()
2180 i7core_pci_ctl_release(pvt); i7core_unregister_mci()
2195 struct i7core_pvt *pvt; i7core_register_mci() local
2208 sizeof(*pvt)); i7core_register_mci()
2214 pvt = mci->pvt_info; i7core_register_mci()
2215 memset(pvt, 0, sizeof(*pvt)); i7core_register_mci()
2218 pvt->i7core_dev = i7core_dev; i7core_register_mci()
2250 if (pvt->enable_scrub) i7core_register_mci()
2271 pvt->inject.channel = 0; i7core_register_mci()
2272 pvt->inject.dimm = -1; i7core_register_mci()
2273 pvt->inject.rank = -1; i7core_register_mci()
2274 pvt->inject.bank = -1; i7core_register_mci()
2275 pvt->inject.page = -1; i7core_register_mci()
2276 pvt->inject.col = -1; i7core_register_mci()
2279 i7core_pci_ctl_create(pvt); i7core_register_mci()
2282 pvt->dclk_freq = get_dclk_freq(); i7core_register_mci()
|
| H A D | amd64_edac.h | 139 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
140 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
141 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
144 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
145 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
146 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
149 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
170 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
192 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
193 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
195 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
197 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
198 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
222 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
223 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
357 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) get_dram_base() argument
359 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; get_dram_base()
364 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; get_dram_base()
367 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) get_dram_limit() argument
369 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; get_dram_limit()
374 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; get_dram_limit()
382 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) dct_sel_interleave_addr() argument
384 if (pvt->fam == 0x15 && pvt->model >= 0x30) dct_sel_interleave_addr()
385 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | dct_sel_interleave_addr()
386 ((pvt->dct_sel_lo >> 6) & 0x3); dct_sel_interleave_addr()
388 return ((pvt)->dct_sel_lo >> 6) & 0x3; dct_sel_interleave_addr()
416 int (*early_channel_count) (struct amd64_pvt *pvt);
419 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
457 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) dram_intlv_en() argument
459 if (pvt->fam == 0x15 && pvt->model >= 0x30) { dram_intlv_en()
461 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); dram_intlv_en()
464 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; dram_intlv_en()
467 static inline u8 dhar_valid(struct amd64_pvt *pvt) dhar_valid() argument
469 if (pvt->fam == 0x15 && pvt->model >= 0x30) { dhar_valid()
471 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); dhar_valid()
474 return (pvt)->dhar & BIT(0); dhar_valid()
477 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) dct_sel_baseaddr() argument
479 if (pvt->fam == 0x15 && pvt->model >= 0x30) { dct_sel_baseaddr()
481 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); dct_sel_baseaddr()
484 return (pvt)->dct_sel_lo & 0xFFFFF800; dct_sel_baseaddr()
|
| H A D | i7300_edac.c | 356 struct i7300_pvt *pvt; i7300_process_error_global() local
362 pvt = mci->pvt_info; i7300_process_error_global()
365 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_process_error_global()
375 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_process_error_global()
381 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_process_error_global()
391 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_process_error_global()
411 struct i7300_pvt *pvt; i7300_process_fbd_error() local
421 pvt = mci->pvt_info; i7300_process_fbd_error()
424 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
433 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
438 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
445 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
448 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, i7300_process_fbd_error()
455 pvt->tmp_prt_buffer); i7300_process_fbd_error()
460 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
469 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
472 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
477 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
483 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
490 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_process_fbd_error()
494 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, i7300_process_fbd_error()
502 pvt->tmp_prt_buffer); i7300_process_fbd_error()
523 struct i7300_pvt *pvt = mci->pvt_info; i7300_clear_error() local
531 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_clear_error()
533 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_clear_error()
536 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_clear_error()
538 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, i7300_clear_error()
542 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_clear_error()
544 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_clear_error()
547 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_clear_error()
549 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_clear_error()
560 struct i7300_pvt *pvt = mci->pvt_info; i7300_enable_error_reporting() local
564 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_enable_error_reporting()
570 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, i7300_enable_error_reporting()
580 * @pvt: pointer to the private data struct used by i7300 driver
587 static int decode_mtr(struct i7300_pvt *pvt, decode_mtr() argument
596 mtr = pvt->mtr[slot][branch]; decode_mtr()
654 if (IS_SINGLE_MODE(pvt->mc_settings_a)) { decode_mtr()
668 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? decode_mtr()
680 * @pvt: pointer to the private data struct used by i7300 driver
684 static void print_dimm_size(struct i7300_pvt *pvt) print_dimm_size() argument
693 p = pvt->tmp_prt_buffer; print_dimm_size()
703 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); print_dimm_size()
704 p = pvt->tmp_prt_buffer; print_dimm_size()
710 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); print_dimm_size()
711 p = pvt->tmp_prt_buffer; print_dimm_size()
720 dinfo = &pvt->dimm_info[slot][channel]; print_dimm_size()
726 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); print_dimm_size()
727 p = pvt->tmp_prt_buffer; print_dimm_size()
735 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); print_dimm_size()
736 p = pvt->tmp_prt_buffer; print_dimm_size()
749 struct i7300_pvt *pvt; i7300_init_csrows() local
756 pvt = mci->pvt_info; i7300_init_csrows()
760 if (IS_SINGLE_MODE(pvt->mc_settings_a)) { i7300_init_csrows()
772 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], i7300_init_csrows()
774 &pvt->ambpresent[channel]); i7300_init_csrows()
776 channel, pvt->ambpresent[channel]); i7300_init_csrows()
782 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], i7300_init_csrows()
784 &pvt->ambpresent[channel]); i7300_init_csrows()
786 channel, pvt->ambpresent[channel]); i7300_init_csrows()
793 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], i7300_init_csrows()
795 &pvt->mtr[slot][branch]); i7300_init_csrows()
802 dinfo = &pvt->dimm_info[slot][channel]; i7300_init_csrows()
804 mtr = decode_mtr(pvt, slot, ch, branch, i7300_init_csrows()
843 struct i7300_pvt *pvt; i7300_get_mc_regs() local
847 pvt = mci->pvt_info; i7300_get_mc_regs()
849 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, i7300_get_mc_regs()
850 (u32 *) &pvt->ambase); i7300_get_mc_regs()
852 edac_dbg(2, "AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase); i7300_get_mc_regs()
855 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); i7300_get_mc_regs()
856 pvt->tolm >>= 12; i7300_get_mc_regs()
858 pvt->tolm, pvt->tolm); i7300_get_mc_regs()
860 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); i7300_get_mc_regs()
862 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); i7300_get_mc_regs()
865 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, i7300_get_mc_regs()
866 &pvt->mc_settings); i7300_get_mc_regs()
867 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, i7300_get_mc_regs()
868 &pvt->mc_settings_a); i7300_get_mc_regs()
870 if (IS_SINGLE_MODE(pvt->mc_settings_a)) i7300_get_mc_regs()
874 IS_MIRRORED(pvt->mc_settings) ? "" : "non-"); i7300_get_mc_regs()
877 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); i7300_get_mc_regs()
879 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); i7300_get_mc_regs()
882 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, i7300_get_mc_regs()
883 &pvt->mir[0]); i7300_get_mc_regs()
884 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, i7300_get_mc_regs()
885 &pvt->mir[1]); i7300_get_mc_regs()
886 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, i7300_get_mc_regs()
887 &pvt->mir[2]); i7300_get_mc_regs()
891 decode_mir(i, pvt->mir); i7300_get_mc_regs()
899 print_dimm_size(pvt); i7300_get_mc_regs()
914 struct i7300_pvt *pvt; i7300_put_devices() local
917 pvt = mci->pvt_info; i7300_put_devices()
921 pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); i7300_put_devices()
922 pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); i7300_put_devices()
923 pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); i7300_put_devices()
939 struct i7300_pvt *pvt; i7300_get_devices() local
942 pvt = mci->pvt_info; i7300_get_devices()
952 if (!pvt->pci_dev_16_1_fsb_addr_map) i7300_get_devices()
953 pvt->pci_dev_16_1_fsb_addr_map = i7300_get_devices()
957 if (!pvt->pci_dev_16_2_fsb_err_regs) i7300_get_devices()
958 pvt->pci_dev_16_2_fsb_err_regs = i7300_get_devices()
964 if (!pvt->pci_dev_16_1_fsb_addr_map || i7300_get_devices()
965 !pvt->pci_dev_16_2_fsb_err_regs) { i7300_get_devices()
976 pci_name(pvt->pci_dev_16_0_fsb_ctlr), i7300_get_devices()
977 pvt->pci_dev_16_0_fsb_ctlr->vendor, i7300_get_devices()
978 pvt->pci_dev_16_0_fsb_ctlr->device); i7300_get_devices()
980 pci_name(pvt->pci_dev_16_1_fsb_addr_map), i7300_get_devices()
981 pvt->pci_dev_16_1_fsb_addr_map->vendor, i7300_get_devices()
982 pvt->pci_dev_16_1_fsb_addr_map->device); i7300_get_devices()
984 pci_name(pvt->pci_dev_16_2_fsb_err_regs), i7300_get_devices()
985 pvt->pci_dev_16_2_fsb_err_regs->vendor, i7300_get_devices()
986 pvt->pci_dev_16_2_fsb_err_regs->device); i7300_get_devices()
988 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, i7300_get_devices()
991 if (!pvt->pci_dev_2x_0_fbd_branch[0]) { i7300_get_devices()
999 pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, i7300_get_devices()
1002 if (!pvt->pci_dev_2x_0_fbd_branch[1]) { i7300_get_devices()
1028 struct i7300_pvt *pvt; i7300_init_one() local
1054 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); i7300_init_one()
1062 pvt = mci->pvt_info; i7300_init_one()
1063 pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ i7300_init_one()
1065 pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL); i7300_init_one()
1066 if (!pvt->tmp_prt_buffer) { i7300_init_one()
1128 kfree(pvt->tmp_prt_buffer); i7300_init_one()
|
| H A D | amd64_edac_inj.c | 8 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_section_show() local
9 return sprintf(buf, "0x%x\n", pvt->injection.section); amd64_inject_section_show()
23 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_section_store() local
36 pvt->injection.section = (u32) value; amd64_inject_section_store()
45 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_word_show() local
46 return sprintf(buf, "0x%x\n", pvt->injection.word); amd64_inject_word_show()
60 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_word_store() local
73 pvt->injection.word = (u32) value; amd64_inject_word_store()
82 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_ecc_vector_show() local
83 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); amd64_inject_ecc_vector_show()
96 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_ecc_vector_store() local
109 pvt->injection.bit_map = (u32) value; amd64_inject_ecc_vector_store()
114 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
122 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_read_store() local
132 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); amd64_inject_read_store()
134 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); amd64_inject_read_store()
136 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); amd64_inject_read_store()
139 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); amd64_inject_read_store()
147 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
155 struct amd64_pvt *pvt = mci->pvt_info; amd64_inject_write_store() local
165 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); amd64_inject_write_store()
167 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); amd64_inject_write_store()
169 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); amd64_inject_write_store()
178 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); amd64_inject_write_store()
182 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); amd64_inject_write_store()
224 struct amd64_pvt *pvt = mci->pvt_info; amd64_edac_inj_is_visible() local
226 if (pvt->fam < 0x10) amd64_edac_inj_is_visible()
|
| H A D | i5400_edac.c | 438 struct i5400_pvt *pvt; i5400_get_error_info() local
441 pvt = mci->pvt_info; i5400_get_error_info()
444 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); i5400_get_error_info()
457 pci_read_config_dword(pvt->branchmap_werrors, i5400_get_error_info()
459 pci_read_config_word(pvt->branchmap_werrors, i5400_get_error_info()
461 pci_read_config_word(pvt->branchmap_werrors, i5400_get_error_info()
465 pci_write_config_dword(pvt->branchmap_werrors, i5400_get_error_info()
475 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); i5400_get_error_info()
483 pci_read_config_dword(pvt->branchmap_werrors, i5400_get_error_info()
485 pci_read_config_word(pvt->branchmap_werrors, i5400_get_error_info()
487 pci_read_config_dword(pvt->branchmap_werrors, i5400_get_error_info()
489 pci_read_config_dword(pvt->branchmap_werrors, i5400_get_error_info()
493 pci_write_config_dword(pvt->branchmap_werrors, i5400_get_error_info()
700 struct i5400_pvt *pvt; i5400_put_devices() local
702 pvt = mci->pvt_info; i5400_put_devices()
705 pci_dev_put(pvt->branch_1); i5400_put_devices()
706 pci_dev_put(pvt->branch_0); i5400_put_devices()
707 pci_dev_put(pvt->fsb_error_regs); i5400_put_devices()
708 pci_dev_put(pvt->branchmap_werrors); i5400_put_devices()
719 struct i5400_pvt *pvt; i5400_get_devices() local
722 pvt = mci->pvt_info; i5400_get_devices()
723 pvt->branchmap_werrors = NULL; i5400_get_devices()
724 pvt->fsb_error_regs = NULL; i5400_get_devices()
725 pvt->branch_0 = NULL; i5400_get_devices()
726 pvt->branch_1 = NULL; i5400_get_devices()
749 pvt->branchmap_werrors = pdev; i5400_get_devices()
765 pci_dev_put(pvt->branchmap_werrors); i5400_get_devices()
773 pvt->fsb_error_regs = pdev; i5400_get_devices()
776 pci_name(pvt->system_address), i5400_get_devices()
777 pvt->system_address->vendor, pvt->system_address->device); i5400_get_devices()
779 pci_name(pvt->branchmap_werrors), i5400_get_devices()
780 pvt->branchmap_werrors->vendor, i5400_get_devices()
781 pvt->branchmap_werrors->device); i5400_get_devices()
783 pci_name(pvt->fsb_error_regs), i5400_get_devices()
784 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); i5400_get_devices()
786 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, i5400_get_devices()
788 if (!pvt->branch_0) { i5400_get_devices()
794 pci_dev_put(pvt->fsb_error_regs); i5400_get_devices()
795 pci_dev_put(pvt->branchmap_werrors); i5400_get_devices()
802 if (pvt->maxch < CHANNELS_PER_BRANCH) i5400_get_devices()
805 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, i5400_get_devices()
807 if (!pvt->branch_1) { i5400_get_devices()
815 pci_dev_put(pvt->branch_0); i5400_get_devices()
816 pci_dev_put(pvt->fsb_error_regs); i5400_get_devices()
817 pci_dev_put(pvt->branchmap_werrors); i5400_get_devices()
837 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel) determine_amb_present_reg() argument
843 amb_present = pvt->b0_ambpresent1; determine_amb_present_reg()
845 amb_present = pvt->b0_ambpresent0; determine_amb_present_reg()
848 amb_present = pvt->b1_ambpresent1; determine_amb_present_reg()
850 amb_present = pvt->b1_ambpresent0; determine_amb_present_reg()
857 * determine_mtr(pvt, dimm, channel)
861 static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel) determine_mtr() argument
878 mtr = pvt->b0_mtr[n]; determine_mtr()
880 mtr = pvt->b1_mtr[n]; determine_mtr()
918 static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel, handle_channel() argument
925 mtr = determine_mtr(pvt, dimm, channel); handle_channel()
927 amb_present_reg = determine_amb_present_reg(pvt, channel); handle_channel()
956 static void calculate_dimm_size(struct i5400_pvt *pvt) calculate_dimm_size() argument
978 max_dimms = pvt->maxdimmperch; calculate_dimm_size()
996 for (channel = 0; channel < pvt->maxch; channel++) { calculate_dimm_size()
997 dinfo = &pvt->dimm_info[dimm][channel]; calculate_dimm_size()
998 handle_channel(pvt, dimm, channel, dinfo); calculate_dimm_size()
1021 for (channel = 0; channel < pvt->maxch; channel++) { calculate_dimm_size()
1053 struct i5400_pvt *pvt; i5400_get_mc_regs() local
1061 pvt = mci->pvt_info; i5400_get_mc_regs()
1063 pci_read_config_dword(pvt->system_address, AMBASE, i5400_get_mc_regs()
1064 &pvt->u.ambase_bottom); i5400_get_mc_regs()
1065 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), i5400_get_mc_regs()
1066 &pvt->u.ambase_top); i5400_get_mc_regs()
1068 maxdimmperch = pvt->maxdimmperch; i5400_get_mc_regs()
1069 maxch = pvt->maxch; i5400_get_mc_regs()
1072 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); i5400_get_mc_regs()
1075 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); i5400_get_mc_regs()
1076 pvt->tolm >>= 12; i5400_get_mc_regs()
1078 pvt->tolm, pvt->tolm); i5400_get_mc_regs()
1080 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); i5400_get_mc_regs()
1082 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); i5400_get_mc_regs()
1084 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); i5400_get_mc_regs()
1085 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); i5400_get_mc_regs()
1088 limit = (pvt->mir0 >> 4) & 0x0fff; i5400_get_mc_regs()
1089 way0 = pvt->mir0 & 0x1; i5400_get_mc_regs()
1090 way1 = pvt->mir0 & 0x2; i5400_get_mc_regs()
1093 limit = (pvt->mir1 >> 4) & 0xfff; i5400_get_mc_regs()
1094 way0 = pvt->mir1 & 0x1; i5400_get_mc_regs()
1095 way1 = pvt->mir1 & 0x2; i5400_get_mc_regs()
1104 pci_read_config_word(pvt->branch_0, where, i5400_get_mc_regs()
1105 &pvt->b0_mtr[slot_row]); i5400_get_mc_regs()
1108 slot_row, where, pvt->b0_mtr[slot_row]); i5400_get_mc_regs()
1110 if (pvt->maxch < CHANNELS_PER_BRANCH) { i5400_get_mc_regs()
1111 pvt->b1_mtr[slot_row] = 0; i5400_get_mc_regs()
1116 pci_read_config_word(pvt->branch_1, where, i5400_get_mc_regs()
1117 &pvt->b1_mtr[slot_row]); i5400_get_mc_regs()
1119 slot_row, where, pvt->b1_mtr[slot_row]); i5400_get_mc_regs()
1126 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); i5400_get_mc_regs()
1128 pci_read_config_word(pvt->branch_0, AMBPRESENT_0, i5400_get_mc_regs()
1129 &pvt->b0_ambpresent0); i5400_get_mc_regs()
1130 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); i5400_get_mc_regs()
1131 pci_read_config_word(pvt->branch_0, AMBPRESENT_1, i5400_get_mc_regs()
1132 &pvt->b0_ambpresent1); i5400_get_mc_regs()
1133 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); i5400_get_mc_regs()
1136 if (pvt->maxch < CHANNELS_PER_BRANCH) { i5400_get_mc_regs()
1137 pvt->b1_ambpresent0 = 0; i5400_get_mc_regs()
1138 pvt->b1_ambpresent1 = 0; i5400_get_mc_regs()
1143 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); i5400_get_mc_regs()
1145 pci_read_config_word(pvt->branch_1, AMBPRESENT_0, i5400_get_mc_regs()
1146 &pvt->b1_ambpresent0); i5400_get_mc_regs()
1148 pvt->b1_ambpresent0); i5400_get_mc_regs()
1149 pci_read_config_word(pvt->branch_1, AMBPRESENT_1, i5400_get_mc_regs()
1150 &pvt->b1_ambpresent1); i5400_get_mc_regs()
1152 pvt->b1_ambpresent1); i5400_get_mc_regs()
1157 calculate_dimm_size(pvt); i5400_get_mc_regs()
1171 struct i5400_pvt *pvt; i5400_init_dimms() local
1179 pvt = mci->pvt_info; i5400_init_dimms()
1181 channel_count = pvt->maxch; i5400_init_dimms()
1182 max_dimms = pvt->maxdimmperch; i5400_init_dimms()
1187 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 i5400_init_dimms()
1193 mtr = determine_mtr(pvt, slot, channel); i5400_init_dimms()
1202 size_mb = pvt->dimm_info[slot][channel].megabytes; i5400_init_dimms()
1238 struct i5400_pvt *pvt; i5400_enable_error_reporting() local
1241 pvt = mci->pvt_info; i5400_enable_error_reporting()
1244 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, i5400_enable_error_reporting()
1250 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, i5400_enable_error_reporting()
1264 struct i5400_pvt *pvt; i5400_probe1() local
1292 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); i5400_probe1()
1300 pvt = mci->pvt_info; i5400_probe1()
1301 pvt->system_address = pdev; /* Record this device in our private */ i5400_probe1()
1302 pvt->maxch = MAX_CHANNELS; i5400_probe1()
1303 pvt->maxdimmperch = DIMMS_PER_CHANNEL; i5400_probe1()
|
| H A D | i5000_edac.c | 388 struct i5000_pvt *pvt; i5000_get_error_info() local
391 pvt = mci->pvt_info; i5000_get_error_info()
394 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); i5000_get_error_info()
406 pci_read_config_dword(pvt->branchmap_werrors, i5000_get_error_info()
408 pci_read_config_word(pvt->branchmap_werrors, i5000_get_error_info()
410 pci_read_config_word(pvt->branchmap_werrors, i5000_get_error_info()
414 pci_write_config_dword(pvt->branchmap_werrors, i5000_get_error_info()
424 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); i5000_get_error_info()
432 pci_read_config_dword(pvt->branchmap_werrors, i5000_get_error_info()
434 pci_read_config_word(pvt->branchmap_werrors, i5000_get_error_info()
436 pci_read_config_dword(pvt->branchmap_werrors, i5000_get_error_info()
438 pci_read_config_dword(pvt->branchmap_werrors, i5000_get_error_info()
442 pci_write_config_dword(pvt->branchmap_werrors, i5000_get_error_info()
782 struct i5000_pvt *pvt; i5000_get_devices() local
785 pvt = mci->pvt_info; i5000_get_devices()
811 pvt->branchmap_werrors = pdev; i5000_get_devices()
828 pci_dev_put(pvt->branchmap_werrors); i5000_get_devices()
837 pvt->fsb_error_regs = pdev; i5000_get_devices()
840 pci_name(pvt->system_address), i5000_get_devices()
841 pvt->system_address->vendor, pvt->system_address->device); i5000_get_devices()
843 pci_name(pvt->branchmap_werrors), i5000_get_devices()
844 pvt->branchmap_werrors->vendor, i5000_get_devices()
845 pvt->branchmap_werrors->device); i5000_get_devices()
847 pci_name(pvt->fsb_error_regs), i5000_get_devices()
848 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); i5000_get_devices()
860 pci_dev_put(pvt->branchmap_werrors); i5000_get_devices()
861 pci_dev_put(pvt->fsb_error_regs); i5000_get_devices()
865 pvt->branch_0 = pdev; i5000_get_devices()
870 if (pvt->maxch >= CHANNELS_PER_BRANCH) { i5000_get_devices()
883 pci_dev_put(pvt->branchmap_werrors); i5000_get_devices()
884 pci_dev_put(pvt->fsb_error_regs); i5000_get_devices()
885 pci_dev_put(pvt->branch_0); i5000_get_devices()
889 pvt->branch_1 = pdev; i5000_get_devices()
901 struct i5000_pvt *pvt; i5000_put_devices() local
903 pvt = mci->pvt_info; i5000_put_devices()
905 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */ i5000_put_devices()
906 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */ i5000_put_devices()
907 pci_dev_put(pvt->branch_0); /* DEV 21 */ i5000_put_devices()
910 if (pvt->maxch >= CHANNELS_PER_BRANCH) i5000_put_devices()
911 pci_dev_put(pvt->branch_1); /* DEV 22 */ i5000_put_devices()
927 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel) determine_amb_present_reg() argument
933 amb_present = pvt->b0_ambpresent1; determine_amb_present_reg()
935 amb_present = pvt->b0_ambpresent0; determine_amb_present_reg()
938 amb_present = pvt->b1_ambpresent1; determine_amb_present_reg()
940 amb_present = pvt->b1_ambpresent0; determine_amb_present_reg()
947 * determine_mtr(pvt, csrow, channel)
951 static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel) determine_mtr() argument
956 mtr = pvt->b0_mtr[slot]; determine_mtr()
958 mtr = pvt->b1_mtr[slot]; determine_mtr()
992 static void handle_channel(struct i5000_pvt *pvt, int slot, int channel, handle_channel() argument
999 mtr = determine_mtr(pvt, slot, channel); handle_channel()
1001 amb_present_reg = determine_amb_present_reg(pvt, channel); handle_channel()
1034 static void calculate_dimm_size(struct i5000_pvt *pvt) calculate_dimm_size() argument
1055 for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) { calculate_dimm_size()
1072 for (channel = 0; channel < pvt->maxch; channel++) { calculate_dimm_size()
1073 dinfo = &pvt->dimm_info[slot][channel]; calculate_dimm_size()
1074 handle_channel(pvt, slot, channel, dinfo); calculate_dimm_size()
1103 for (channel = 0; channel < pvt->maxch; channel++) { calculate_dimm_size()
1133 struct i5000_pvt *pvt; i5000_get_mc_regs() local
1141 pvt = mci->pvt_info; i5000_get_mc_regs()
1143 pci_read_config_dword(pvt->system_address, AMBASE, i5000_get_mc_regs()
1144 &pvt->u.ambase_bottom); i5000_get_mc_regs()
1145 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), i5000_get_mc_regs()
1146 &pvt->u.ambase_top); i5000_get_mc_regs()
1148 maxdimmperch = pvt->maxdimmperch; i5000_get_mc_regs()
1149 maxch = pvt->maxch; i5000_get_mc_regs()
1152 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); i5000_get_mc_regs()
1155 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); i5000_get_mc_regs()
1156 pvt->tolm >>= 12; i5000_get_mc_regs()
1158 pvt->tolm, pvt->tolm); i5000_get_mc_regs()
1160 actual_tolm = pvt->tolm << 28; i5000_get_mc_regs()
1164 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); i5000_get_mc_regs()
1165 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); i5000_get_mc_regs()
1166 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2); i5000_get_mc_regs()
1169 limit = (pvt->mir0 >> 4) & 0x0FFF; i5000_get_mc_regs()
1170 way0 = pvt->mir0 & 0x1; i5000_get_mc_regs()
1171 way1 = pvt->mir0 & 0x2; i5000_get_mc_regs()
1174 limit = (pvt->mir1 >> 4) & 0x0FFF; i5000_get_mc_regs()
1175 way0 = pvt->mir1 & 0x1; i5000_get_mc_regs()
1176 way1 = pvt->mir1 & 0x2; i5000_get_mc_regs()
1179 limit = (pvt->mir2 >> 4) & 0x0FFF; i5000_get_mc_regs()
1180 way0 = pvt->mir2 & 0x1; i5000_get_mc_regs()
1181 way1 = pvt->mir2 & 0x2; i5000_get_mc_regs()
1189 pci_read_config_word(pvt->branch_0, where, i5000_get_mc_regs()
1190 &pvt->b0_mtr[slot_row]); i5000_get_mc_regs()
1193 slot_row, where, pvt->b0_mtr[slot_row]); i5000_get_mc_regs()
1195 if (pvt->maxch >= CHANNELS_PER_BRANCH) { i5000_get_mc_regs()
1196 pci_read_config_word(pvt->branch_1, where, i5000_get_mc_regs()
1197 &pvt->b1_mtr[slot_row]); i5000_get_mc_regs()
1199 slot_row, where, pvt->b1_mtr[slot_row]); i5000_get_mc_regs()
1201 pvt->b1_mtr[slot_row] = 0; i5000_get_mc_regs()
1209 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); i5000_get_mc_regs()
1211 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0, i5000_get_mc_regs()
1212 &pvt->b0_ambpresent0); i5000_get_mc_regs()
1213 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); i5000_get_mc_regs()
1214 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1, i5000_get_mc_regs()
1215 &pvt->b0_ambpresent1); i5000_get_mc_regs()
1216 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); i5000_get_mc_regs()
1219 if (pvt->maxch < CHANNELS_PER_BRANCH) { i5000_get_mc_regs()
1220 pvt->b1_ambpresent0 = 0; i5000_get_mc_regs()
1221 pvt->b1_ambpresent1 = 0; i5000_get_mc_regs()
1226 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); i5000_get_mc_regs()
1228 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0, i5000_get_mc_regs()
1229 &pvt->b1_ambpresent0); i5000_get_mc_regs()
1231 pvt->b1_ambpresent0); i5000_get_mc_regs()
1232 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1, i5000_get_mc_regs()
1233 &pvt->b1_ambpresent1); i5000_get_mc_regs()
1235 pvt->b1_ambpresent1); i5000_get_mc_regs()
1240 calculate_dimm_size(pvt); i5000_get_mc_regs()
1254 struct i5000_pvt *pvt; i5000_init_csrows() local
1263 pvt = mci->pvt_info; i5000_init_csrows()
1265 channel_count = pvt->maxch; i5000_init_csrows()
1266 max_csrows = pvt->maxdimmperch * 2; i5000_init_csrows()
1278 for (channel = 0; channel < pvt->maxch; channel++) { i5000_init_csrows()
1280 mtr = determine_mtr(pvt, slot, channel); i5000_init_csrows()
1289 csrow_megs = pvt->dimm_info[slot][channel].megabytes; i5000_init_csrows()
1317 struct i5000_pvt *pvt; i5000_enable_error_reporting() local
1320 pvt = mci->pvt_info; i5000_enable_error_reporting()
1323 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, i5000_enable_error_reporting()
1329 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, i5000_enable_error_reporting()
1366 struct i5000_pvt *pvt; i5000_probe1() local
1408 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); i5000_probe1()
1416 pvt = mci->pvt_info; i5000_probe1()
1417 pvt->system_address = pdev; /* Record this device in our private */ i5000_probe1()
1418 pvt->maxch = num_channels; i5000_probe1()
1419 pvt->maxdimmperch = num_dimms_per_channel; i5000_probe1()
|
| H A D | octeon_edac-lmc.c | 74 struct octeon_lmc_pvt *pvt = mci->pvt_info; octeon_lmc_edac_poll_o2() local
79 if (!pvt->inject) octeon_lmc_edac_poll_o2()
82 if (pvt->error_type == 1) octeon_lmc_edac_poll_o2()
84 if (pvt->error_type == 2) octeon_lmc_edac_poll_o2()
90 if (likely(!pvt->inject)) octeon_lmc_edac_poll_o2()
93 fadr.cn61xx.fdimm = pvt->dimm; octeon_lmc_edac_poll_o2()
94 fadr.cn61xx.fbunk = pvt->rank; octeon_lmc_edac_poll_o2()
95 fadr.cn61xx.fbank = pvt->bank; octeon_lmc_edac_poll_o2()
96 fadr.cn61xx.frow = pvt->row; octeon_lmc_edac_poll_o2()
97 fadr.cn61xx.fcol = pvt->col; octeon_lmc_edac_poll_o2()
120 if (likely(!pvt->inject)) octeon_lmc_edac_poll_o2()
123 pvt->inject = 0; octeon_lmc_edac_poll_o2()
136 struct octeon_lmc_pvt *pvt = mci->pvt_info; \
137 return sprintf(data, "%016llu\n", (u64)pvt->reg); \
146 struct octeon_lmc_pvt *pvt = mci->pvt_info; \
148 if (!kstrtoul(data, 0, &pvt->reg)) \
173 struct octeon_lmc_pvt *pvt = mci->pvt_info; octeon_mc_inject_error_type_store() local
176 pvt->error_type = 1; octeon_mc_inject_error_type_store()
178 pvt->error_type = 2; octeon_mc_inject_error_type_store()
188 struct octeon_lmc_pvt *pvt = mci->pvt_info; octeon_mc_inject_error_type_show() local
189 if (pvt->error_type == 1) octeon_mc_inject_error_type_show()
191 else if (pvt->error_type == 2) octeon_mc_inject_error_type_show()
|
| H A D | e7xxx_edac.c | 187 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; ctl_page_to_phys() local
191 if ((page < pvt->tolm) || ctl_page_to_phys()
192 ((page >= 0x100000) && (page < pvt->remapbase))) ctl_page_to_phys()
195 remap = (page - pvt->tolm) + pvt->remapbase; ctl_page_to_phys()
197 if (remap < pvt->remaplimit) ctl_page_to_phys()
201 return pvt->tolm - 1; ctl_page_to_phys()
260 struct e7xxx_pvt *pvt; e7xxx_get_error_info() local
262 pvt = (struct e7xxx_pvt *)mci->pvt_info; e7xxx_get_error_info()
263 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr); e7xxx_get_error_info()
264 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr); e7xxx_get_error_info()
267 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD, e7xxx_get_error_info()
269 pci_read_config_word(pvt->bridge_ck, e7xxx_get_error_info()
275 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD, e7xxx_get_error_info()
279 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03); e7xxx_get_error_info()
282 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03); e7xxx_get_error_info()
427 struct e7xxx_pvt *pvt = NULL; e7xxx_probe1() local
451 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); e7xxx_probe1()
463 edac_dbg(3, "init pvt\n"); e7xxx_probe1()
464 pvt = (struct e7xxx_pvt *)mci->pvt_info; e7xxx_probe1()
465 pvt->dev_info = &e7xxx_devs[dev_idx]; e7xxx_probe1()
466 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, e7xxx_probe1()
467 pvt->dev_info->err_dev, pvt->bridge_ck); e7xxx_probe1()
469 if (!pvt->bridge_ck) { e7xxx_probe1()
477 mci->ctl_name = pvt->dev_info->ctl_name; e7xxx_probe1()
486 pvt->tolm = ((u32) pci_data) << 4; e7xxx_probe1()
488 pvt->remapbase = ((u32) pci_data) << 14; e7xxx_probe1()
490 pvt->remaplimit = ((u32) pci_data) << 14; e7xxx_probe1()
492 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, e7xxx_probe1()
493 pvt->remapbase, pvt->remaplimit); e7xxx_probe1()
522 pci_dev_put(pvt->bridge_ck); e7xxx_probe1()
543 struct e7xxx_pvt *pvt; e7xxx_remove_one() local
553 pvt = (struct e7xxx_pvt *)mci->pvt_info; e7xxx_remove_one()
554 pci_dev_put(pvt->bridge_ck); e7xxx_remove_one()
|
| H A D | ghes_edac.c | 174 struct ghes_edac_pvt *pvt = NULL; ghes_edac_report_mem_error() local
178 list_for_each_entry(pvt, &ghes_reglist, list) { ghes_edac_report_mem_error()
179 if (ghes == pvt->ghes) ghes_edac_report_mem_error()
182 if (!pvt) { ghes_edac_report_mem_error()
186 mci = pvt->mci; ghes_edac_report_mem_error()
193 e->msg = pvt->msg; ghes_edac_report_mem_error()
194 e->other_detail = pvt->other_detail; ghes_edac_report_mem_error()
198 *pvt->other_detail = '\0'; ghes_edac_report_mem_error()
199 *pvt->msg = '\0'; ghes_edac_report_mem_error()
221 p = pvt->msg; ghes_edac_report_mem_error()
276 strcpy(pvt->msg, "unknown error"); ghes_edac_report_mem_error()
320 p = pvt->other_detail; ghes_edac_report_mem_error()
391 if (p > pvt->other_detail) ghes_edac_report_mem_error()
396 snprintf(pvt->detail_location, sizeof(pvt->detail_location), ghes_edac_report_mem_error()
401 grain_bits, e->syndrome, pvt->detail_location); ghes_edac_report_mem_error()
414 struct ghes_edac_pvt *pvt; ghes_edac_register() local
436 sizeof(*pvt)); ghes_edac_register()
443 pvt = mci->pvt_info; ghes_edac_register()
444 memset(pvt, 0, sizeof(*pvt)); ghes_edac_register()
445 list_add_tail(&pvt->list, &ghes_reglist); ghes_edac_register()
446 pvt->ghes = ghes; ghes_edac_register()
447 pvt->mci = mci; ghes_edac_register()
516 struct ghes_edac_pvt *pvt, *tmp; ghes_edac_unregister() local
518 list_for_each_entry_safe(pvt, tmp, &ghes_reglist, list) { ghes_edac_unregister()
519 if (ghes == pvt->ghes) { ghes_edac_unregister()
520 mci = pvt->mci; ghes_edac_unregister()
523 list_del(&pvt->list); ghes_edac_unregister()
|
| H A D | e752x_edac.c | 309 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; ctl_page_to_phys() local
313 if (page < pvt->tolm) ctl_page_to_phys()
316 if ((page >= 0x100000) && (page < pvt->remapbase)) ctl_page_to_phys()
319 remap = (page - pvt->tolm) + pvt->remapbase; ctl_page_to_phys()
321 if (remap < pvt->remaplimit) ctl_page_to_phys()
325 return pvt->tolm - 1; ctl_page_to_phys()
335 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; do_process_ce() local
343 if (pvt->mc_symmetric) { do_process_ce()
348 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], do_process_ce()
349 pvt->map[4], pvt->map[5], pvt->map[6], do_process_ce()
350 pvt->map[7]); do_process_ce()
354 if (pvt->map[i] == row) do_process_ce()
394 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; do_process_ue() local
404 row = pvt->mc_symmetric ? do_process_ue()
423 row = pvt->mc_symmetric ? do_process_ue()
466 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; do_process_ded_retry() local
472 row = pvt->mc_symmetric ? ((page >> 1) & 3) : do_process_ded_retry()
843 struct e752x_pvt *pvt; e752x_get_error_info() local
846 pvt = (struct e752x_pvt *)mci->pvt_info; e752x_get_error_info()
847 dev = pvt->dev_d0f1; e752x_get_error_info()
851 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { e752x_get_error_info()
893 pci_write_bits16(pvt->dev_d0f1, E752X_DRAM_FERR, e752x_get_error_info()
903 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { e752x_get_error_info()
938 pci_write_bits16(pvt->dev_d0f1, E752X_DRAM_NERR, e752x_get_error_info()
993 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; set_sdram_scrub_rate() local
994 struct pci_dev *pdev = pvt->dev_d0f0; set_sdram_scrub_rate()
997 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0) set_sdram_scrub_rate()
1022 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; get_sdram_scrub_rate() local
1023 struct pci_dev *pdev = pvt->dev_d0f0; get_sdram_scrub_rate()
1027 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0) get_sdram_scrub_rate()
1059 struct e752x_pvt *pvt = mci->pvt_info; remap_csrow_index() local
1061 if (!pvt->map_type) remap_csrow_index()
1141 struct e752x_pvt *pvt) e752x_init_mem_map_table()
1154 pvt->map[index] = 0xff; e752x_init_mem_map_table()
1155 pvt->map[index + 1] = 0xff; e752x_init_mem_map_table()
1157 pvt->map[index] = row; e752x_init_mem_map_table()
1168 pvt->map[index + 1] = (value == last) ? 0xff : row; e752x_init_mem_map_table()
1177 struct e752x_pvt *pvt) e752x_get_devs()
1179 pvt->dev_d0f1 = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_get_devs()
1180 pvt->dev_info->err_dev, NULL); e752x_get_devs()
1182 if (pvt->dev_d0f1 == NULL) { e752x_get_devs()
1183 pvt->dev_d0f1 = pci_scan_single_device(pdev->bus, e752x_get_devs()
1185 pci_dev_get(pvt->dev_d0f1); e752x_get_devs()
1188 if (pvt->dev_d0f1 == NULL) { e752x_get_devs()
1195 pvt->dev_d0f0 = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_get_devs()
1199 if (pvt->dev_d0f0 == NULL) e752x_get_devs()
1205 pci_dev_put(pvt->dev_d0f1); e752x_get_devs()
1213 static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt) e752x_init_sysbus_parity_mask() argument
1216 struct pci_dev *dev = pvt->dev_d0f1; e752x_init_sysbus_parity_mask()
1234 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt) e752x_init_error_reporting_regs() argument
1238 dev = pvt->dev_d0f1; e752x_init_error_reporting_regs()
1240 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { e752x_init_error_reporting_regs()
1248 e752x_init_sysbus_parity_mask(pvt); e752x_init_error_reporting_regs()
1263 struct e752x_pvt *pvt; e752x_probe1() local
1295 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); e752x_probe1()
1309 edac_dbg(3, "init pvt\n"); e752x_probe1()
1310 pvt = (struct e752x_pvt *)mci->pvt_info; e752x_probe1()
1311 pvt->dev_info = &e752x_devs[dev_idx]; e752x_probe1()
1312 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); e752x_probe1()
1314 if (e752x_get_devs(pdev, dev_idx, pvt)) { e752x_probe1()
1320 mci->ctl_name = pvt->dev_info->ctl_name; e752x_probe1()
1332 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); e752x_probe1()
1335 e752x_init_mem_map_table(pdev, pvt); e752x_probe1()
1345 pvt->tolm = ((u32) pci_data) << 4; e752x_probe1()
1347 pvt->remapbase = ((u32) pci_data) << 14; e752x_probe1()
1349 pvt->remaplimit = ((u32) pci_data) << 14; e752x_probe1()
1352 pvt->tolm, pvt->remapbase, pvt->remaplimit); e752x_probe1()
1362 e752x_init_error_reporting_regs(pvt); e752x_probe1()
1380 pci_dev_put(pvt->dev_d0f0); e752x_probe1()
1381 pci_dev_put(pvt->dev_d0f1); e752x_probe1()
1402 struct e752x_pvt *pvt; e752x_remove_one() local
1412 pvt = (struct e752x_pvt *)mci->pvt_info; e752x_remove_one()
1413 pci_dev_put(pvt->dev_d0f0); e752x_remove_one()
1414 pci_dev_put(pvt->dev_d0f1); e752x_remove_one()
1140 e752x_init_mem_map_table(struct pci_dev *pdev, struct e752x_pvt *pvt) e752x_init_mem_map_table() argument
1176 e752x_get_devs(struct pci_dev *pdev, int dev_idx, struct e752x_pvt *pvt) e752x_get_devs() argument
|
| H A D | amd64_edac_dbg.c | 9 struct amd64_pvt *pvt = mci->pvt_info; \
10 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
|
| H A D | i82875p_edac.c | 394 struct i82875p_pvt *pvt; i82875p_probe1() local
414 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); i82875p_probe1()
431 edac_dbg(3, "init pvt\n"); i82875p_probe1()
432 pvt = (struct i82875p_pvt *)mci->pvt_info; i82875p_probe1()
433 pvt->ovrfl_pdev = ovrfl_pdev; i82875p_probe1()
434 pvt->ovrfl_window = ovrfl_window; i82875p_probe1()
496 struct i82875p_pvt *pvt = NULL; i82875p_remove_one() local
506 pvt = (struct i82875p_pvt *)mci->pvt_info; i82875p_remove_one()
508 if (pvt->ovrfl_window) i82875p_remove_one()
509 iounmap(pvt->ovrfl_window); i82875p_remove_one()
511 if (pvt->ovrfl_pdev) { i82875p_remove_one()
513 pci_release_regions(pvt->ovrfl_pdev); i82875p_remove_one()
515 pci_disable_device(pvt->ovrfl_pdev); i82875p_remove_one()
516 pci_dev_put(pvt->ovrfl_pdev); i82875p_remove_one()
|
| H A D | i82975x_edac.c | 477 struct i82975x_pvt *pvt; i82975x_probe1() local
551 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); i82975x_probe1()
568 edac_dbg(3, "init pvt\n"); i82975x_probe1()
569 pvt = (struct i82975x_pvt *) mci->pvt_info; i82975x_probe1()
570 pvt->mch_window = mch_window; i82975x_probe1()
616 struct i82975x_pvt *pvt; i82975x_remove_one() local
624 pvt = mci->pvt_info; i82975x_remove_one()
625 if (pvt->mch_window) i82975x_remove_one()
626 iounmap( pvt->mch_window ); i82975x_remove_one()
|
| H A D | edac_pci.c | 45 void *p = NULL, *pvt; edac_pci_alloc_ctl_info() local
51 pvt = edac_align_ptr(&p, 1, sz_pvt); edac_pci_alloc_ctl_info()
52 size = ((unsigned long)pvt) + sz_pvt; edac_pci_alloc_ctl_info()
60 pvt = sz_pvt ? ((char *)pci) + ((unsigned long)pvt) : NULL; edac_pci_alloc_ctl_info()
62 pci->pvt_info = pvt; edac_pci_alloc_ctl_info()
|
| H A D | edac_device.c | 83 void *pvt, *p; edac_device_alloc_ctl_info() local
118 pvt = edac_align_ptr(&p, sz_private, 1); edac_device_alloc_ctl_info()
120 /* 'pvt' now points to where the private data area is. edac_device_alloc_ctl_info()
121 * At this point 'pvt' (like dev_inst,dev_blk and dev_attrib) edac_device_alloc_ctl_info()
124 total_size = ((unsigned long)pvt) + sz_private; edac_device_alloc_ctl_info()
144 pvt = sz_private ? (((char *)dev_ctl) + ((unsigned long)pvt)) : NULL; edac_device_alloc_ctl_info()
150 dev_ctl->pvt_info = pvt; edac_device_alloc_ctl_info()
160 dev_ctl, pvt + sz_private); edac_device_alloc_ctl_info()
|
| H A D | edac_mc.c | 280 void *pvt, *p, *ptr = NULL; edac_mc_alloc() local
316 pvt = edac_align_ptr(&ptr, sz_pvt, 1); edac_mc_alloc()
317 size = ((unsigned long)pvt) + sz_pvt; edac_mc_alloc()
337 pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; edac_mc_alloc()
342 mci->pvt_info = pvt; edac_mc_alloc()
|
| /linux-4.4.14/drivers/gpu/drm/omapdrm/ |
| H A D | tcm-sita.c | 83 struct sita_pvt *pvt; sita_init() local
91 pvt = kmalloc(sizeof(*pvt), GFP_KERNEL); sita_init()
92 if (!tcm || !pvt) sita_init()
96 memset(pvt, 0, sizeof(*pvt)); sita_init()
105 tcm->pvt = (void *)pvt; sita_init()
107 spin_lock_init(&(pvt->lock)); sita_init()
110 pvt->map = kmalloc(sizeof(*pvt->map) * tcm->width, GFP_KERNEL); sita_init()
111 if (!pvt->map) sita_init()
115 pvt->map[i] = sita_init()
116 kmalloc(sizeof(**pvt->map) * tcm->height, sita_init()
118 if (pvt->map[i] == NULL) { sita_init()
120 kfree(pvt->map[i]); sita_init()
121 kfree(pvt->map); sita_init()
127 pvt->div_pt.x = attr->x; sita_init()
128 pvt->div_pt.y = attr->y; sita_init()
133 pvt->div_pt.x = (tcm->width * 3) / 4; sita_init()
134 pvt->div_pt.y = (tcm->height * 3) / 4; sita_init()
137 spin_lock(&(pvt->lock)); sita_init()
140 spin_unlock(&(pvt->lock)); sita_init()
145 kfree(pvt); sita_init()
151 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; sita_deinit() local
158 spin_lock(&(pvt->lock)); sita_deinit()
160 spin_unlock(&(pvt->lock)); sita_deinit()
163 kfree(pvt->map[i]); sita_deinit()
164 kfree(pvt->map); sita_deinit()
165 kfree(pvt); sita_deinit()
182 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; sita_reserve_1d() local
184 spin_lock(&(pvt->lock)); sita_reserve_1d()
194 spin_unlock(&(pvt->lock)); sita_reserve_1d()
212 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; sita_reserve_2d() local
221 spin_lock(&(pvt->lock)); sita_reserve_2d()
227 spin_unlock(&(pvt->lock)); sita_reserve_2d()
238 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; sita_free() local
240 spin_lock(&(pvt->lock)); sita_free()
243 WARN_ON(pvt->map[area->p0.x][area->p0.y] != area || sita_free()
244 pvt->map[area->p1.x][area->p1.y] != area); sita_free()
249 spin_unlock(&(pvt->lock)); sita_free()
279 struct tcm_area ***map = ((struct sita_pvt *)tcm->pvt)->map; scan_r2l_t2b()
353 struct tcm_area ***map = ((struct sita_pvt *)tcm->pvt)->map; scan_l2r_t2b()
429 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; scan_r2l_b2t_one_dim() local
462 p = pvt->map[x][y]; scan_r2l_b2t_one_dim()
508 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; scan_areas_and_find_fit() local
512 boundary_x = pvt->div_pt.x - 1; scan_areas_and_find_fit()
513 boundary_y = pvt->div_pt.y - 1; scan_areas_and_find_fit()
516 if (w > pvt->div_pt.x) scan_areas_and_find_fit()
518 if (h > pvt->div_pt.y) scan_areas_and_find_fit()
533 boundary_x = pvt->div_pt.x; scan_areas_and_find_fit()
534 boundary_y = pvt->div_pt.y - 1; scan_areas_and_find_fit()
537 if (w > (tcm->width - pvt->div_pt.x)) scan_areas_and_find_fit()
539 if (h > pvt->div_pt.y) scan_areas_and_find_fit()
576 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; fill_area() local
585 pvt->map[x][y] = parent; fill_area()
673 struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt; get_neighbor_stats() local
682 else if (pvt->map[x][area->p0.y - 1]) get_neighbor_stats()
687 else if (pvt->map[x][area->p1.y + 1]) get_neighbor_stats()
695 else if (pvt->map[area->p0.x - 1][y]) get_neighbor_stats()
700 else if (pvt->map[area->p1.x + 1][y]) get_neighbor_stats()
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| H A D | tcm.h | 64 /* 'pvt' structure shall contain any tcm details (attr) along with
68 void *pvt; member in struct:tcm
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| /linux-4.4.14/sound/pci/asihpi/ |
| H A D | hpidspcd.c | 83 dsp_code->pvt = kmalloc(sizeof(*dsp_code->pvt), GFP_KERNEL); hpi_dsp_code_open()
84 if (!dsp_code->pvt) { hpi_dsp_code_open()
89 dsp_code->pvt->dev = dev; hpi_dsp_code_open()
90 dsp_code->pvt->firmware = firmware; hpi_dsp_code_open()
107 release_firmware(dsp_code->pvt->firmware); hpi_dsp_code_close()
108 kfree(dsp_code->pvt); hpi_dsp_code_close()
124 *pword = ((u32 *)(dsp_code->pvt->firmware->data))[dsp_code-> hpi_dsp_code_read_word()
138 ((u32 *)(dsp_code->pvt->firmware->data)) + hpi_dsp_code_read_block()
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| H A D | hpidspcd.h | 65 struct dsp_code_private *pvt; member in struct:dsp_code
|
| /linux-4.4.14/arch/s390/kernel/ |
| H A D | cache.c | 162 unsigned int level, idx, pvt; populate_cache_leaves() local
173 pvt = (ct.ci[level].scope == CACHE_SCOPE_PRIVATE) ? 1 : 0; populate_cache_leaves()
176 ci_leaf_init(this_leaf++, pvt, CACHE_TYPE_DATA, level, cpu); populate_cache_leaves()
177 ci_leaf_init(this_leaf++, pvt, CACHE_TYPE_INST, level, cpu); populate_cache_leaves()
179 ci_leaf_init(this_leaf++, pvt, ctype, level, cpu); populate_cache_leaves()
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| /linux-4.4.14/drivers/s390/crypto/ |
| H A D | zcrypt_cca_key.h | 286 struct cca_pvt_ext_CRT_sec pvt; zcrypt_type6_crt_key() member in struct:__anon8985
314 key->pvt.section_identifier = CCA_PVT_EXT_CRT_SEC_ID_PVT; zcrypt_type6_crt_key()
315 key->pvt.section_length = sizeof(key->pvt) + key_len; zcrypt_type6_crt_key()
316 key->pvt.key_format = CCA_PVT_EXT_CRT_SEC_FMT_CL; zcrypt_type6_crt_key()
317 key->pvt.key_use_flags[0] = CCA_PVT_USAGE_ALL; zcrypt_type6_crt_key()
318 key->pvt.p_len = key->pvt.dp_len = key->pvt.u_len = long_len; zcrypt_type6_crt_key()
319 key->pvt.q_len = key->pvt.dq_len = short_len; zcrypt_type6_crt_key()
320 key->pvt.mod_len = crt->inputdatalength; zcrypt_type6_crt_key()
321 key->pvt.pad_len = pad_len; zcrypt_type6_crt_key()
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| /linux-4.4.14/include/sound/ |
| H A D | compress_driver.h | 140 * @private_data: pointer to DSP pvt data
|
| /linux-4.4.14/sound/soc/intel/atom/sst/ |
| H A D | sst_pvt.c | 338 * sst_assign_pvt_id - assign a pvt id for stream
|
| /linux-4.4.14/drivers/net/xen-netback/ |
| H A D | xenbus.c | 72 seq_printf(m, "rsp prod %u (base) pvt %u (%d) event %u (%d)\n", xenvif_read_io_ring()
99 seq_printf(m, "rsp prod %u (base) pvt %u (%d) event %u (%d)\n\n", xenvif_read_io_ring()
|
| /linux-4.4.14/drivers/usb/serial/ |
| H A D | mos7720.c | 38 #define DRIVER_AUTHOR "Aspire Communications pvt Ltd."
|