Lines Matching refs:pvt
91 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
95 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
96 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
98 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
115 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
118 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
131 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
143 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
144 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
155 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
176 static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) in __set_scrub_rate() argument
204 if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
205 f15h_select_dct(pvt, 0); in __set_scrub_rate()
206 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
207 f15h_select_dct(pvt, 1); in __set_scrub_rate()
208 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
210 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
221 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate() local
224 if (pvt->fam == 0xf) in set_scrub_rate()
227 if (pvt->fam == 0x15) { in set_scrub_rate()
229 if (pvt->model < 0x10) in set_scrub_rate()
230 f15h_select_dct(pvt, 0); in set_scrub_rate()
232 if (pvt->model == 0x60) in set_scrub_rate()
235 return __set_scrub_rate(pvt, bw, min_scrubrate); in set_scrub_rate()
240 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate() local
244 if (pvt->fam == 0x15) { in get_scrub_rate()
246 if (pvt->model < 0x10) in get_scrub_rate()
247 f15h_select_dct(pvt, 0); in get_scrub_rate()
249 if (pvt->model == 0x60) in get_scrub_rate()
250 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
252 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
269 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) in base_limit_match() argument
281 return ((addr >= get_dram_base(pvt, nid)) && in base_limit_match()
282 (addr <= get_dram_limit(pvt, nid))); in base_limit_match()
294 struct amd64_pvt *pvt; in find_mc_by_sys_addr() local
302 pvt = mci->pvt_info; in find_mc_by_sys_addr()
309 intlv_en = dram_intlv_en(pvt, 0); in find_mc_by_sys_addr()
313 if (base_limit_match(pvt, sys_addr, node_id)) in find_mc_by_sys_addr()
329 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) in find_mc_by_sys_addr()
337 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { in find_mc_by_sys_addr()
358 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
364 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
365 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
366 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
375 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
376 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
377 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
378 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
393 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
394 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
397 if (pvt->fam == 0x15) in get_cs_base_and_mask()
414 #define for_each_chip_select(i, dct, pvt) \ argument
415 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
417 #define chip_select_base(i, dct, pvt) \ argument
418 pvt->csels[dct].csbases[i]
420 #define for_each_chip_select_mask(i, dct, pvt) \ argument
421 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
429 struct amd64_pvt *pvt; in input_addr_to_csrow() local
433 pvt = mci->pvt_info; in input_addr_to_csrow()
435 for_each_chip_select(csrow, 0, pvt) { in input_addr_to_csrow()
436 if (!csrow_enabled(csrow, 0, pvt)) in input_addr_to_csrow()
439 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); in input_addr_to_csrow()
446 pvt->mc_node_id); in input_addr_to_csrow()
452 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
476 struct amd64_pvt *pvt = mci->pvt_info; in amd64_get_dram_hole_info() local
479 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in amd64_get_dram_hole_info()
481 pvt->ext_model, pvt->mc_node_id); in amd64_get_dram_hole_info()
486 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in amd64_get_dram_hole_info()
491 if (!dhar_valid(pvt)) { in amd64_get_dram_hole_info()
493 pvt->mc_node_id); in amd64_get_dram_hole_info()
515 *hole_base = dhar_base(pvt); in amd64_get_dram_hole_info()
518 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in amd64_get_dram_hole_info()
519 : k8_dhar_offset(pvt); in amd64_get_dram_hole_info()
522 pvt->mc_node_id, (unsigned long)*hole_base, in amd64_get_dram_hole_info()
560 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr() local
564 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
616 struct amd64_pvt *pvt; in dram_addr_to_input_addr() local
620 pvt = mci->pvt_info; in dram_addr_to_input_addr()
626 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); in dram_addr_to_input_addr()
688 static unsigned long determine_edac_cap(struct amd64_pvt *pvt) in determine_edac_cap() argument
693 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in determine_edac_cap()
697 if (pvt->dclr0 & BIT(bit)) in determine_edac_cap()
705 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) in debug_dump_dramcfg_low() argument
709 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
710 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
726 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
738 static void dump_misc_regs(struct amd64_pvt *pvt) in dump_misc_regs() argument
740 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in dump_misc_regs()
743 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in dump_misc_regs()
746 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in dump_misc_regs()
747 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in dump_misc_regs()
749 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in dump_misc_regs()
751 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in dump_misc_regs()
754 pvt->dhar, dhar_base(pvt), in dump_misc_regs()
755 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in dump_misc_regs()
756 : f10_dhar_offset(pvt)); in dump_misc_regs()
758 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); in dump_misc_regs()
760 debug_display_dimm_sizes(pvt, 0); in dump_misc_regs()
763 if (pvt->fam == 0xf) in dump_misc_regs()
766 debug_display_dimm_sizes(pvt, 1); in dump_misc_regs()
768 amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4")); in dump_misc_regs()
771 if (!dct_ganging_enabled(pvt)) in dump_misc_regs()
772 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in dump_misc_regs()
778 static void prep_chip_selects(struct amd64_pvt *pvt) in prep_chip_selects() argument
780 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in prep_chip_selects()
781 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
782 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in prep_chip_selects()
783 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in prep_chip_selects()
784 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in prep_chip_selects()
785 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in prep_chip_selects()
787 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
788 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in prep_chip_selects()
795 static void read_dct_base_mask(struct amd64_pvt *pvt) in read_dct_base_mask() argument
799 prep_chip_selects(pvt); in read_dct_base_mask()
801 for_each_chip_select(cs, 0, pvt) { in read_dct_base_mask()
804 u32 *base0 = &pvt->csels[0].csbases[cs]; in read_dct_base_mask()
805 u32 *base1 = &pvt->csels[1].csbases[cs]; in read_dct_base_mask()
807 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) in read_dct_base_mask()
811 if (pvt->fam == 0xf) in read_dct_base_mask()
814 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) in read_dct_base_mask()
816 cs, *base1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
820 for_each_chip_select_mask(cs, 0, pvt) { in read_dct_base_mask()
823 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in read_dct_base_mask()
824 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in read_dct_base_mask()
826 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) in read_dct_base_mask()
830 if (pvt->fam == 0xf) in read_dct_base_mask()
833 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) in read_dct_base_mask()
835 cs, *mask1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
840 static void determine_memory_type(struct amd64_pvt *pvt) in determine_memory_type() argument
844 switch (pvt->fam) { in determine_memory_type()
846 if (pvt->ext_model >= K8_REV_F) in determine_memory_type()
849 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in determine_memory_type()
853 if (pvt->dchr0 & DDR3_MODE) in determine_memory_type()
856 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in determine_memory_type()
860 if (pvt->model < 0x60) in determine_memory_type()
872 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); in determine_memory_type()
873 dcsm = pvt->csels[0].csmasks[0]; in determine_memory_type()
876 pvt->dram_type = MEM_DDR4; in determine_memory_type()
877 else if (pvt->dclr0 & BIT(16)) in determine_memory_type()
878 pvt->dram_type = MEM_DDR3; in determine_memory_type()
880 pvt->dram_type = MEM_LRDDR3; in determine_memory_type()
882 pvt->dram_type = MEM_RDDR3; in determine_memory_type()
890 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in determine_memory_type()
891 pvt->dram_type = MEM_EMPTY; in determine_memory_type()
896 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in determine_memory_type()
900 static int k8_early_channel_count(struct amd64_pvt *pvt) in k8_early_channel_count() argument
904 if (pvt->ext_model >= K8_REV_F) in k8_early_channel_count()
906 flag = pvt->dclr0 & WIDTH_128; in k8_early_channel_count()
909 flag = pvt->dclr0 & REVE_WIDTH_128; in k8_early_channel_count()
912 pvt->dclr1 = 0; in k8_early_channel_count()
918 static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) in get_error_address() argument
930 pvt = mci->pvt_info; in get_error_address()
932 if (pvt->fam == 0xf) { in get_error_address()
942 if (pvt->fam == 0x15) { in get_error_address()
951 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
966 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
999 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) in read_dram_base_limit_regs() argument
1007 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1008 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1010 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1013 if (!dram_rw(pvt, range)) in read_dram_base_limit_regs()
1016 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1017 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1020 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1023 nb = node_to_amd_nb(dram_dst_node(pvt, range)); in read_dram_base_limit_regs()
1027 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1029 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1040 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1043 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1045 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1048 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1056 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow() local
1080 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1121 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1124 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1126 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1130 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1176 static int f1x_early_channel_count(struct amd64_pvt *pvt) in f1x_early_channel_count() argument
1181 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) in f1x_early_channel_count()
1200 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); in f1x_early_channel_count()
1275 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1278 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1282 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1291 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1300 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1304 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1308 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1313 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1333 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
1345 static void read_dram_ctl_register(struct amd64_pvt *pvt) in read_dram_ctl_register() argument
1348 if (pvt->fam == 0xf) in read_dram_ctl_register()
1351 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
1353 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
1356 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); in read_dram_ctl_register()
1358 if (!dct_ganging_enabled(pvt)) in read_dram_ctl_register()
1360 (dct_high_range_enabled(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1363 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1364 (dct_memory_cleared(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1368 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1369 dct_sel_interleave_addr(pvt)); in read_dram_ctl_register()
1372 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
1379 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f15_m30h_determine_channel() argument
1393 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_determine_channel()
1410 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f1x_determine_channel() argument
1413 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
1415 if (dct_ganging_enabled(pvt)) in f1x_determine_channel()
1424 if (dct_interleave_enabled(pvt)) { in f1x_determine_channel()
1425 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f1x_determine_channel()
1441 if (dct_high_range_enabled(pvt)) in f1x_determine_channel()
1448 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, in f1x_get_norm_dct_addr() argument
1453 u64 dram_base = get_dram_base(pvt, range); in f1x_get_norm_dct_addr()
1454 u64 hole_off = f10_dhar_offset(pvt); in f1x_get_norm_dct_addr()
1455 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
1470 dct_sel_base_addr < dhar_base(pvt)) && in f1x_get_norm_dct_addr()
1471 dhar_valid(pvt) && in f1x_get_norm_dct_addr()
1486 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) in f1x_get_norm_dct_addr()
1499 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
1503 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
1504 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
1506 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
1507 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
1527 struct amd64_pvt *pvt; in f1x_lookup_addr_in_dct() local
1536 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
1540 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
1541 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
1544 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
1555 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
1559 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
1573 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) in f1x_swap_interleaved_region() argument
1577 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
1579 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
1583 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
1603 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f1x_match_to_this_node() argument
1612 u8 node_id = dram_dst_node(pvt, range); in f1x_match_to_this_node()
1613 u8 intlv_en = dram_intlv_en(pvt, range); in f1x_match_to_this_node()
1614 u32 intlv_sel = dram_intlv_sel(pvt, range); in f1x_match_to_this_node()
1617 range, sys_addr, get_dram_limit(pvt, range)); in f1x_match_to_this_node()
1619 if (dhar_valid(pvt) && in f1x_match_to_this_node()
1620 dhar_base(pvt) <= sys_addr && in f1x_match_to_this_node()
1630 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); in f1x_match_to_this_node()
1632 dct_sel_base = dct_sel_baseaddr(pvt); in f1x_match_to_this_node()
1638 if (dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
1639 !dct_ganging_enabled(pvt) && in f1x_match_to_this_node()
1643 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); in f1x_match_to_this_node()
1645 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, in f1x_match_to_this_node()
1654 if (dct_interleave_enabled(pvt) && in f1x_match_to_this_node()
1655 !dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
1656 !dct_ganging_enabled(pvt)) { in f1x_match_to_this_node()
1658 if (dct_sel_interleave_addr(pvt) != 1) { in f1x_match_to_this_node()
1659 if (dct_sel_interleave_addr(pvt) == 0x3) in f1x_match_to_this_node()
1683 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f15_m30h_match_to_this_node() argument
1693 u64 dhar_offset = f10_dhar_offset(pvt); in f15_m30h_match_to_this_node()
1694 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_match_to_this_node()
1695 u8 node_id = dram_dst_node(pvt, range); in f15_m30h_match_to_this_node()
1696 u8 intlv_en = dram_intlv_en(pvt, range); in f15_m30h_match_to_this_node()
1698 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
1699 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
1705 range, sys_addr, get_dram_limit(pvt, range)); in f15_m30h_match_to_this_node()
1707 if (!(get_dram_base(pvt, range) <= sys_addr) && in f15_m30h_match_to_this_node()
1708 !(get_dram_limit(pvt, range) >= sys_addr)) in f15_m30h_match_to_this_node()
1711 if (dhar_valid(pvt) && in f15_m30h_match_to_this_node()
1712 dhar_base(pvt) <= sys_addr && in f15_m30h_match_to_this_node()
1720 dct_base = (u64) dct_sel_baseaddr(pvt); in f15_m30h_match_to_this_node()
1734 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, in f15_m30h_match_to_this_node()
1774 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
1780 f15h_select_dct(pvt, channel); in f15_m30h_match_to_this_node()
1802 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, in f1x_translate_sysaddr_to_cs() argument
1810 if (!dram_rw(pvt, range)) in f1x_translate_sysaddr_to_cs()
1813 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
1814 cs_found = f15_m30h_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
1818 else if ((get_dram_base(pvt, range) <= sys_addr) && in f1x_translate_sysaddr_to_cs()
1819 (get_dram_limit(pvt, range) >= sys_addr)) { in f1x_translate_sysaddr_to_cs()
1820 cs_found = f1x_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
1839 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow() local
1843 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
1854 if (dct_ganging_enabled(pvt)) in f1x_map_sysaddr_to_csrow()
1862 static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in debug_display_dimm_sizes() argument
1865 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in debug_display_dimm_sizes()
1866 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in debug_display_dimm_sizes()
1868 if (pvt->fam == 0xf) { in debug_display_dimm_sizes()
1870 if (pvt->ext_model < K8_REV_F) in debug_display_dimm_sizes()
1876 if (pvt->fam == 0x10) { in debug_display_dimm_sizes()
1877 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in debug_display_dimm_sizes()
1878 : pvt->dbam0; in debug_display_dimm_sizes()
1879 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? in debug_display_dimm_sizes()
1880 pvt->csels[1].csbases : in debug_display_dimm_sizes()
1881 pvt->csels[0].csbases; in debug_display_dimm_sizes()
1883 dbam = pvt->dbam0; in debug_display_dimm_sizes()
1884 dcsb = pvt->csels[1].csbases; in debug_display_dimm_sizes()
1901 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
1907 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2135 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome() local
2138 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2141 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2142 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2145 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2147 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2151 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2196 struct amd64_pvt *pvt; in decode_bus_error() local
2207 pvt = mci->pvt_info; in decode_bus_error()
2219 sys_addr = get_error_address(pvt, m); in decode_bus_error()
2224 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2233 static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id) in reserve_mc_sibling_devs() argument
2236 pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2); in reserve_mc_sibling_devs()
2237 if (!pvt->F1) { in reserve_mc_sibling_devs()
2245 pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2); in reserve_mc_sibling_devs()
2246 if (!pvt->F3) { in reserve_mc_sibling_devs()
2247 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2248 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2256 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2257 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2258 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2263 static void free_mc_sibling_devs(struct amd64_pvt *pvt) in free_mc_sibling_devs() argument
2265 pci_dev_put(pvt->F1); in free_mc_sibling_devs()
2266 pci_dev_put(pvt->F3); in free_mc_sibling_devs()
2273 static void read_mc_regs(struct amd64_pvt *pvt) in read_mc_regs() argument
2283 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in read_mc_regs()
2284 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in read_mc_regs()
2289 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in read_mc_regs()
2290 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in read_mc_regs()
2294 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in read_mc_regs()
2296 read_dram_ctl_register(pvt); in read_mc_regs()
2302 read_dram_base_limit_regs(pvt, range); in read_mc_regs()
2304 rw = dram_rw(pvt, range); in read_mc_regs()
2310 get_dram_base(pvt, range), in read_mc_regs()
2311 get_dram_limit(pvt, range)); in read_mc_regs()
2314 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", in read_mc_regs()
2317 dram_intlv_sel(pvt, range), in read_mc_regs()
2318 dram_dst_node(pvt, range)); in read_mc_regs()
2321 read_dct_base_mask(pvt); in read_mc_regs()
2323 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in read_mc_regs()
2324 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in read_mc_regs()
2326 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in read_mc_regs()
2328 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in read_mc_regs()
2329 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in read_mc_regs()
2331 if (!dct_ganging_enabled(pvt)) { in read_mc_regs()
2332 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in read_mc_regs()
2333 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in read_mc_regs()
2336 pvt->ecc_sym_sz = 4; in read_mc_regs()
2337 determine_memory_type(pvt); in read_mc_regs()
2338 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in read_mc_regs()
2340 if (pvt->fam >= 0x10) { in read_mc_regs()
2341 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in read_mc_regs()
2343 if (pvt->fam != 0x16) in read_mc_regs()
2344 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in read_mc_regs()
2347 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in read_mc_regs()
2348 pvt->ecc_sym_sz = 8; in read_mc_regs()
2350 dump_misc_regs(pvt); in read_mc_regs()
2387 static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in get_csrow_nr_pages() argument
2390 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in get_csrow_nr_pages()
2402 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, (csrow_nr / 2)) in get_csrow_nr_pages()
2418 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows() local
2426 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in init_csrows()
2428 pvt->nbcfg = val; in init_csrows()
2431 pvt->mc_node_id, val, in init_csrows()
2437 for_each_chip_select(i, 0, pvt) { in init_csrows()
2438 bool row_dct0 = !!csrow_enabled(i, 0, pvt); in init_csrows()
2441 if (pvt->fam != 0xf) in init_csrows()
2442 row_dct1 = !!csrow_enabled(i, 1, pvt); in init_csrows()
2451 pvt->mc_node_id, i); in init_csrows()
2454 nr_pages = get_csrow_nr_pages(pvt, 0, i); in init_csrows()
2459 if (pvt->fam != 0xf && row_dct1) { in init_csrows()
2460 int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i); in init_csrows()
2471 if (pvt->nbcfg & NBCFG_ECC_ENABLE) in init_csrows()
2472 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) ? in init_csrows()
2477 for (j = 0; j < pvt->channel_count; j++) { in init_csrows()
2479 dimm->mtype = pvt->dram_type; in init_csrows()
2687 struct amd64_pvt *pvt = mci->pvt_info; in setup_mci_misc_attrs() local
2692 if (pvt->nbcap & NBCAP_SECDED) in setup_mci_misc_attrs()
2695 if (pvt->nbcap & NBCAP_CHIPKILL) in setup_mci_misc_attrs()
2698 mci->edac_cap = determine_edac_cap(pvt); in setup_mci_misc_attrs()
2702 mci->dev_name = pci_name(pvt->F2); in setup_mci_misc_attrs()
2713 static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) in per_family_init() argument
2717 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
2718 pvt->stepping = boot_cpu_data.x86_mask; in per_family_init()
2719 pvt->model = boot_cpu_data.x86_model; in per_family_init()
2720 pvt->fam = boot_cpu_data.x86; in per_family_init()
2722 switch (pvt->fam) { in per_family_init()
2725 pvt->ops = &family_types[K8_CPUS].ops; in per_family_init()
2730 pvt->ops = &family_types[F10_CPUS].ops; in per_family_init()
2734 if (pvt->model == 0x30) { in per_family_init()
2736 pvt->ops = &family_types[F15_M30H_CPUS].ops; in per_family_init()
2738 } else if (pvt->model == 0x60) { in per_family_init()
2740 pvt->ops = &family_types[F15_M60H_CPUS].ops; in per_family_init()
2745 pvt->ops = &family_types[F15_CPUS].ops; in per_family_init()
2749 if (pvt->model == 0x30) { in per_family_init()
2751 pvt->ops = &family_types[F16_M30H_CPUS].ops; in per_family_init()
2755 pvt->ops = &family_types[F16_CPUS].ops; in per_family_init()
2764 (pvt->fam == 0xf ? in per_family_init()
2765 (pvt->ext_model >= K8_REV_F ? "revF or later " in per_family_init()
2767 : ""), pvt->mc_node_id); in per_family_init()
2783 struct amd64_pvt *pvt = NULL; in init_one_instance() local
2791 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); in init_one_instance()
2792 if (!pvt) in init_one_instance()
2795 pvt->mc_node_id = nid; in init_one_instance()
2796 pvt->F2 = F2; in init_one_instance()
2799 fam_type = per_family_init(pvt); in init_one_instance()
2804 err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id); in init_one_instance()
2808 read_mc_regs(pvt); in init_one_instance()
2816 pvt->channel_count = pvt->ops->early_channel_count(pvt); in init_one_instance()
2817 if (pvt->channel_count < 0) in init_one_instance()
2822 layers[0].size = pvt->csels[0].b_cnt; in init_one_instance()
2838 mci->pvt_info = pvt; in init_one_instance()
2839 mci->pdev = &pvt->F2->dev; in init_one_instance()
2866 free_mc_sibling_devs(pvt); in init_one_instance()
2869 kfree(pvt); in init_one_instance()
2927 struct amd64_pvt *pvt; in remove_one_instance() local
2940 pvt = mci->pvt_info; in remove_one_instance()
2944 free_mc_sibling_devs(pvt); in remove_one_instance()
2956 kfree(pvt); in remove_one_instance()
2988 struct amd64_pvt *pvt; in setup_pci_device() local
2997 pvt = mci->pvt_info; in setup_pci_device()
2998 pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR); in setup_pci_device()