1#include "amd64_edac.h"
2
3#define EDAC_DCT_ATTR_SHOW(reg)						\
4static ssize_t amd64_##reg##_show(struct device *dev,			\
5			       struct device_attribute *mattr,		\
6			       char *data)				\
7{									\
8	struct mem_ctl_info *mci = to_mci(dev);				\
9	struct amd64_pvt *pvt = mci->pvt_info;				\
10		return sprintf(data, "0x%016llx\n", (u64)pvt->reg);	\
11}
12
13EDAC_DCT_ATTR_SHOW(dhar);
14EDAC_DCT_ATTR_SHOW(dbam0);
15EDAC_DCT_ATTR_SHOW(top_mem);
16EDAC_DCT_ATTR_SHOW(top_mem2);
17
18static ssize_t amd64_hole_show(struct device *dev,
19			       struct device_attribute *mattr,
20			       char *data)
21{
22	struct mem_ctl_info *mci = to_mci(dev);
23
24	u64 hole_base = 0;
25	u64 hole_offset = 0;
26	u64 hole_size = 0;
27
28	amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
29
30	return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
31						 hole_size);
32}
33
34/*
35 * update NUM_DBG_ATTRS in case you add new members
36 */
37static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);
38static DEVICE_ATTR(dbam, S_IRUGO, amd64_dbam0_show, NULL);
39static DEVICE_ATTR(topmem, S_IRUGO, amd64_top_mem_show, NULL);
40static DEVICE_ATTR(topmem2, S_IRUGO, amd64_top_mem2_show, NULL);
41static DEVICE_ATTR(dram_hole, S_IRUGO, amd64_hole_show, NULL);
42
43static struct attribute *amd64_edac_dbg_attrs[] = {
44	&dev_attr_dhar.attr,
45	&dev_attr_dbam.attr,
46	&dev_attr_topmem.attr,
47	&dev_attr_topmem2.attr,
48	&dev_attr_dram_hole.attr,
49	NULL
50};
51
52const struct attribute_group amd64_edac_dbg_group = {
53	.attrs = amd64_edac_dbg_attrs,
54};
55