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Searched refs:pinmux (Results 1 – 141 of 141) sorted by relevance

/linux-4.4.14/arch/sh/kernel/cpu/sh4a/
DMakefile39 pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
40 pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
41 pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
42 pinmux-$(CONFIG_CPU_SUBTYPE_SH7734) := pinmux-sh7734.o
43 pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
44 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
45 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
46 pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o
50 obj-$(CONFIG_GPIOLIB) += $(pinmux-y)
/linux-4.4.14/arch/arm64/boot/dts/qcom/
Dmsm8916-pins.dtsi17 pinmux {
29 pinmux {
41 pinmux {
53 pinmux {
65 pinmux {
87 pinmux {
99 pinmux {
121 pinmux {
133 pinmux {
155 pinmux {
[all …]
/linux-4.4.14/arch/sh/kernel/cpu/sh2a/
DMakefile20 pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
21 pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
22 pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o
24 obj-$(CONFIG_GPIOLIB) += $(pinmux-y)
/linux-4.4.14/arch/arm/boot/dts/
Dimx28.dtsi213 fsl,pinmux-ids = <
224 fsl,pinmux-ids = <
235 fsl,pinmux-ids = <
248 fsl,pinmux-ids = <
271 fsl,pinmux-ids = <
281 fsl,pinmux-ids = <
294 fsl,pinmux-ids = <
305 fsl,pinmux-ids = <
318 fsl,pinmux-ids = <
329 fsl,pinmux-ids = <
[all …]
Dat91-sama5d2_xplained.dts251 pinmux = <PIN_PB28__FLEXCOM0_IO0>,
257 pinmux = <PIN_PD12__FLEXCOM4_IO0>,
263 pinmux = <PIN_PD21__TWD0>,
269 pinmux = <PIN_PD4__TWD1>,
275 pinmux = <PIN_PB14__GTXCK>,
290 pinmux = <PIN_PA1__SDMMC0_CMD>,
303 pinmux = <PIN_PA0__SDMMC0_CK>,
313 pinmux = <PIN_PA28__SDMMC1_CMD>,
322 pinmux = <PIN_PA22__SDMMC1_CK>,
329 pinmux = <PIN_PA14__SPI0_SPCK>,
[all …]
Dimx28-cfa10049.dts27 fsl,pinmux-ids = <
37 fsl,pinmux-ids = <
48 fsl,pinmux-ids = <
58 fsl,pinmux-ids = <
68 fsl,pinmux-ids = <
79 fsl,pinmux-ids = <
89 fsl,pinmux-ids = <
102 fsl,pinmux-ids = <
116 fsl,pinmux-ids = <
143 fsl,pinmux-ids = <
[all …]
Dimx23.dtsi141 fsl,pinmux-ids = <
152 fsl,pinmux-ids = <
165 fsl,pinmux-ids = <
176 fsl,pinmux-ids = <
201 fsl,pinmux-ids = <
211 fsl,pinmux-ids = <
226 fsl,pinmux-ids = <
245 fsl,pinmux-ids = <
254 fsl,pinmux-ids = <
264 fsl,pinmux-ids = <
[all …]
Dimx28-eukrea-mbmx28lc.dtsi197 fsl,pinmux-ids = <
207 fsl,pinmux-ids = <
217 fsl,pinmux-ids = <
230 fsl,pinmux-ids = <
240 fsl,pinmux-ids = <
250 fsl,pinmux-ids = <
260 fsl,pinmux-ids = <
270 fsl,pinmux-ids = <
Dimx28-cfa10036.dts28 fsl,pinmux-ids = <
38 fsl,pinmux-ids = <
48 fsl,pinmux-ids = <
58 fsl,pinmux-ids = <
Dspear310.dtsi25 pinmux: pinmux@b4000000 { label
26 compatible = "st,spear310-pinmux";
105 gpio-ranges = <&pinmux 0 0 102>;
Dimx28-cfa10055.dts28 fsl,pinmux-ids = <
41 fsl,pinmux-ids = <
68 fsl,pinmux-ids = <
81 fsl,pinmux-ids = <
Dspear320.dtsi24 pinmux: pinmux@b3000000 { label
25 compatible = "st,spear320-pinmux";
133 gpio-ranges = <&pinmux 0 0 102>;
Dimx28-tx28.dts507 fsl,pinmux-ids = <
516 fsl,pinmux-ids = <
527 fsl,pinmux-ids = <
536 fsl,pinmux-ids = <
568 fsl,pinmux-ids = <
578 fsl,pinmux-ids = <
595 fsl,pinmux-ids = <
604 fsl,pinmux-ids = <
618 fsl,pinmux-ids = <
628 fsl,pinmux-ids = <
[all …]
Dimx28-cfa10056.dts27 fsl,pinmux-ids = <
40 fsl,pinmux-ids = <
53 fsl,pinmux-ids = <
Dimx28-apx4devkit.dts42 fsl,pinmux-ids = <
58 fsl,pinmux-ids = <
71 fsl,pinmux-ids = <
85 fsl,pinmux-ids = <
Dspear1340.dtsi91 pinmux: pinmux@e0700000 { label
92 compatible = "st,spear1340-pinmux";
161 gpio-ranges = <&pinmux 0 0 252>;
Dtegra20-iris-512.dts20 pinmux@70000014 {
21 state_default: pinmux {
Dimx28-cfa10057.dts28 fsl,pinmux-ids = <
38 fsl,pinmux-ids = <
65 fsl,pinmux-ids = <
Dspear320-evb.dts28 pinmux@b3000000 {
29 st,pinmux-mode = <4>;
33 state_default: pinmux {
Dspear300-evb.dts28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
33 state_default: pinmux {
Dimx28-cfa10037.dts27 fsl,pinmux-ids = <
37 fsl,pinmux-ids = <
Dspear300.dtsi24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
Dimx28-apf28dev.dts43 fsl,pinmux-ids = <
60 fsl,pinmux-ids = <
73 fsl,pinmux-ids = <
Dimx28-duckbill.dts41 fsl,pinmux-ids = <
51 fsl,pinmux-ids = <
Dimx28-evk.dts72 fsl,pinmux-ids = <
89 fsl,pinmux-ids = <
99 fsl,pinmux-ids = <
110 fsl,pinmux-ids = <
Dimx23-olinuxino.dts43 fsl,pinmux-ids = <
53 fsl,pinmux-ids = <
Dimx28-m28cu3.dts72 fsl,pinmux-ids = <
85 fsl,pinmux-ids = <
100 fsl,pinmux-ids = <
Dimx28-cfa10058.dts28 fsl,pinmux-ids = <
38 fsl,pinmux-ids = <
Dspear1310.dtsi176 pinmux: pinmux@e0700000 { label
177 compatible = "st,spear1310-pinmux";
302 gpio-ranges = <&pinmux 0 0 246>;
Dspear320-hmi.dts28 pinmux@b3000000 {
29 st,pinmux-mode = <4>;
33 state_default: pinmux {
Dspear310-evb.dts28 pinmux@b4000000 {
32 state_default: pinmux {
Dqcom-ipq8064-ap148.dts26 pinmux@800000 {
Dimx28-m28evk.dts56 fsl,pinmux-ids = <
70 fsl,pinmux-ids = <
Domap34xx.dtsi32 omap3_pmx_core2: pinmux@480025d8 {
Dimx23-stmp378x_devb.dts41 fsl,pinmux-ids = <
Dimx28-eukrea-mbmx287lc.dts43 fsl,pinmux-ids = <
Dimx28-eukrea-mbmx283lc.dts63 fsl,pinmux-ids = <
Dam3517.dtsi64 omap3_pmx_core2: pinmux@480025d8 {
Dbcm-cygnus.dtsi95 compatible = "brcm,cygnus-pinmux";
251 pinmux = <&pinctrl>;
Dspear1310-evb.dts28 pinmux@e0700000 {
32 state_default: pinmux {
Domap36xx.dtsi64 omap3_pmx_core2: pinmux@480025a0 {
Dimx28-sps1.dts31 fsl,pinmux-ids = <
Dimx23-evk.dts47 fsl,pinmux-ids = <
Dtegra114.dtsi238 gpio-ranges = <&pinmux 0 0 246>;
248 pinmux: pinmux@70000868 { label
249 compatible = "nvidia,tegra114-pinmux";
Dtegra20.dtsi248 gpio-ranges = <&pinmux 0 0 224>;
258 pinmux: pinmux@70000014 { label
259 compatible = "nvidia,tegra20-pinmux";
Dspear1340-evb.dts28 pinmux@e0700000 {
32 state_default: pinmux {
Dtegra30-colibri.dtsi27 pinmux@70000868 {
31 state_default: pinmux {
Dtegra20-trimslice.dts33 pinmux@70000014 {
37 state_default: pinmux {
Dtegra30.dtsi353 gpio-ranges = <&pinmux 0 0 248>;
363 pinmux: pinmux@70000868 { label
364 compatible = "nvidia,tegra30-pinmux";
Dtegra20-tamonten.dtsi28 pinmux@70000014 {
32 state_default: pinmux {
Domap2420.dtsi43 omap2420_pmx: pinmux@30 {
Dtegra20-colibri-512.dtsi27 pinmux@70000014 {
31 state_default: pinmux {
Dtegra20-paz00.dts42 pinmux@70000014 {
46 state_default: pinmux {
Dtegra124.dtsi262 gpio-ranges = <&pinmux 0 0 251>;
313 pinmux: pinmux@0,70000868 { label
314 compatible = "nvidia,tegra124-pinmux";
Dtegra114-dalmore.dts54 pinmux@70000868 {
58 state_default: pinmux {
1066 pinmux {
1071 palmas_default: pinmux {
Dda850-evm.dts18 pmx_core: pinmux@1c14120 {
Dhi3620.dtsi535 pmx0: pinmux@803000 {
556 pmx1: pinmux@803800 {
Dtegra20-whistler.dts33 pinmux@70000014 {
37 state_default: pinmux {
Dtegra20-ventana.dts41 pinmux@70000014 {
45 state_default: pinmux {
Dtegra30-cardhu.dtsi77 pinmux@70000868 {
81 state_default: pinmux {
Dtegra30-apalis.dtsi46 pinmux@70000868 {
50 state_default: pinmux {
Dtegra124-venice2.dts54 pinmux: pinmux@0,70000868 { label
658 as3722_default: pinmux {
Dda850.dtsi34 pmx_core: pinmux@1c14120 {
Ddm814x.dtsi206 pincntl: pinmux@800 {
Dqcom-ipq8064.dtsi93 qcom_pinmux: pinmux@800000 {
Domap2430.dtsi43 omap2430_pmx: pinmux@30 {
Dtegra124-jetson-tk1.dts64 pinmux: pinmux@0,70000868 { label
68 state_boot: pinmux {
1442 as3722_default: pinmux {
1666 padctl_default: pinmux {
Dhi3620-hi4511.dts68 pmx0: pinmux@803000 {
315 pmx1: pinmux@803800 {
Domap3.dtsi103 omap3_pmx_core: pinmux@30 {
142 omap3_pmx_wkup: pinmux@a00 {
Dtegra20-harmony.dts42 pinmux@70000014 {
46 state_default: pinmux {
Dtegra20-seaboard.dts42 pinmux@70000014 {
46 state_default: pinmux {
Ddm816x.dtsi89 dm816x_pinmux: pinmux@800 {
Domap4.dtsi181 omap4_pmx_core: pinmux@40 {
253 omap4_pmx_wkup: pinmux@1e040 {
Dtegra114-roth.dts51 pinmux@70000868 {
55 state_default: pinmux {
Domap5.dtsi170 omap5_pmx_core: pinmux@40 {
269 omap5_pmx_wkup: pinmux@c840 {
Dtegra124-nyan.dtsi119 as3722_default: pinmux {
Dam33xx.dtsi135 am33xx_pinmux: pinmux@800 {
Dr8a7791.dtsi458 /* doesn't need pinmux */
470 /* doesn't need pinmux */
Dtegra30-beaver.dts60 pinmux@70000868 {
64 state_default: pinmux {
Dam4372.dtsi142 am43xx_pinmux: pinmux@800 {
Dtegra124-nyan-big.dts29 pinmux@0,70000868 {
Dtegra124-nyan-blaze.dts25 pinmux@0,70000868 {
Ddra7.dtsi142 dra7_pmx_core: pinmux@1400 {
/linux-4.4.14/drivers/mfd/
Dsi476x-i2c.c50 core->pinmux.dclk, in si476x_core_config_pinmux()
51 core->pinmux.dfs, in si476x_core_config_pinmux()
52 core->pinmux.dout, in si476x_core_config_pinmux()
53 core->pinmux.xout); in si476x_core_config_pinmux()
62 core->pinmux.iqclk, in si476x_core_config_pinmux()
63 core->pinmux.iqfs, in si476x_core_config_pinmux()
64 core->pinmux.iout, in si476x_core_config_pinmux()
65 core->pinmux.qout); in si476x_core_config_pinmux()
74 core->pinmux.icin, in si476x_core_config_pinmux()
75 core->pinmux.icip, in si476x_core_config_pinmux()
[all …]
Dsi476x-cmd.c1079 const bool intsel = (core->pinmux.a1 == SI476X_A1_IRQ); in si476x_core_cmd_power_up_a10()
1102 const bool intsel = (core->pinmux.a1 == SI476X_A1_IRQ); in si476x_core_cmd_power_up_a20()
/linux-4.4.14/drivers/pinctrl/qcom/
DKconfig15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
31 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
39 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
47 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
55 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
63 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
82 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
94 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
/linux-4.4.14/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-pinmux.txt1 NVIDIA Tegra124 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
13 -- second entry - the pinmux registers
116 pinmux: pinmux {
117 compatible = "nvidia,tegra124-pinmux";
123 Example pinmux entries:
126 sdmmc4_default: pinmux {
Dpinctrl-mt65xx.txt11 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
47 pinmux = <PIN_NUMBER_PINMUX>;
52 - pinmux: integer array, represents gpio pin number and mux setting.
101 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
109 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
117 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
122 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
129 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
135 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
142 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
Datmel,at91-pio4-pinctrl.txt26 pinmux = <PIN_NUMBER_PINMUX>;
31 - pinmux: integer array. Each integer represents a pin number plus mux and
60 pinmux = <PIN_PD21__TWD0>,
66 pinmux = <PIN_PB0>,
73 pinmux = <PIN_PA28__SDMMC1_CMD>,
82 pinmux = <PIN_PA22__SDMMC1_CK>,
Dnvidia,tegra114-pinmux.txt1 NVIDIA Tegra114 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
13 be pinmux register address.
96 pinmux: pinmux {
97 compatible = "nvidia,tegra114-pinmux";
105 sdmmc4_default: pinmux {
Dpinctrl-single.txt10 - pinctrl-single,register-width : pinmux register access width in bits
12 - pinctrl-single,function-mask : mask of allowed pinmux function bits
13 in the pinmux register
25 drive strength in the pinmux register. They're value of drive strength
32 input bias pullup in the pinmux register.
38 input bias pulldown in the pinmux register.
54 input schmitt in the pinmux register. In some silicons, there're two input
55 schmitt value (rising-edge & falling-edge) in the pinmux register.
61 configure input schmitt enable or disable in the pinmux register.
115 Optional sub-node: In case some pins could be configured as GPIO in the pinmux
[all …]
Dxlnx,zynq-pinctrl.txt18 Each configuration node can consist of multiple nodes describing the pinmux and
19 pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
24 Required properties for pinmux nodes are:
25 - groups: A list of pinmux groups.
26 - function: The name of a pinmux function to activate for the specified set
32 - groups: A list of pinmux groups.
35 to specify in a pinmux subnode:
Dpinctrl_spear.txt1 ST Microelectronics, SPEAr pinmux controller
4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
35 SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each
Dbrcm,cygnus-pinmux.txt9 Must be "brcm,cygnus-pinmux"
28 pinmux: pinmux@0x0301d0c8 {
29 compatible = "brcm,cygnus-pinmux";
Dnvidia,tegra210-pinmux.txt1 NVIDIA Tegra210 pinmux controller
4 - compatible: "nvidia,tegra210-pinmux"
7 - second entry: The PINMUX_AUX_* registers (pinmux)
83 These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property
129 use when configuring the pinmux.
146 pinmux: pinmux@70000800 {
147 compatible = "nvidia,tegra210-pinmux";
154 state_boot: pinmux {
Dmeson,pinctrl.txt1 == Amlogic Meson pinmux controller ==
28 configuration for a pin or a group. Those nodes can be pinmux nodes or
31 Required properties for pinmux nodes are:
32 - groups: a list of pinmux groups. The list of all available groups
Dnvidia,tegra30-pinmux.txt1 NVIDIA Tegra30 pinmux controller
4 as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
9 - compatible: "nvidia,tegra30-pinmux"
109 compatible = "nvidia,tegra30-pinmux";
117 sdmmc4_default: pinmux {
Dlantiq,pinctrl-xway.txt1 Lantiq XWAY pinmux controller
5 - reg: Should contain the physical address and length of the gpio/pinmux
72 gpio: pinmux@E100B10 {
81 state_default: pinmux {
Dfsl,mxs-pinctrl.txt42 - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
87 fsl,pinmux-ids = <
106 fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>;
111 fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>;
124 Valid values for i.MX28/i.MX23 pinmux-id are defined in
Dlantiq,pinctrl-falcon.txt1 Lantiq FALCON pinmux controller
5 - reg: Should contain the physical address and length of the gpio/pinmux
65 state_default: pinmux {
Dpinctrl-sirf.txt1 CSR SiRFprimaII pinmux controller
16 SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes.
Dpinctrl-atlas7.txt1 CSR SiRFatlas7 pinmux controller
63 SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes.
Dnvidia,tegra20-pinmux.txt1 NVIDIA Tegra20 pinmux controller
4 - compatible: "nvidia,tegra20-pinmux"
63 or groups. See the Tegra TRM and various pinmux spreadsheets for complete
120 compatible = "nvidia,tegra20-pinmux";
Dbrcm,bcm2835-gpio.txt1 Broadcom BCM2835 GPIO (and pinmux) controller
4 controller, and pinmux/control device.
Dnvidia,tegra124-xusb-padctl.txt30 Child nodes contain the pinmux configurations following the conventions from
109 padctl_default: pinmux {
Dpinctrl-vt8500.txt1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
Dbrcm,bcm11351-pinctrl.txt164 - setting pinmux to "alt1"
176 - setting pinmux to "alt2"
185 - setting pinmux to "alt3"
Dste,abx500.txt1 ST Ericsson abx500 pinmux controller
Dqcom,ipq8064-pinctrl.txt64 pinmux: pinctrl@800000 {
Dpinctrl-palmas.txt75 palmas_pins_state: pinmux {
Dste,nomadik.txt1 ST Ericsson Nomadik pinmux controller
Dfsl,imx-pinctrl.txt47 what pinmux functions this SoC supports.
Datmel,at91-pinctrl.txt107 what pinmux functions this SoC supports.
Drockchip,pinctrl.txt19 defined as gpio sub-nodes of the pinmux controller.
Dimg,pistachio-pinctrl.txt5 interrupt controller, and pinmux + pinconf device. The system ("east") pin
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/
Dstartup.inc43 move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
45 move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
52 move.d REG_ADDR(pinmux, regi_pinmux, rw_hwprot), $r1
54 btstq REG_BIT(pinmux, rw_hwprot, eth), $r0
56 btstq REG_BIT(pinmux, rw_hwprot, eth_mdio), $r0
58 btstq REG_BIT(pinmux, rw_hwprot, geth), $r0
60 move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
/linux-4.4.14/arch/arm64/boot/dts/mediatek/
Dmt8173-evb.dts97 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
111 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
116 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
123 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
134 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
140 pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>;
147 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
162 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
168 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
175 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
[all …]
Dmt8173.dtsi185 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
193 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
201 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
209 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
217 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
225 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
/linux-4.4.14/arch/cris/arch-v32/mach-fs/
Dpinmux.c58 reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); in crisv32_pinmux_init()
60 REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); in crisv32_pinmux_init()
63 REG_WR(pinmux, regi_pinmux, rw_pa, pa); in crisv32_pinmux_init()
107 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_alloc_fixed()
169 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_alloc_fixed()
242 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_dealloc_fixed()
304 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_dealloc_fixed()
DMakefile5 obj-y := dma.o pinmux.o arbiter.o
/linux-4.4.14/arch/sh/kernel/cpu/sh3/
DMakefile30 pinmux-$(CONFIG_CPU_SUBTYPE_SH7720) := pinmux-sh7720.o
33 obj-$(CONFIG_GPIOLIB) += $(pinmux-y)
/linux-4.4.14/arch/cris/arch-v32/mach-a3/
Dpinmux.c38 REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); in crisv32_pinmux_init()
98 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_alloc_fixed()
203 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_alloc_fixed()
275 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in crisv32_pinmux_dealloc_fixed()
362 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_dealloc_fixed()
DMakefile5 obj-y := dma.o pinmux.o arbiter.o
/linux-4.4.14/Documentation/devicetree/bindings/input/touchscreen/
Dcolibri-vf50-ts.txt13 - pinctrl-0: pinctrl node for pen/touch detection state pinmux
14 - pinctrl-1: pinctrl node for X/Y and pressure measurement (ADC) state pinmux
/linux-4.4.14/arch/mips/boot/dts/lantiq/
Deasy50712.dts54 gpio: pinmux@E100B10 {
63 state_default: pinmux {
/linux-4.4.14/arch/sh/boards/mach-highlander/
DMakefile7 obj-$(CONFIG_SH_R7785RP) += irq-r7785rp.o pinmux-r7785rp.o
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Dmarvell,berlin.txt58 individual registers dealing with pinmux, padmux, clock, reset, and secondary
74 individual registers dealing with pinmux, padmux, and reset.
/linux-4.4.14/arch/cris/boot/compressed/
Dmisc.c301 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); in decompress_kernel()
323 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in decompress_kernel()
/linux-4.4.14/Documentation/
Dpinctrl.txt453 different pins by pinmux settings.
463 The purpose of the pinmux functionality in the pin controller subsystem is to
464 abstract and provide pinmux settings to the devices you choose to instantiate
474 identify three pinmux functions, one for spi, one for i2c and one for mmc.
495 and their machine-specific particulars are kept inside the pinmux driver,
516 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
554 by inspecting available pinmux hardware, and a necessary assumption since we
555 expect pinmux drivers to present *all* possible function vs pin group mappings
562 The pinmux core takes care of preventing conflicts on pins and calling
565 It is the responsibility of the pinmux driver to impose further restrictions
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Defm32-spi.txt14 bitfield to configure the pinmux for the device, see
/linux-4.4.14/drivers/soc/tegra/
Dpmc.c733 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; in tegra_pmc_init_tsense_reset() local
767 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
768 pinmux = 0; in tegra_pmc_init_tsense_reset()
780 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; in tegra_pmc_init_tsense_reset()
/linux-4.4.14/include/linux/mfd/
Dsi476x-platform.h263 struct si476x_pinmux pinmux; member
Dsi476x-core.h153 struct si476x_pinmux pinmux; member
/linux-4.4.14/drivers/pinctrl/
DMakefile6 obj-$(CONFIG_PINMUX) += pinmux.o
DKconfig44 functionality. This driver supports the pinmux, push-pull and
237 functionality. This driver supports the pinmux, push-pull and
/linux-4.4.14/Documentation/devicetree/bindings/arm/omap/
Dctrl.txt43 omap3_pmx_core: pinmux@30 {
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
Das3722.txt36 Following are properties which is needed if GPIO and pinmux functionality
152 as3722_default: pinmux {
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/
DMakefile60 REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
/linux-4.4.14/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.txt67 - nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
/linux-4.4.14/arch/powerpc/boot/dts/
Dmpc5125twr.dts234 // correct pinmux config and fix USB3320 ulpi dependency
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dsamsung-fimc.txt37 camera port pinmux at runtime. The "idle" state should configure both the camera