1Marvell Berlin SoC Family Device Tree Bindings
2---------------------------------------------------------------
3
4Work in progress statement:
5
6Device tree files and bindings applying to Marvell Berlin SoCs and boards are
7considered "unstable". Any Marvell Berlin device tree binding may change at any
8time. Be sure to use a device tree binary and a kernel image generated from the
9same source tree.
10
11Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
12stable binding/ABI.
13
14---------------------------------------------------------------
15
16Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
17shall have the following properties:
18
19* Required root node properties:
20compatible: must contain "marvell,berlin"
21
22In addition, the above compatible shall be extended with the specific
23SoC and board used. Currently known SoC compatibles are:
24    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
25    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
26    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
27    "marvell,berlin2q"     for Marvell Armada 1500-pro (BG2Q, 88DE3114)
28    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
29
30* Example:
31
32/ {
33	model = "Sony NSZ-GS7";
34	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
35
36	...
37}
38
39* Marvell Berlin CPU control bindings
40
41CPU control register allows various operations on CPUs, like resetting them
42independently.
43
44Required properties:
45- compatible: should be "marvell,berlin-cpu-ctrl"
46- reg: address and length of the register set
47
48Example:
49
50cpu-ctrl@f7dd0000 {
51	compatible = "marvell,berlin-cpu-ctrl";
52	reg = <0xf7dd0000 0x10000>;
53};
54
55* Marvell Berlin2 chip control binding
56
57Marvell Berlin SoCs have a chip control register set providing several
58individual registers dealing with pinmux, padmux, clock, reset, and secondary
59CPU boot address. Unfortunately, the individual registers are spread among the
60chip control registers, so there should be a single DT node only providing the
61different functions which are described below.
62
63Required properties:
64- compatible:
65	* the first and second values must be:
66		"simple-mfd", "syscon"
67- reg: address and length of following register sets for
68  BG2/BG2CD: chip control register set
69  BG2Q: chip control register set and cpu pll registers
70
71* Marvell Berlin2 system control binding
72
73Marvell Berlin SoCs have a system control register set providing several
74individual registers dealing with pinmux, padmux, and reset.
75
76Required properties:
77- compatible:
78	* the first and second values must be:
79		"simple-mfd", "syscon"
80- reg: address and length of the system control register set
81
82Example:
83
84chip: chip-control@ea0000 {
85	compatible = "simple-mfd", "syscon";
86	reg = <0xea0000 0x400>;
87
88	/* sub-device nodes */
89};
90
91sysctrl: system-controller@d000 {
92	compatible = "simple-mfd", "syscon";
93	reg = <0xd000 0x100>;
94
95	/* sub-device nodes */
96};
97