1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15/dts-v1/; 16#include "mt8173.dtsi" 17 18/ { 19 model = "MediaTek MT8173 evaluation board"; 20 compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 serial3 = &uart3; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0 0x40000000 0 0x80000000>; 32 }; 33 34 chosen { }; 35}; 36 37&i2c1 { 38 status = "okay"; 39 40 buck: da9211@68 { 41 compatible = "dlg,da9211"; 42 reg = <0x68>; 43 44 regulators { 45 da9211_vcpu_reg: BUCKA { 46 regulator-name = "VBUCKA"; 47 regulator-min-microvolt = < 700000>; 48 regulator-max-microvolt = <1310000>; 49 regulator-min-microamp = <2000000>; 50 regulator-max-microamp = <4400000>; 51 regulator-ramp-delay = <10000>; 52 regulator-always-on; 53 }; 54 55 da9211_vgpu_reg: BUCKB { 56 regulator-name = "VBUCKB"; 57 regulator-min-microvolt = < 700000>; 58 regulator-max-microvolt = <1310000>; 59 regulator-min-microamp = <2000000>; 60 regulator-max-microamp = <3000000>; 61 regulator-ramp-delay = <10000>; 62 }; 63 }; 64 }; 65}; 66 67&mmc0 { 68 status = "okay"; 69 pinctrl-names = "default", "state_uhs"; 70 pinctrl-0 = <&mmc0_pins_default>; 71 pinctrl-1 = <&mmc0_pins_uhs>; 72 bus-width = <8>; 73 max-frequency = <50000000>; 74 cap-mmc-highspeed; 75 vmmc-supply = <&mt6397_vemc_3v3_reg>; 76 vqmmc-supply = <&mt6397_vio18_reg>; 77 non-removable; 78}; 79 80&mmc1 { 81 status = "okay"; 82 pinctrl-names = "default", "state_uhs"; 83 pinctrl-0 = <&mmc1_pins_default>; 84 pinctrl-1 = <&mmc1_pins_uhs>; 85 bus-width = <4>; 86 max-frequency = <50000000>; 87 cap-sd-highspeed; 88 sd-uhs-sdr25; 89 cd-gpios = <&pio 132 0>; 90 vmmc-supply = <&mt6397_vmch_reg>; 91 vqmmc-supply = <&mt6397_vmc_reg>; 92}; 93 94&pio { 95 mmc0_pins_default: mmc0default { 96 pins_cmd_dat { 97 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 98 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 99 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, 100 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, 101 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, 102 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, 103 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, 104 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, 105 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; 106 input-enable; 107 bias-pull-up; 108 }; 109 110 pins_clk { 111 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 112 bias-pull-down; 113 }; 114 115 pins_rst { 116 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 117 bias-pull-up; 118 }; 119 }; 120 121 mmc1_pins_default: mmc1default { 122 pins_cmd_dat { 123 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 124 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 125 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 126 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 127 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; 128 input-enable; 129 drive-strength = <MTK_DRIVE_4mA>; 130 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 131 }; 132 133 pins_clk { 134 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 135 bias-pull-down; 136 drive-strength = <MTK_DRIVE_4mA>; 137 }; 138 139 pins_insert { 140 pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>; 141 bias-pull-up; 142 }; 143 }; 144 145 mmc0_pins_uhs: mmc0 { 146 pins_cmd_dat { 147 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 148 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 149 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, 150 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, 151 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, 152 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, 153 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, 154 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, 155 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; 156 input-enable; 157 drive-strength = <MTK_DRIVE_2mA>; 158 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 159 }; 160 161 pins_clk { 162 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 163 drive-strength = <MTK_DRIVE_2mA>; 164 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 165 }; 166 167 pins_rst { 168 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 169 bias-pull-up; 170 }; 171 }; 172 173 mmc1_pins_uhs: mmc1 { 174 pins_cmd_dat { 175 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 176 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 177 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 178 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 179 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; 180 input-enable; 181 drive-strength = <MTK_DRIVE_4mA>; 182 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 183 }; 184 185 pins_clk { 186 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 187 drive-strength = <MTK_DRIVE_4mA>; 188 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 189 }; 190 }; 191}; 192 193&pwrap { 194 pmic: mt6397 { 195 compatible = "mediatek,mt6397"; 196 interrupt-parent = <&pio>; 197 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 201 mt6397regulator: mt6397regulator { 202 compatible = "mediatek,mt6397-regulator"; 203 204 mt6397_vpca15_reg: buck_vpca15 { 205 regulator-compatible = "buck_vpca15"; 206 regulator-name = "vpca15"; 207 regulator-min-microvolt = < 700000>; 208 regulator-max-microvolt = <1350000>; 209 regulator-ramp-delay = <12500>; 210 regulator-always-on; 211 }; 212 213 mt6397_vpca7_reg: buck_vpca7 { 214 regulator-compatible = "buck_vpca7"; 215 regulator-name = "vpca7"; 216 regulator-min-microvolt = < 700000>; 217 regulator-max-microvolt = <1350000>; 218 regulator-ramp-delay = <12500>; 219 regulator-enable-ramp-delay = <115>; 220 }; 221 222 mt6397_vsramca15_reg: buck_vsramca15 { 223 regulator-compatible = "buck_vsramca15"; 224 regulator-name = "vsramca15"; 225 regulator-min-microvolt = < 700000>; 226 regulator-max-microvolt = <1350000>; 227 regulator-ramp-delay = <12500>; 228 regulator-always-on; 229 }; 230 231 mt6397_vsramca7_reg: buck_vsramca7 { 232 regulator-compatible = "buck_vsramca7"; 233 regulator-name = "vsramca7"; 234 regulator-min-microvolt = < 700000>; 235 regulator-max-microvolt = <1350000>; 236 regulator-ramp-delay = <12500>; 237 regulator-always-on; 238 }; 239 240 mt6397_vcore_reg: buck_vcore { 241 regulator-compatible = "buck_vcore"; 242 regulator-name = "vcore"; 243 regulator-min-microvolt = < 700000>; 244 regulator-max-microvolt = <1350000>; 245 regulator-ramp-delay = <12500>; 246 regulator-always-on; 247 }; 248 249 mt6397_vgpu_reg: buck_vgpu { 250 regulator-compatible = "buck_vgpu"; 251 regulator-name = "vgpu"; 252 regulator-min-microvolt = < 700000>; 253 regulator-max-microvolt = <1350000>; 254 regulator-ramp-delay = <12500>; 255 regulator-enable-ramp-delay = <115>; 256 }; 257 258 mt6397_vdrm_reg: buck_vdrm { 259 regulator-compatible = "buck_vdrm"; 260 regulator-name = "vdrm"; 261 regulator-min-microvolt = <1200000>; 262 regulator-max-microvolt = <1400000>; 263 regulator-ramp-delay = <12500>; 264 regulator-always-on; 265 }; 266 267 mt6397_vio18_reg: buck_vio18 { 268 regulator-compatible = "buck_vio18"; 269 regulator-name = "vio18"; 270 regulator-min-microvolt = <1620000>; 271 regulator-max-microvolt = <1980000>; 272 regulator-ramp-delay = <12500>; 273 regulator-always-on; 274 }; 275 276 mt6397_vtcxo_reg: ldo_vtcxo { 277 regulator-compatible = "ldo_vtcxo"; 278 regulator-name = "vtcxo"; 279 regulator-always-on; 280 }; 281 282 mt6397_va28_reg: ldo_va28 { 283 regulator-compatible = "ldo_va28"; 284 regulator-name = "va28"; 285 regulator-always-on; 286 }; 287 288 mt6397_vcama_reg: ldo_vcama { 289 regulator-compatible = "ldo_vcama"; 290 regulator-name = "vcama"; 291 regulator-min-microvolt = <1500000>; 292 regulator-max-microvolt = <2800000>; 293 regulator-enable-ramp-delay = <218>; 294 }; 295 296 mt6397_vio28_reg: ldo_vio28 { 297 regulator-compatible = "ldo_vio28"; 298 regulator-name = "vio28"; 299 regulator-always-on; 300 }; 301 302 mt6397_vusb_reg: ldo_vusb { 303 regulator-compatible = "ldo_vusb"; 304 regulator-name = "vusb"; 305 }; 306 307 mt6397_vmc_reg: ldo_vmc { 308 regulator-compatible = "ldo_vmc"; 309 regulator-name = "vmc"; 310 regulator-min-microvolt = <1800000>; 311 regulator-max-microvolt = <3300000>; 312 regulator-enable-ramp-delay = <218>; 313 }; 314 315 mt6397_vmch_reg: ldo_vmch { 316 regulator-compatible = "ldo_vmch"; 317 regulator-name = "vmch"; 318 regulator-min-microvolt = <3000000>; 319 regulator-max-microvolt = <3300000>; 320 regulator-enable-ramp-delay = <218>; 321 }; 322 323 mt6397_vemc_3v3_reg: ldo_vemc3v3 { 324 regulator-compatible = "ldo_vemc3v3"; 325 regulator-name = "vemc_3v3"; 326 regulator-min-microvolt = <3000000>; 327 regulator-max-microvolt = <3300000>; 328 regulator-enable-ramp-delay = <218>; 329 }; 330 331 mt6397_vgp1_reg: ldo_vgp1 { 332 regulator-compatible = "ldo_vgp1"; 333 regulator-name = "vcamd"; 334 regulator-min-microvolt = <1220000>; 335 regulator-max-microvolt = <3300000>; 336 regulator-enable-ramp-delay = <240>; 337 }; 338 339 mt6397_vgp2_reg: ldo_vgp2 { 340 regulator-compatible = "ldo_vgp2"; 341 regulator-name = "vcamio"; 342 regulator-min-microvolt = <1000000>; 343 regulator-max-microvolt = <3300000>; 344 regulator-enable-ramp-delay = <218>; 345 }; 346 347 mt6397_vgp3_reg: ldo_vgp3 { 348 regulator-compatible = "ldo_vgp3"; 349 regulator-name = "vcamaf"; 350 regulator-min-microvolt = <1200000>; 351 regulator-max-microvolt = <3300000>; 352 regulator-enable-ramp-delay = <218>; 353 }; 354 355 mt6397_vgp4_reg: ldo_vgp4 { 356 regulator-compatible = "ldo_vgp4"; 357 regulator-name = "vgp4"; 358 regulator-min-microvolt = <1200000>; 359 regulator-max-microvolt = <3300000>; 360 regulator-enable-ramp-delay = <218>; 361 }; 362 363 mt6397_vgp5_reg: ldo_vgp5 { 364 regulator-compatible = "ldo_vgp5"; 365 regulator-name = "vgp5"; 366 regulator-min-microvolt = <1200000>; 367 regulator-max-microvolt = <3000000>; 368 regulator-enable-ramp-delay = <218>; 369 }; 370 371 mt6397_vgp6_reg: ldo_vgp6 { 372 regulator-compatible = "ldo_vgp6"; 373 regulator-name = "vgp6"; 374 regulator-min-microvolt = <1200000>; 375 regulator-max-microvolt = <3300000>; 376 regulator-enable-ramp-delay = <218>; 377 }; 378 379 mt6397_vibr_reg: ldo_vibr { 380 regulator-compatible = "ldo_vibr"; 381 regulator-name = "vibr"; 382 regulator-min-microvolt = <1300000>; 383 regulator-max-microvolt = <3300000>; 384 regulator-enable-ramp-delay = <218>; 385 }; 386 }; 387 }; 388}; 389 390&pio { 391 spi_pins_a: spi0 { 392 pins_spi { 393 pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>, 394 <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>, 395 <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>, 396 <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>; 397 }; 398 }; 399}; 400 401&spi { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&spi_pins_a>; 404 mediatek,pad-select = <0>; 405 status = "okay"; 406}; 407 408&uart0 { 409 status = "okay"; 410}; 411