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Searched refs:parents (Results 1 – 105 of 105) sorted by relevance

/linux-4.4.14/drivers/clk/ingenic/
Djz4780-cgu.c248 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
254 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
260 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
266 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
276 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
284 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
291 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
298 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
304 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
310 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
[all …]
Djz4740-cgu.c69 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
92 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
98 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
104 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
116 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
122 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
129 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
135 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
143 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
[all …]
Dcgu.c255 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
284 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
512 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
559 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
562 if (clk_info->parents[i] == -1) in ingenic_register_clock()
565 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
574 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
576 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
Dcgu.h151 int parents[4]; member
/linux-4.4.14/drivers/clk/st/
Dclkgen-mux.c28 const char **parents; in clkgen_mux_get_parents() local
35 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
36 if (!parents) in clkgen_mux_get_parents()
39 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
40 return parents; in clkgen_mux_get_parents()
392 const char **parents; in st_of_clkgena_divmux_setup() local
405 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgena_divmux_setup()
406 if (IS_ERR(parents)) in st_of_clkgena_divmux_setup()
434 clk = clk_register_genamux(clk_name, parents, num_parents, in st_of_clkgena_divmux_setup()
443 kfree(parents); in st_of_clkgena_divmux_setup()
[all …]
Dclk-flexgen.c246 const char **parents; in flexgen_get_parents() local
253 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in flexgen_get_parents()
254 if (!parents) in flexgen_get_parents()
257 *num_parents = of_clk_parent_fill(np, parents, nparents); in flexgen_get_parents()
259 return parents; in flexgen_get_parents()
267 const char **parents; in st_of_flexgen_setup() local
281 parents = flexgen_get_parents(np, &num_parents); in st_of_flexgen_setup()
282 if (!parents) in st_of_flexgen_setup()
323 clk = clk_register_flexgen(clk_name, parents, num_parents, in st_of_flexgen_setup()
332 kfree(parents); in st_of_flexgen_setup()
[all …]
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos-clkout.c60 struct clk *parents[EXYNOS_CLKOUT_PARENTS]; in exynos_clkout_init() local
76 parents[i] = of_clk_get_by_name(node, name); in exynos_clkout_init()
77 if (IS_ERR(parents[i])) { in exynos_clkout_init()
82 parent_names[i] = __clk_get_name(parents[i]); in exynos_clkout_init()
127 if (!IS_ERR(parents[i])) in exynos_clkout_init()
128 clk_put(parents[i]); in exynos_clkout_init()
/linux-4.4.14/drivers/clk/pxa/
Dclk-pxa.h83 #define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \ argument
86 .dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
93 #define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \ argument
95 PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
Dclk-pxa25x.c100 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \ argument
102 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
114 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ argument
115 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
117 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ argument
118 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
Dclk-pxa27x.c93 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \ argument
95 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
107 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ argument
108 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
110 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ argument
111 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
Dclk-pxa3xx.c130 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \ argument
132 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
139 #define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents) \ argument
140 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
/linux-4.4.14/drivers/clk/shmobile/
Dclk-div6.c37 u8 *parents; member
137 if (clock->parents[i] == hw_index) in cpg_div6_clock_get_parent()
156 hw_index = clock->parents[index]; in cpg_div6_clock_set_parent()
197 clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents), in cpg_div6_clock_init()
231 clock->parents[valid_parents] = i; in cpg_div6_clock_init()
/linux-4.4.14/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c538 const char *parents[CLK_SRC_MAX]; in lpc18xx_cgu_register_div() local
544 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); in lpc18xx_cgu_register_div()
546 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_cgu_register_div()
558 const char *parents[CLK_SRC_MAX]; in lpc18xx_register_base_clk() local
566 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); in lpc18xx_register_base_clk()
570 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_register_base_clk()
574 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_register_base_clk()
585 const char *parents[CLK_SRC_MAX]; in lpc18xx_cgu_register_pll() local
591 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); in lpc18xx_cgu_register_pll()
593 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_cgu_register_pll()
[all …]
/linux-4.4.14/drivers/clk/sunxi/
Dclk-a10-mod1.c34 const char *parents[4]; in sun4i_mod1_clk_setup() local
52 i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS); in sun4i_mod1_clk_setup()
62 clk = clk_register_composite(NULL, clk_name, parents, i, in sun4i_mod1_clk_setup()
Dclk-a20-gmac.c67 const char *parents[SUN7I_A20_GMAC_PARENTS]; in sun7i_a20_gmac_clk_setup() local
83 if (of_clk_parent_fill(node, parents, 2) != 2) in sun7i_a20_gmac_clk_setup()
100 parents, SUN7I_A20_GMAC_PARENTS, in sun7i_a20_gmac_clk_setup()
Dclk-sun6i-ar100.c177 const char *parents[SUN6I_AR100_MAX_PARENTS]; in sun6i_a31_ar100_clk_probe() local
199 of_clk_parent_fill(np, parents, nparents); in sun6i_a31_ar100_clk_probe()
205 init.parent_names = parents; in sun6i_a31_ar100_clk_probe()
Dclk-factors.c174 const char *parents[FACTORS_MAX_PARENTS]; in sunxi_factors_register() local
178 i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS); in sunxi_factors_register()
232 parents, i, in sunxi_factors_register()
Dclk-sunxi.c198 const char *parents[SUN6I_AHB1_MAX_PARENTS]; in sun6i_ahb1_clk_setup() local
207 i = of_clk_parent_fill(node, parents, SUN6I_AHB1_MAX_PARENTS); in sun6i_ahb1_clk_setup()
227 clk = clk_register_composite(NULL, clk_name, parents, i, in sun6i_ahb1_clk_setup()
786 const char *parents[SUNXI_MAX_PARENTS]; in sunxi_mux_clk_setup() local
792 i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS); in sunxi_mux_clk_setup()
795 clk = clk_register_mux(NULL, clk_name, parents, i, in sunxi_mux_clk_setup()
/linux-4.4.14/drivers/clk/keystone/
Dpll.c301 const char *parents[2]; in of_pll_mux_clk_init() local
311 of_clk_parent_fill(node, parents, 2); in of_pll_mux_clk_init()
312 if (!parents[0] || !parents[1]) { in of_pll_mux_clk_init()
327 clk = clk_register_mux(NULL, clk_name, (const char **)&parents, in of_pll_mux_clk_init()
328 ARRAY_SIZE(parents) , 0, reg, shift, mask, in of_pll_mux_clk_init()
/linux-4.4.14/drivers/clk/imx/
Dclk.h85 u8 shift, u8 width, const char **parents,
123 u8 shift, u8 width, const char **parents, int num_parents) in imx_clk_mux() argument
125 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux()
131 void __iomem *reg, u8 shift, u8 width, const char **parents, in imx_clk_mux_flags() argument
134 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux_flags()
Dclk-fixup-mux.c75 u8 shift, u8 width, const char **parents, in imx_clk_fixup_mux() argument
91 init.parent_names = parents; in imx_clk_fixup_mux()
/linux-4.4.14/drivers/clk/tegra/
Dclk-tegra-pmc.c39 const char **parents; member
52 .parents = clk_out ##_num ##_parents,\
97 clk = clk_register_mux(NULL, data->mux_name, data->parents, in tegra_pmc_clk_init()
/linux-4.4.14/drivers/clk/bcm/
Dclk-bcm2835.c625 const char *const *parents; member
677 .parents = bcm2835_clock_osc_parents,
688 .parents = bcm2835_clock_osc_parents,
704 .parents = bcm2835_clock_vpu_parents,
715 .parents = bcm2835_clock_vpu_parents,
725 .parents = bcm2835_clock_vpu_parents,
735 .parents = bcm2835_clock_vpu_parents,
746 .parents = bcm2835_clock_per_parents,
756 .parents = bcm2835_clock_per_parents,
767 .parents = bcm2835_clock_per_parents,
[all …]
/linux-4.4.14/drivers/clk/ti/
Dclk-3xxx-legacy.c97 .parents = osc_sys_ck_parents,
133 .parents = dpll3_ck_parents,
304 .parents = dpll4_ck_parents,
402 .parents = omap_96m_fck_parents,
506 .parents = dpll5_ck_parents,
589 .parents = omap_48m_fck_parents,
649 .parents = mcbsp2_mux_fck_parents,
821 .parents = gpt2_mux_fck_parents,
960 .parents = mcbsp3_mux_fck_parents,
1005 .parents = gpt9_mux_fck_parents,
[all …]
Dclock.h89 const char **parents; member
138 const char **parents; member
Ddpll.c210 clk_ref = clk_get_sys(NULL, dpll->parents[0]); in ti_clk_register_dpll()
211 clk_bypass = clk_get_sys(NULL, dpll->parents[1]); in ti_clk_register_dpll()
232 init.parent_names = dpll->parents; in ti_clk_register_dpll()
Dcomposite.c146 parent_names = comp->mux->parents; in ti_clk_register_composite()
Dmux.c168 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, in ti_clk_register_mux()
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Dsp810.txt31 - assigned-clock-parents: from the common clock binding;
44 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
/linux-4.4.14/Documentation/devicetree/bindings/mmc/
Dmtk-sd.txt22 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
39 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
/linux-4.4.14/drivers/clk/
Dclk.c51 struct clk_core **parents; member
353 else if (!core->parents) in clk_core_get_parent_by_index()
355 else if (!core->parents[index]) in clk_core_get_parent_by_index()
356 return core->parents[index] = in clk_core_get_parent_by_index()
359 return core->parents[index]; in clk_core_get_parent_by_index()
1070 if (!core->parents) { in clk_fetch_parent_index()
1071 core->parents = kcalloc(core->num_parents, in clk_fetch_parent_index()
1073 if (!core->parents) in clk_fetch_parent_index()
1083 if (core->parents[i] == parent) in clk_fetch_parent_index()
1086 if (core->parents[i]) in clk_fetch_parent_index()
[all …]
/linux-4.4.14/drivers/clk/pistachio/
Dclk.h37 const char **parents; member
48 .parents = _pnames, \
Dclk.c84 clk = clk_register_mux(NULL, mux[i].name, mux[i].parents, in pistachio_clk_register_mux()
/linux-4.4.14/drivers/pinctrl/samsung/
Dpinctrl-s3c24xx.c96 int parents[NUM_EINT_IRQ]; member
207 int parent_irq = eint_data->parents[data->hwirq]; in s3c2410_eint0_3_ack()
218 int parent_irq = eint_data->parents[data->hwirq]; in s3c2410_eint0_3_mask()
229 int parent_irq = eint_data->parents[data->hwirq]; in s3c2410_eint0_3_unmask()
514 eint_data->parents[i] = irq; in s3c24xx_eint_init()
/linux-4.4.14/arch/arm/boot/dts/
Dstih407.dtsi27 assigned-clock-parents = <0>,
87 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
Dexynos4412-odroid-common.dtsi48 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
152 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
160 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
168 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
176 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
Dexynos4210-trats.dts162 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
170 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
178 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
186 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
Dexynos4210-universal_c210.dts188 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
196 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
204 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
212 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
Dstih410.dtsi114 assigned-clock-parents = <0>,
174 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
Dexynos4412-trats2.dts236 assigned-clock-parents = <&clock CLK_XUSBXTI>,
301 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
321 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
402 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
410 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
418 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
426 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
871 assigned-clock-parents = <&clock CLK_XUSBXTI>;
Dimx7d-sdb.dts109 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
135 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
269 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dstih418.dtsi105 assigned-clock-parents = <&clk_s_c0_pll1 0>;
Dimx6qdl-sabreauto.dtsi119 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
Drk3288-veyron.dtsi384 /* We need to go faster than 24MHz, so adjust clock parents / rates */
419 assigned-clock-parents = <&cru SCLK_OTGPHY0>;
Dexynos3250.dtsi197 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
271 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
Drk3288-rock2-som.dtsi93 assigned-clock-parents = <&ext_gmac>;
Drk3288-evb-rk808.dts256 assigned-clock-parents = <&ext_gmac>;
Ddra72-evm.dts802 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
820 assigned-clock-parents = <&atl_clkin2_ck>;
Dexynos5422-odroidxu3-common.dtsi63 assigned-clock-parents = <&clock CLK_FIN_PLL>,
Ddra7-evm.dts875 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
893 assigned-clock-parents = <&atl_clkin2_ck>;
Dvexpress-v2m-rs1.dtsi105 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
Dvexpress-v2m.dtsi104 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
Drk3288-r89.dts135 assigned-clock-parents = <&ext_gmac>;
Dimx6qdl-sabresd.dtsi147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
Dimx6qdl-sabrelite.dtsi239 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
Drk3288-firefly.dtsi226 assigned-clock-parents = <&ext_gmac>;
Dimx6qdl-nit6xlite.dtsi216 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
Drk3288-popmetal.dts200 assigned-clock-parents = <&ext_gmac>;
Dimx6qdl-nitrogen6x.dtsi253 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
Dimx6qdl-nitrogen6_max.dtsi351 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
Dsun5i.dtsi167 assigned-clock-parents = <&pll6 1>;
Dam43x-epos-evm.dts798 assigned-clock-parents = <&clkdiv32k_ick>;
Dexynos5420-peach-pit.dts920 assigned-clock-parents = <&clock CLK_FIN_PLL>;
Dexynos5800-peach-pi.dts883 assigned-clock-parents = <&clock CLK_FIN_PLL>;
Dsun6i-a31.dtsi247 assigned-clock-parents = <&pll6 0>;
Dsun7i-a20.dtsi272 assigned-clock-parents = <&pll6 3>;
/linux-4.4.14/fs/btrfs/
Dbackref.c248 struct ulist *parents, struct __prelim_ref *ref, in add_all_parents() argument
265 ret = ulist_add(parents, eb->start, 0, GFP_NOFS); in add_all_parents()
309 ret = ulist_add_merge_ptr(parents, eb->start, in add_all_parents()
341 struct ulist *parents, in __resolve_indirect_ref() argument
412 ret = add_all_parents(root, path, parents, ref, level, time_seq, in __resolve_indirect_ref()
434 struct ulist *parents; in __resolve_indirect_refs() local
438 parents = ulist_alloc(GFP_NOFS); in __resolve_indirect_refs()
439 if (!parents) in __resolve_indirect_refs()
457 parents, extent_item_pos, in __resolve_indirect_refs()
472 node = ulist_next(parents, &uiter); in __resolve_indirect_refs()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/clock/ti/
Dmux.txt7 parents, one of which can be selected as output. This clock does not
10 By default the "clocks" property lists the parents in the same order
Dcomposite.txt8 a multiplexer clock with multiple input clock signals or parents, one
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dclock-bindings.txt135 ==Assigned clock parents and rates==
139 node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
140 properties. The assigned-clock-parents property should contain a list of parent
157 assigned-clock-parents = <&pll 2>;
Drenesas,cpg-div6-clocks.txt20 clocks must be specified. For clocks with multiple parents, invalid
Drenesas,cpg-mstp-clocks.txt28 - clocks: Reference to the parent clocks, one per output clock. The parents
/linux-4.4.14/Documentation/devicetree/bindings/net/
Drockchip-dwmac.txt30 - assigned-clock-parents = parent of main clock.
63 assigned-clock-parents = <&ext_gmac>;
/linux-4.4.14/Documentation/devicetree/bindings/gpio/
Dbrcm,brcmstb-gpio.txt37 Alternate form of specifying interrupts and parents that allows for
38 multiple parents. This takes precedence over 'interrupts' and
/linux-4.4.14/drivers/clk/mvebu/
Dkirkwood.c236 const char **parents; member
309 desc[n].parents, desc[n].num_parents, in kirkwood_clk_muxing_setup()
/linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/
Dinterrupts.txt26 to reference multiple interrupt parents. Each entry in this property contains
28 should only be used when a device has multiple interrupt parents.
Dbrcm,bcm7120-l2-intc.txt65 respective interrupt parents. Should match exactly the number of interrupts
/linux-4.4.14/tools/perf/Documentation/
Dcallchain-overhead-calculation.txt65 child functions (i.e. 'foo' and 'bar') are added to the parents to
102 overhead) and they are the parents of 'foo' and 'bar'.
/linux-4.4.14/arch/x86/kvm/
Dmmu.c1973 #define for_each_sp(pvec, sp, parents, i) \ argument
1974 for (i = mmu_pages_next(&pvec, &parents, -1), \
1977 i = mmu_pages_next(&pvec, &parents, i))
1980 struct mmu_page_path *parents, in mmu_pages_next() argument
1989 parents->idx[0] = pvec->page[n].idx; in mmu_pages_next()
1993 parents->parent[sp->role.level-2] = sp; in mmu_pages_next()
1994 parents->idx[sp->role.level-1] = pvec->page[n].idx; in mmu_pages_next()
2000 static void mmu_pages_clear_parents(struct mmu_page_path *parents) in mmu_pages_clear_parents() argument
2006 unsigned int idx = parents->idx[level]; in mmu_pages_clear_parents()
2008 sp = parents->parent[level]; in mmu_pages_clear_parents()
[all …]
/linux-4.4.14/drivers/clk/zynq/
Dclkc.c115 const char **parents, int enable) in zynq_clk_register_fclk() argument
145 clk = clk_register_mux(NULL, mux_name, parents, 4, in zynq_clk_register_fclk()
188 const char **parents, unsigned int two_gates) in zynq_clk_register_periph_clk() argument
203 clk = clk_register_mux(NULL, mux_name, parents, 4, in zynq_clk_register_periph_clk()
/linux-4.4.14/Documentation/devicetree/bindings/leds/
Dleds-ns2.txt1 Binding for dual-GPIO LED found on Network Space v2 (and parents).
/linux-4.4.14/Documentation/devicetree/bindings/arm/msm/
Dtimer.txt17 - clocks: Reference to the parent clocks, one per output clock. The parents
/linux-4.4.14/Documentation/devicetree/bindings/display/exynos/
Dexynos_hdmi.txt24 parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
/linux-4.4.14/Documentation/power/
Dswsusp.txt189 * SUSPEND all but swap device and parents
192 * SUSPEND swap device and parents
195 Oh no, that does not work, if swap device or its parents uses DMA,
198 * SUSPEND all but swap device and parents
199 * FREEZE swap device and parents
201 * UNFREEZE swap device and parents
203 * SUSPEND swap device and parents
/linux-4.4.14/include/linux/
Dclk-provider.h704 int of_clk_parent_fill(struct device_node *np, const char **parents,
736 const char **parents, unsigned int size) in of_clk_parent_fill() argument
/linux-4.4.14/scripts/kconfig/
Dgconf.c59 static GtkTreeIter *parents[256]; variable
208 for (parents[0] = NULL, i = 1; i < 256; i++) in init_tree_model()
209 parents[i] = (GtkTreeIter *) g_malloc(sizeof(GtkTreeIter)); in init_tree_model()
1200 GtkTreeIter *parent = parents[indent - 1]; in place_node()
1201 GtkTreeIter *node = parents[indent]; in place_node()
/linux-4.4.14/Documentation/devicetree/bindings/i2c/
Di2c-pxa-pci-ce4100.txt45 * requires also a valid translation in parents ranges
/linux-4.4.14/drivers/clk/zte/
Dclk-zx296702.c214 static inline struct clk *zx_mux(const char *name, const char * const *parents, in zx_mux() argument
217 return clk_register_mux(NULL, name, parents, num_parents, in zx_mux()
/linux-4.4.14/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi78 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
Djuno-motherboard.dtsi155 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
Dvexpress-v2m-rs1.dtsi105 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
/linux-4.4.14/arch/arm64/boot/dts/rockchip/
Drk3368-r88.dts243 assigned-clock-parents = <&cru PLL_CPLL>;
/linux-4.4.14/Documentation/filesystems/
Ddirectory-locking32 * lock parents in "ancestors first" order.
Doverlayfs.txt150 exists in the upper filesystem - creating it and any parents as
Dporting73 same (i.e. parents and victim are locked, etc.).
Dvfs.txt1093 d_drop: this unhashes a dentry from its parents hash list. A
1102 d_add: add a dentry to its parents hash list and then calls
/linux-4.4.14/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi465 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
/linux-4.4.14/Documentation/
Dclk.txt48 struct clk **parents;
Dsysfs-rules.txt163 access the chain of parents is a bug in the application.
/linux-4.4.14/tools/testing/ktest/
Dktest.pl3738 my @parents = get_depends $config;
3739 foreach my $parent (@parents) {
/linux-4.4.14/Documentation/driver-model/
Dporting.txt138 devices are shutdown before their physical parents, and vice versa.
/linux-4.4.14/Documentation/powerpc/
Dcxlflash.txt270 forks, child process can clone the parents context by first creating
/linux-4.4.14/drivers/leds/
DKconfig465 Network Space v2 (and parents: Max, Mini)
/linux-4.4.14/Documentation/cgroups/
Dcpusets.txt130 of the parents CPU and Memory Node resources.
207 - Its CPUs and Memory Nodes must be a subset of its parents.
Dcgroups.txt295 value of their parents' notify_on_release settings. The default value of