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Searched refs:intel_ring_emit (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_ringbuffer.c113 intel_ring_emit(ring, cmd); in gen2_render_ring_flush()
114 intel_ring_emit(ring, MI_NOOP); in gen2_render_ring_flush()
172 intel_ring_emit(ring, cmd); in gen4_render_ring_flush()
173 intel_ring_emit(ring, MI_NOOP); in gen4_render_ring_flush()
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); in intel_emit_post_sync_nonzero_flush()
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | in intel_emit_post_sync_nonzero_flush()
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ in intel_emit_post_sync_nonzero_flush()
231 intel_ring_emit(ring, 0); /* low dword */ in intel_emit_post_sync_nonzero_flush()
232 intel_ring_emit(ring, 0); /* high dword */ in intel_emit_post_sync_nonzero_flush()
233 intel_ring_emit(ring, MI_NOOP); in intel_emit_post_sync_nonzero_flush()
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Di915_gem_context.c552 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); in mi_set_context()
556 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); in mi_set_context()
561 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
562 intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in mi_set_context()
567 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
568 intel_ring_emit(ring, MI_SET_CONTEXT); in mi_set_context()
569 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | in mi_set_context()
575 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
581 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); in mi_set_context()
586 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
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Dintel_overlay.c255 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON); in intel_overlay_on()
256 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE); in intel_overlay_on()
257 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_on()
258 intel_ring_emit(ring, MI_NOOP); in intel_overlay_on()
296 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_continue()
297 intel_ring_emit(ring, flip_addr); in intel_overlay_continue()
363 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_off()
364 intel_ring_emit(ring, flip_addr); in intel_overlay_off()
365 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_off()
370 intel_ring_emit(ring, MI_NOOP); in intel_overlay_off()
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Di915_gem_gtt.c663 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in gen8_write_pdp()
664 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); in gen8_write_pdp()
665 intel_ring_emit(ring, upper_32_bits(addr)); in gen8_write_pdp()
666 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in gen8_write_pdp()
667 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); in gen8_write_pdp()
668 intel_ring_emit(ring, lower_32_bits(addr)); in gen8_write_pdp()
1664 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); in hsw_mm_switch()
1665 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); in hsw_mm_switch()
1666 intel_ring_emit(ring, PP_DIR_DCLV_2G); in hsw_mm_switch()
1667 intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); in hsw_mm_switch()
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Di915_gem_execbuffer.c1116 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_reset_gen7_sol_offsets()
1117 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); in i915_reset_gen7_sol_offsets()
1118 intel_ring_emit(ring, 0); in i915_reset_gen7_sol_offsets()
1242 intel_ring_emit(ring, MI_NOOP); in i915_gem_ringbuffer_submission()
1243 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_gem_ringbuffer_submission()
1244 intel_ring_emit(ring, INSTPM); in i915_gem_ringbuffer_submission()
1245 intel_ring_emit(ring, instp_mask << 16 | instp_mode); in i915_gem_ringbuffer_submission()
Dintel_ringbuffer.h437 static inline void intel_ring_emit(struct intel_engine_cs *ring, in intel_ring_emit() function
Dintel_display.c10940 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); in intel_gen2_queue_flip()
10941 intel_ring_emit(ring, MI_NOOP); in intel_gen2_queue_flip()
10942 intel_ring_emit(ring, MI_DISPLAY_FLIP | in intel_gen2_queue_flip()
10944 intel_ring_emit(ring, fb->pitches[0]); in intel_gen2_queue_flip()
10945 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen2_queue_flip()
10946 intel_ring_emit(ring, 0); /* aux display base address, unused */ in intel_gen2_queue_flip()
10972 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); in intel_gen3_queue_flip()
10973 intel_ring_emit(ring, MI_NOOP); in intel_gen3_queue_flip()
10974 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | in intel_gen3_queue_flip()
10976 intel_ring_emit(ring, fb->pitches[0]); in intel_gen3_queue_flip()
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Di915_gem.c4653 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_gem_l3_remap()
4654 intel_ring_emit(ring, reg_base + i); in i915_gem_l3_remap()
4655 intel_ring_emit(ring, remap_info[i/4]); in i915_gem_l3_remap()