113 	intel_ring_emit(ring, cmd);  in gen2_render_ring_flush()
114 	intel_ring_emit(ring, MI_NOOP);  in gen2_render_ring_flush()
172 	intel_ring_emit(ring, cmd);  in gen4_render_ring_flush()
173 	intel_ring_emit(ring, MI_NOOP);  in gen4_render_ring_flush()
227 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));  in intel_emit_post_sync_nonzero_flush()
228 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |  in intel_emit_post_sync_nonzero_flush()
230 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
231 	intel_ring_emit(ring, 0); /* low dword */  in intel_emit_post_sync_nonzero_flush()
232 	intel_ring_emit(ring, 0); /* high dword */  in intel_emit_post_sync_nonzero_flush()
233 	intel_ring_emit(ring, MI_NOOP);  in intel_emit_post_sync_nonzero_flush()
240 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));  in intel_emit_post_sync_nonzero_flush()
241 	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);  in intel_emit_post_sync_nonzero_flush()
242 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
243 	intel_ring_emit(ring, 0);  in intel_emit_post_sync_nonzero_flush()
244 	intel_ring_emit(ring, 0);  in intel_emit_post_sync_nonzero_flush()
245 	intel_ring_emit(ring, MI_NOOP);  in intel_emit_post_sync_nonzero_flush()
295 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));  in gen6_render_ring_flush()
296 	intel_ring_emit(ring, flags);  in gen6_render_ring_flush()
297 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);  in gen6_render_ring_flush()
298 	intel_ring_emit(ring, 0);  in gen6_render_ring_flush()
314 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));  in gen7_render_ring_cs_stall_wa()
315 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |  in gen7_render_ring_cs_stall_wa()
317 	intel_ring_emit(ring, 0);  in gen7_render_ring_cs_stall_wa()
318 	intel_ring_emit(ring, 0);  in gen7_render_ring_cs_stall_wa()
379 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));  in gen7_render_ring_flush()
380 	intel_ring_emit(ring, flags);  in gen7_render_ring_flush()
381 	intel_ring_emit(ring, scratch_addr);  in gen7_render_ring_flush()
382 	intel_ring_emit(ring, 0);  in gen7_render_ring_flush()
399 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));  in gen8_emit_pipe_control()
400 	intel_ring_emit(ring, flags);  in gen8_emit_pipe_control()
401 	intel_ring_emit(ring, scratch_addr);  in gen8_emit_pipe_control()
402 	intel_ring_emit(ring, 0);  in gen8_emit_pipe_control()
403 	intel_ring_emit(ring, 0);  in gen8_emit_pipe_control()
404 	intel_ring_emit(ring, 0);  in gen8_emit_pipe_control()
736 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));  in intel_ring_workarounds_emit()
738 		intel_ring_emit(ring, w->reg[i].addr);  in intel_ring_workarounds_emit()
739 		intel_ring_emit(ring, w->reg[i].value);  in intel_ring_workarounds_emit()
741 	intel_ring_emit(ring, MI_NOOP);  in intel_ring_workarounds_emit()
1250 		intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));  in gen8_rcs_signal()
1251 		intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |  in gen8_rcs_signal()
1254 		intel_ring_emit(signaller, lower_32_bits(gtt_offset));  in gen8_rcs_signal()
1255 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_rcs_signal()
1256 		intel_ring_emit(signaller, seqno);  in gen8_rcs_signal()
1257 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1258 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_rcs_signal()
1260 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1291 		intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |  in gen8_xcs_signal()
1293 		intel_ring_emit(signaller, lower_32_bits(gtt_offset) |  in gen8_xcs_signal()
1295 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_xcs_signal()
1296 		intel_ring_emit(signaller, seqno);  in gen8_xcs_signal()
1297 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_xcs_signal()
1299 		intel_ring_emit(signaller, 0);  in gen8_xcs_signal()
1327 			intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));  in gen6_signal()
1328 			intel_ring_emit(signaller, mbox_reg);  in gen6_signal()
1329 			intel_ring_emit(signaller, seqno);  in gen6_signal()
1335 		intel_ring_emit(signaller, MI_NOOP);  in gen6_signal()
1362 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);  in gen6_add_request()
1363 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);  in gen6_add_request()
1364 	intel_ring_emit(ring, i915_gem_request_get_seqno(req));  in gen6_add_request()
1365 	intel_ring_emit(ring, MI_USER_INTERRUPT);  in gen6_add_request()
1399 	intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |  in gen8_ring_sync()
1403 	intel_ring_emit(waiter, seqno);  in gen8_ring_sync()
1404 	intel_ring_emit(waiter,  in gen8_ring_sync()
1406 	intel_ring_emit(waiter,  in gen8_ring_sync()
1438 		intel_ring_emit(waiter, dw1 | wait_mbox);  in gen6_ring_sync()
1439 		intel_ring_emit(waiter, seqno);  in gen6_ring_sync()
1440 		intel_ring_emit(waiter, 0);  in gen6_ring_sync()
1441 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1443 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1444 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1445 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1446 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1455 	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |		\
1457 	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\
1458 	intel_ring_emit(ring__, 0);							\
1459 	intel_ring_emit(ring__, 0);							\
1481 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |  in pc_render_add_request()
1484 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1485 	intel_ring_emit(ring, i915_gem_request_get_seqno(req));  in pc_render_add_request()
1486 	intel_ring_emit(ring, 0);  in pc_render_add_request()
1499 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |  in pc_render_add_request()
1503 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1504 	intel_ring_emit(ring, i915_gem_request_get_seqno(req));  in pc_render_add_request()
1505 	intel_ring_emit(ring, 0);  in pc_render_add_request()
1666 	intel_ring_emit(ring, MI_FLUSH);  in bsd_ring_flush()
1667 	intel_ring_emit(ring, MI_NOOP);  in bsd_ring_flush()
1682 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);  in i9xx_add_request()
1683 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);  in i9xx_add_request()
1684 	intel_ring_emit(ring, i915_gem_request_get_seqno(req));  in i9xx_add_request()
1685 	intel_ring_emit(ring, MI_USER_INTERRUPT);  in i9xx_add_request()
1827 	intel_ring_emit(ring,  in i965_dispatch_execbuffer()
1832 	intel_ring_emit(ring, offset);  in i965_dispatch_execbuffer()
1856 	intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);  in i830_dispatch_execbuffer()
1857 	intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);  in i830_dispatch_execbuffer()
1858 	intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */  in i830_dispatch_execbuffer()
1859 	intel_ring_emit(ring, cs_offset);  in i830_dispatch_execbuffer()
1860 	intel_ring_emit(ring, 0xdeadbeef);  in i830_dispatch_execbuffer()
1861 	intel_ring_emit(ring, MI_NOOP);  in i830_dispatch_execbuffer()
1876 		intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);  in i830_dispatch_execbuffer()
1877 		intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);  in i830_dispatch_execbuffer()
1878 		intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);  in i830_dispatch_execbuffer()
1879 		intel_ring_emit(ring, cs_offset);  in i830_dispatch_execbuffer()
1880 		intel_ring_emit(ring, 4096);  in i830_dispatch_execbuffer()
1881 		intel_ring_emit(ring, offset);  in i830_dispatch_execbuffer()
1883 		intel_ring_emit(ring, MI_FLUSH);  in i830_dispatch_execbuffer()
1884 		intel_ring_emit(ring, MI_NOOP);  in i830_dispatch_execbuffer()
1895 	intel_ring_emit(ring, MI_BATCH_BUFFER);  in i830_dispatch_execbuffer()
1896 	intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?  in i830_dispatch_execbuffer()
1898 	intel_ring_emit(ring, offset + len - 8);  in i830_dispatch_execbuffer()
1899 	intel_ring_emit(ring, MI_NOOP);  in i830_dispatch_execbuffer()
1917 	intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);  in i915_dispatch_execbuffer()
1918 	intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?  in i915_dispatch_execbuffer()
2423 		intel_ring_emit(ring, MI_NOOP);  in intel_ring_cacheline_align()
2510 	intel_ring_emit(ring, cmd);  in gen6_bsd_ring_flush()
2511 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);  in gen6_bsd_ring_flush()
2513 		intel_ring_emit(ring, 0); /* upper addr */  in gen6_bsd_ring_flush()
2514 		intel_ring_emit(ring, 0); /* value */  in gen6_bsd_ring_flush()
2516 		intel_ring_emit(ring, 0);  in gen6_bsd_ring_flush()
2517 		intel_ring_emit(ring, MI_NOOP);  in gen6_bsd_ring_flush()
2538 	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |  in gen8_ring_dispatch_execbuffer()
2541 	intel_ring_emit(ring, lower_32_bits(offset));  in gen8_ring_dispatch_execbuffer()
2542 	intel_ring_emit(ring, upper_32_bits(offset));  in gen8_ring_dispatch_execbuffer()
2543 	intel_ring_emit(ring, MI_NOOP);  in gen8_ring_dispatch_execbuffer()
2561 	intel_ring_emit(ring,  in hsw_ring_dispatch_execbuffer()
2568 	intel_ring_emit(ring, offset);  in hsw_ring_dispatch_execbuffer()
2586 	intel_ring_emit(ring,  in gen6_ring_dispatch_execbuffer()
2591 	intel_ring_emit(ring, offset);  in gen6_ring_dispatch_execbuffer()
2630 	intel_ring_emit(ring, cmd);  in gen6_ring_flush()
2631 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);  in gen6_ring_flush()
2633 		intel_ring_emit(ring, 0); /* upper addr */  in gen6_ring_flush()
2634 		intel_ring_emit(ring, 0); /* value */  in gen6_ring_flush()
2636 		intel_ring_emit(ring, 0);  in gen6_ring_flush()
2637 		intel_ring_emit(ring, MI_NOOP);  in gen6_ring_flush()