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Searched refs:intc (Results 1 – 200 of 276) sorted by relevance

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/linux-4.4.14/drivers/irqchip/
Dirq-bcm7038-l1.c78 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
81 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
84 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
87 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
90 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
93 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
96 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
99 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
120 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
126 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
[all …]
Dirq-moxart.c44 static struct moxart_irq_data intc; variable
51 irqstat = readl(intc.base + IRQ_STATUS_REG); in handle_irq()
55 handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); in handle_irq()
67 intc.base = of_iomap(node, 0); in moxart_of_intc_init()
68 if (!intc.base) { in moxart_of_intc_init()
74 intc.domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops, in moxart_of_intc_init()
75 intc.base); in moxart_of_intc_init()
76 if (!intc.domain) { in moxart_of_intc_init()
81 ret = irq_alloc_domain_generic_chips(intc.domain, 32, 1, in moxart_of_intc_init()
87 irq_domain_remove(intc.domain); in moxart_of_intc_init()
[all …]
Dirq-s3c24xx.c55 struct s3c_irq_intc *intc; member
89 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask() local
90 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
95 mask = __raw_readl(intc->reg_mask); in s3c_irq_mask()
97 __raw_writel(mask, intc->reg_mask); in s3c_irq_mask()
117 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_unmask() local
118 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_unmask()
122 mask = __raw_readl(intc->reg_mask); in s3c_irq_unmask()
124 __raw_writel(mask, intc->reg_mask); in s3c_irq_unmask()
136 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_ack() local
[all …]
Dirq-ingenic.c46 struct ingenic_intc_data *intc = irq_get_handler_data(irq); in intc_cascade() local
50 for (i = 0; i < intc->num_chips; i++) { in intc_cascade()
51 irq_reg = readl(intc->base + (i * CHIP_SIZE) + in intc_cascade()
90 struct ingenic_intc_data *intc; in ingenic_intc_of_init() local
97 intc = kzalloc(sizeof(*intc), GFP_KERNEL); in ingenic_intc_of_init()
98 if (!intc) { in ingenic_intc_of_init()
109 err = irq_set_handler_data(parent_irq, intc); in ingenic_intc_of_init()
113 intc->num_chips = num_chips; in ingenic_intc_of_init()
114 intc->base = of_iomap(node, 0); in ingenic_intc_of_init()
115 if (!intc->base) { in ingenic_intc_of_init()
[all …]
Dirq-bcm2836.c79 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
85 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
94 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
121 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR); in bcm2836_arm_irqchip_mask_pmu_irq()
126 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET); in bcm2836_arm_irqchip_unmask_pmu_irq()
151 int irq = irq_create_mapping(intc.domain, hwirq); in bcm2836_arm_irqchip_register_irq()
164 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); in bcm2836_arm_irqchip_handle_irq()
167 void __iomem *mailbox0 = (intc.base + in bcm2836_arm_irqchip_handle_irq()
178 handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); in bcm2836_arm_irqchip_handle_irq()
187 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0; in bcm2836_arm_irqchip_send_ipi()
[all …]
Dirq-bcm2835.c96 static struct armctrl_ic intc __read_mostly;
103 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
108 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
154 intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0), in armctrl_of_init()
156 if (!intc.domain) in armctrl_of_init()
160 intc.pending[b] = base + reg_pending[b]; in armctrl_of_init()
161 intc.enable[b] = base + reg_enable[b]; in armctrl_of_init()
162 intc.disable[b] = base + reg_disable[b]; in armctrl_of_init()
165 irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i)); in armctrl_of_init()
209 u32 stat = readl_relaxed(intc.pending[bank]); in armctrl_translate_bank()
[all …]
Dirq-vt8500.c80 static struct vt8500_irq_data intc[VT8500_INTC_MAX]; variable
187 base = intc[i].base; in vt8500_handle_irq()
199 handle_domain_irq(intc[i].domain, irqnr, regs); in vt8500_handle_irq()
215 intc[active_cnt].base = of_iomap(np, 0); in vt8500_irq_init()
216 intc[active_cnt].domain = irq_domain_add_linear(node, 64, in vt8500_irq_init()
217 &vt8500_irq_domain_ops, &intc[active_cnt]); in vt8500_irq_init()
219 if (!intc[active_cnt].base) { in vt8500_irq_init()
224 if (!intc[active_cnt].domain) { in vt8500_irq_init()
231 vt8500_init_irq_hw(intc[active_cnt].base); in vt8500_irq_init()
Dirq-hip04.c210 static u16 hip04_get_cpumask(struct hip04_irq_data *intc) in hip04_get_cpumask() argument
212 void __iomem *base = intc->dist_base; in hip04_get_cpumask()
228 static void __init hip04_irq_dist_init(struct hip04_irq_data *intc) in hip04_irq_dist_init() argument
232 unsigned int nr_irqs = intc->nr_irqs; in hip04_irq_dist_init()
233 void __iomem *base = intc->dist_base; in hip04_irq_dist_init()
240 cpumask = hip04_get_cpumask(intc); in hip04_irq_dist_init()
250 static void hip04_irq_cpu_init(struct hip04_irq_data *intc) in hip04_irq_cpu_init() argument
252 void __iomem *dist_base = intc->dist_base; in hip04_irq_cpu_init()
253 void __iomem *base = intc->cpu_base; in hip04_irq_cpu_init()
261 cpu_mask = hip04_get_cpumask(intc); in hip04_irq_cpu_init()
Dirq-renesas-h8300h.c75 static int __init h8300h_intc_of_init(struct device_node *intc, in h8300h_intc_of_init() argument
80 intc_baseaddr = of_iomap(intc, 0); in h8300h_intc_of_init()
87 domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL); in h8300h_intc_of_init()
Dirq-renesas-h8s.c81 static int __init h8s_intc_of_init(struct device_node *intc, in h8s_intc_of_init() argument
87 intc_baseaddr = of_iomap(intc, 0); in h8s_intc_of_init()
95 domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL); in h8s_intc_of_init()
DMakefile19 obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
35 obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
/linux-4.4.14/arch/m68k/coldfire/
DMakefile18 obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
19 obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
20 obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
21 obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
22 obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
23 obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
24 obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
25 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
26 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
27 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/
Dmrvl,intc.txt4 - compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
5 "mrvl,mmp2-mux-intc"
7 If the interrupt controller is intc, address and length means the range
8 of the whold interrupt controller. If the interrupt controller is mux-intc,
9 address and length means one register. Since address of mux-intc is in the
10 range of intc. mux-intc is secondary interrupt controller.
12 only required in mux-intc interrupt controller.
14 only required in mux-intc interrupt controller.
18 - mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
24 intc: interrupt-controller@d4282000 {
[all …]
Dti,omap-intc-irq.txt1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
Dingenic,intc.txt5 - compatible : should be "ingenic,<socname>-intc". Valid strings are:
6 ingenic,jz4740-intc
7 ingenic,jz4770-intc
8 ingenic,jz4775-intc
9 ingenic,jz4780-intc
19 intc: interrupt-controller@10001000 {
20 compatible = "ingenic,jz4740-intc";
Dqca,ath79-misc-intc.txt7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
25 compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc";
38 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
Dti,omap2-intc.txt9 "ti,omap2-intc"
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
20 intc: interrupt-controller@1 {
21 compatible = "ti,omap2-intc";
24 ti,intc-size = <96>;
Dti,cp-intc.txt10 "ti,cp-intc"
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
21 intc: interrupt-controller@1 {
22 compatible = "ti,cp-intc";
25 ti,intc-size = <101>;
Dsnps,archs-idu-intc.txt4 dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
8 - compatible: "snps,archs-idu-intc"
10 - interrupt-parent: <reference to parent core intc>
18 intc accessed via the special ARC AUX register interface, hence "reg" property
23 compatible = "snps,archs-intc";
29 compatible = "snps,archs-idu-intc";
Drenesas,intc-irqpin.txt5 - compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
8 - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
9 - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
10 - "renesas,intc-irqpin-r8a7779" (R-Car H1)
11 - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
43 compatible = "renesas,intc-irqpin-r8a7740",
44 "renesas,intc-irqpin";
Dsnps,arc700-intc.txt8 - compatible: "snps,arc700-intc"
15 intc accessed via the special ARC AUX register interface, hence "reg" property
20 intc: interrupt-controller {
21 compatible = "snps,arc700-intc";
Dsnps,archs-intc.txt5 - compatible: "snps,archs-intc"
12 intc accessed via the special ARC AUX register interface, hence "reg" property
17 intc: interrupt-controller {
18 compatible = "snps,archs-intc";
Drenesas,h8s-intc.txt5 - compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback.
18 compatible = "renesas,h8s-intc", "renesas,h8300-intc";
Drenesas,h8300h-intc.txt5 - compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback.
18 compatible = "renesas,h8300h-intc", "renesas,h8300-intc";
Daxis,crisv32-intc.txt8 "axis,crisv32-intc"
12 - reg: physical base address and size of the intc registers map.
16 intc: interrupt-controller {
17 compatible = "axis,crisv32-intc";
Dqca,ath79-cpu-intc.txt9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
13 source, should be 1 for intc
29 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
Dvia,vt8500-intc.txt5 - compatible : "via,vt8500-intc"
11 intc: interrupt-controller@d8140000 {
12 compatible = "via,vt8500-intc";
Dmarvell,orion-intc.txt6 - compatible: shall be "marvell,orion-intc"
18 intc: interrupt-controller {
19 compatible = "marvell,orion-intc";
29 - compatible: shall be "marvell,orion-bridge-intc"
41 compatible = "marvell,orion-bridge-intc";
Dimg,meta-intc.txt9 The type shall be <string> and the value shall include "img,meta-intc".
46 intc: intc {
65 compatible = "img,meta-intc";
81 interrupt-parent = <&intc>;
Dbrcm,l2-intc.txt5 - compatible: should be "brcm,l2-intc"
23 compatible = "brcm,l2-intc";
27 interrupt-parent = <&intc>;
Dcirrus,clps711x-intc.txt5 - compatible: Should be "cirrus,clps711x-intc".
36 intc: interrupt-controller {
37 compatible = "cirrus,clps711x-intc";
Dlsi,zevio-intc.txt4 - compatible: Compatible property value should be "lsi,zevio-intc".
14 compatible = "lsi,zevio-intc";
Dbrcm,bcm2836-l1-intc.txt10 - compatible: Should be "brcm,bcm2836-l1-intc"
32 compatible = "brcm,bcm2836-l1-intc";
Dabilis,tb10x-ictl.txt24 intc: interrupt-controller { /* Parent interrupt controller */
35 interrupt-parent = <&intc>;
Dbrcm,bcm3380-l2-intc.txt15 - compatible: should be "brcm,bcm3380-l2-intc"
34 compatible = "brcm,bcm3380-l2-intc";
Dbrcm,bcm7120-l2-intc.txt54 - compatible: should be "brcm,bcm7120-l2-intc"
82 compatible = "brcm,bcm7120-l2-intc";
83 interrupt-parent = <&intc>;
Dbrcm,bcm7038-l1-intc.txt25 - compatible: should be "brcm,bcm7038-l1-intc"
44 compatible = "brcm,bcm7038-l1-intc";
Dbrcm,bcm2835-armctrl-ic.txt117 intc: interrupt-controller {
125 intc: interrupt-controller {
Dallwinner,sun4i-ic.txt13 intc: interrupt-controller {
Ddigicolor-ic.txt15 intc: interrupt-controller@f0000040 {
Dimg,pdc-intc.txt11 The type shall be <string> and the value shall include "img,pdc-intc".
65 compatible = "img,pdc-intc";
Dopencores,or1k-pic.txt19 intc: interrupt-controller {
Dinterrupts.txt51 vic: intc@10140000 {
58 sic: intc@10003000 {
Dallwinner,sun67i-sc-nmi.txt20 sc-nmi-intc@01c00030 {
Drenesas,irqc.txt13 - "renesas,intc-ex-r8a7795" (R-Car H3)
Dnvidia,tegra-ictlr.txt42 interrupt-parent = <&intc>;
Dsamsung,s3c24xx-irq.txt51 interrupt-parent = <&intc>;
/linux-4.4.14/arch/arm/boot/dts/
Dmmp2.dtsi27 interrupt-parent = <&intc>;
42 intc: interrupt-controller@d4282000 { label
43 compatible = "mrvl,mmp2-intc";
47 mrvl,intc-nr-irqs = <64>;
51 compatible = "mrvl,mmp2-mux-intc";
57 mrvl,intc-nr-irqs = <2>;
61 compatible = "mrvl,mmp2-mux-intc";
67 mrvl,intc-nr-irqs = <2>;
72 compatible = "mrvl,mmp2-mux-intc";
78 mrvl,intc-nr-irqs = <3>;
[all …]
Dzynq-7000.dtsi47 interrupt-parent = <&intc>;
64 interrupt-parent = <&intc>;
71 interrupt-parent = <&intc>;
82 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
113 interrupt-parent = <&intc>;
124 interrupt-parent = <&intc>;
131 intc: interrupt-controller@f8f01000 { label
176 interrupt-parent = <&intc>;
[all …]
Dvf500.dtsi29 intc: interrupt-controller@40002000 { label
33 interrupt-parent = <&intc>;
42 interrupt-parent = <&intc>;
50 interrupt-parent = <&intc>;
Dpxa168.dtsi26 interrupt-parent = <&intc>;
36 intc: interrupt-controller@d4282000 { label
37 compatible = "mrvl,mmp-intc";
41 mrvl,intc-nr-irqs = <64>;
Dpxa910.dtsi26 interrupt-parent = <&intc>;
41 intc: interrupt-controller@d4282000 { label
42 compatible = "mrvl,mmp-intc";
46 mrvl,intc-nr-irqs = <64>;
Dstih41x.dtsi27 intc: interrupt-controller@fffe1000 { label
41 interrupt-parent = <&intc>;
Domap3-evm-common.dtsi41 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
42 interrupt-parent = <&intc>;
99 interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
Dvt8500.dtsi36 interrupt-parent = <&intc>;
38 intc: interrupt-controller@d8140000 { label
39 compatible = "via,vt8500-intc";
Dzx296702.dtsi32 interrupt-parent = <&intc>;
40 intc: interrupt-controller@00801000 { label
54 interrupt-parent = <&intc>;
Dnspire-classic.dtsi69 intc: interrupt-controller@DC000000 { label
70 compatible = "lsi,zevio-intc";
Dorion5x.dtsi16 interrupt-parent = <&intc>;
122 compatible = "marvell,orion-bridge-intc";
130 intc: interrupt-controller@20200 { label
131 compatible = "marvell,orion-intc";
Ds3c24xx.dtsi15 interrupt-parent = <&intc>;
24 intc:interrupt-controller@4a000000 { label
Domap3.dtsi19 interrupt-parent = <&intc>;
198 intc: interrupt-controller@48200000 { label
199 compatible = "ti,omap3-intc";
287 interrupts-extended = <&intc 72>;
297 interrupts-extended = <&intc 73>;
307 interrupts-extended = <&intc 74>;
703 interrupt-parent = <&intc>;
710 interrupt-parent = <&intc>;
815 interrupt-parent = <&intc>;
828 interrupt-parent = <&intc>;
Ddove.dtsi11 interrupt-parent = <&intc>;
93 msi-parent = <&intc>;
118 interrupt-map = <0 0 0 0 &intc 16>;
136 interrupt-map = <0 0 0 0 &intc 18>;
234 compatible = "marvell,orion-bridge-intc";
242 intc: main-interrupt-ctrl@20200 { label
243 compatible = "marvell,orion-intc";
721 interrupt-parent = <&intc>;
733 interrupt-parent = <&intc>;
Dlogicpd-torpedo-som.dtsi97 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
98 interrupt-parent = <&intc>;
110 interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
Dda850.dtsi18 intc: interrupt-controller { label
19 compatible = "ti,cp-intc";
22 ti,intc-size = <100>;
32 interrupt-parent = <&intc>;
Dbcm7445.dtsi101 compatible = "brcm,bcm7120-l2-intc";
113 compatible = "brcm,bcm7120-l2-intc";
127 compatible = "brcm,l2-intc";
137 compatible = "brcm,l2-intc";
Ddm814x.dtsi14 interrupt-parent = <&intc>;
250 intc: interrupt-controller@48200000 { label
251 compatible = "ti,dm814-intc";
294 interrupt-parent = <&intc>;
Dr8a7740.dtsi71 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
93 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
115 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
137 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
Dpxa3xx.dtsi41 marvell,intc-priority;
42 marvell,intc-nr-irqs = <56>;
Dpxa2xx.dtsi43 compatible = "marvell,pxa-intc";
46 marvell,intc-nr-irqs = <32>;
Domap3-cm-t3x30.dtsi68 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
69 interrupt-parent = <&intc>;
Dmoxart.dtsi13 interrupt-parent = <&intc>;
38 intc: interrupt-controller@98800000 { label
Dam33xx.dtsi18 interrupt-parent = <&intc>;
169 intc: interrupt-controller@48200000 { label
170 compatible = "ti,am33xx-intc";
329 interrupt-parent = <&intc>;
342 interrupt-parent = <&intc>;
352 interrupt-parent = <&intc>;
738 interrupt-parent = <&intc>;
793 interrupt-parent = <&intc>;
802 interrupt-parent = <&intc>;
Dpxa27x.dtsi20 marvell,intc-priority;
21 marvell,intc-nr-irqs = <34>;
Domap3-evm-37xx.dts143 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
147 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
151 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
Dam3517-craneboard.dts89 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
90 interrupt-parent = <&intc>;
Dkirkwood-6282.dtsi32 interrupt-map = <0 0 0 0 &intc 9>;
49 interrupt-map = <0 0 0 0 &intc 10>;
Dkirkwood.dtsi9 interrupt-parent = <&intc>;
209 compatible = "marvell,orion-bridge-intc";
229 intc: main-interrupt-ctrl@20200 { label
230 compatible = "marvell,orion-intc";
Domap2.dtsi19 interrupt-parent = <&intc>;
74 intc: interrupt-controller@1 { label
75 compatible = "ti,omap2-intc";
Dlogicpd-torpedo-37xx-devkit.dts88 interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
146 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
Dr8a7779-marzen.dts180 intc {
182 renesas,function = "intc";
Dsh73a0.dtsi94 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
116 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
138 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
160 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
Domap3-ldp.dts162 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
163 interrupt-parent = <&intc>;
289 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
Dkirkwood-98dx4122.dtsi28 interrupt-map = <0 0 0 0 &intc 9>;
Domap3-n950-n9.dtsi54 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
55 interrupt-parent = <&intc>;
Dwm8650.dtsi37 compatible = "via,vt8500-intc";
45 compatible = "via,vt8500-intc";
Domap3-beagle-xm.dts272 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
273 interrupt-parent = <&intc>;
335 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
Dqcom-msm8660.dtsi12 interrupt-parent = <&intc>;
51 intc: interrupt-controller@2080000 { label
Dbcm2835.dtsi8 interrupt-parent = <&intc>;
53 intc: interrupt-controller@7e00b200 { label
Dcx92755.dtsi52 interrupt-parent = <&intc>;
70 intc: interrupt-controller@f0000040 { label
Domap3-igep.dtsi152 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
153 interrupt-parent = <&intc>;
Domap3-zoom3.dts148 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
149 interrupt-parent = <&intc>;
Domap3-beagle.dts266 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
267 interrupt-parent = <&intc>;
321 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
Dwm8505.dtsi41 compatible = "via,vt8500-intc";
49 compatible = "via,vt8500-intc";
Dwm8850.dtsi40 compatible = "via,vt8500-intc";
48 compatible = "via,vt8500-intc";
Dkirkwood-6281.dtsi28 interrupt-map = <0 0 0 0 &intc 9>;
Dkirkwood-6192.dtsi28 interrupt-map = <0 0 0 0 &intc 9>;
Dimx6qdl.dtsi50 intc: interrupt-controller@00a01000 { label
56 interrupt-parent = <&intc>;
154 interrupt-parent = <&intc>;
767 interrupt-parent = <&intc>;
878 interrupt-parent = <&intc>;
954 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
955 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
Domap2430-sdp.dts27 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
Dqcom-apq8084.dtsi11 interrupt-parent = <&intc>;
98 intc: interrupt-controller@f9000000 { label
Dversatile-ab.dts96 vic: intc@10140000 {
105 sic: intc@10003000 {
Dwm8750.dtsi43 compatible = "via,vt8500-intc";
51 compatible = "via,vt8500-intc";
Dqcom-msm8960.dtsi13 interrupt-parent = <&intc>;
58 intc: interrupt-controller@2000000 { label
Dtegra20.dtsi145 interrupt-parent = <&intc>;
152 intc: interrupt-controller@50041000 { label
158 interrupt-parent = <&intc>;
178 interrupt-parent = <&intc>;
589 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
Dstih407-family.dtsi37 intc: interrupt-controller@08761000 { label
50 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
86 interrupt-parent = <&intc>;
Ddm816x.dtsi14 interrupt-parent = <&intc>;
209 intc: interrupt-controller@48200000 { label
210 compatible = "ti,dm816-intc";
Domap3-overo-common-peripherals.dtsi91 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
Dnspire-cx.dts95 intc: interrupt-controller@DC000000 { label
Domap3-overo-base.dtsi156 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
157 interrupt-parent = <&intc>;
Dqcom-ipq8064.dtsi11 interrupt-parent = <&intc>;
104 intc: interrupt-controller@2000000 { label
Duniphier-ph1-sld3.dtsi95 interrupt-parent = <&intc>;
117 intc: interrupt-controller@20001000 { label
Dversatile-pb.dts9 sic: intc@10003000 {
Dtegra30.dtsi26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-parent = <&intc>;
237 intc: interrupt-controller@50041000 { label
243 interrupt-parent = <&intc>;
264 interrupt-parent = <&intc>;
Decx-2000.dts94 intc: interrupt-controller@fff11000 { label
Duniphier-ph1-sld8.dtsi87 interrupt-parent = <&intc>;
255 intc: interrupt-controller@60001000 { label
/linux-4.4.14/arch/mips/boot/dts/ralink/
Drt3050.dtsi32 intc: intc@200 { label
33 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
52 interrupt-parent = <&intc>;
63 interrupt-parent = <&intc>;
Dmt7620a.dtsi32 intc: intc@200 { label
33 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
52 interrupt-parent = <&intc>;
Drt3883.dtsi32 intc: intc@200 { label
33 compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
52 interrupt-parent = <&intc>;
Drt2880.dtsi32 intc: intc@200 { label
33 compatible = "ralink,rt2880-intc";
52 interrupt-parent = <&intc>;
/linux-4.4.14/arch/mips/boot/dts/ingenic/
Djz4780.dtsi15 intc: interrupt-controller@10001000 { label
16 compatible = "ingenic,jz4780-intc";
51 interrupt-parent = <&intc>;
64 interrupt-parent = <&intc>;
77 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
103 interrupt-parent = <&intc>;
Djz4740.dtsi15 intc: interrupt-controller@10001000 { label
16 compatible = "ingenic,jz4740-intc";
51 interrupt-parent = <&intc>;
62 interrupt-parent = <&intc>;
/linux-4.4.14/arch/arc/boot/dts/
Daxc003.dtsi26 cpu_intc: archs-intc@cpu {
27 compatible = "snps,archs-intc";
34 * to uplink only 1 IRQ to ARC core intc
75 * The DW APB ICTL intc on MB is connected to CPU intc via a
83 * This intc actually resides on MB, but we move it here to
85 * this intc to cpu intc are different for axs101 and axs103
Daxc003_idu.dtsi10 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
26 cpu_intc: archs-intc@cpu {
27 compatible = "snps,archs-intc";
33 compatible = "snps,archs-idu-intc";
44 * upstream irqs to core intc - downstream these are
52 * to uplink only 1 IRQ to ARC core intc
105 * This intc actually resides on MB, but we move it here to
107 * this intc to cpu intc are different for axs101 and axs103
Daxc001.dtsi27 cpu_intc: arc700-intc@cpu {
28 compatible = "snps,arc700-intc";
35 * to uplink only 1 IRQ to ARC core intc
80 * This intc actually resides on MB, but we move it here to
82 * this intc to cpu intc are different for axs101 and axs103
Dvdk_axc003_idu.dtsi11 * HS38x2 (Dual Core) with IDU intc (VDK version)
27 cpu_intc: archs-intc@cpu {
28 compatible = "snps,archs-intc";
34 compatible = "snps,archs-idu-intc";
Dnsim_700.dts17 interrupt-parent = <&intc>;
35 intc: interrupt-controller { label
36 compatible = "snps,arc700-intc";
Dnsim_hs_idu.dts33 compatible = "snps,archs-intc";
39 compatible = "snps,archs-idu-intc";
50 * upstream irqs to core intc - downstream these are
Dnsimosci.dts17 interrupt-parent = <&intc>;
38 intc: interrupt-controller { label
39 compatible = "snps,arc700-intc";
Dnsimosci_hs_idu.dts37 compatible = "snps,archs-intc";
44 compatible = "snps,archs-idu-intc";
55 * upstream irqs to core intc - downstream these are
Dvdk_axc003.dtsi26 cpu_intc: archs-intc@cpu {
27 compatible = "snps,archs-intc";
Dabilis_tb10x.dtsi70 intc: interrupt-controller { label
71 compatible = "snps,arc700-intc";
80 interrupt-parent = <&intc>;
Dnsim_hs.dts42 compatible = "snps,archs-intc";
Dnsimosci_hs.dts39 compatible = "snps,archs-intc";
/linux-4.4.14/arch/microblaze/kernel/
Dintc.c138 static int __init xilinx_intc_of_init(struct device_node *intc, in xilinx_intc_of_init() argument
144 intc_baseaddr = of_iomap(intc, 0); in xilinx_intc_of_init()
147 ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); in xilinx_intc_of_init()
153 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); in xilinx_intc_of_init()
163 intc->full_name, nr_irq, intr_mask); in xilinx_intc_of_init()
188 root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, in xilinx_intc_of_init()
DMakefile18 hw_exception_handler.o intc.o irq.o \
/linux-4.4.14/Documentation/devicetree/bindings/mips/
Dcpu_irq.txt25 intc: intc@200 {
26 compatible = "ralink,rt2880-intc";
40 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
/linux-4.4.14/Documentation/devicetree/bindings/pci/
Dfsl,imx6q-pcie.txt34 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
35 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
36 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
37 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
/linux-4.4.14/arch/cris/boot/dts/
Detraxfs.dtsi4 interrupt-parent = <&intc>;
24 intc: interrupt-controller { label
25 compatible = "axis,crisv32-intc";
Dartpec3.dtsi4 interrupt-parent = <&intc>;
24 intc: interrupt-controller { label
25 compatible = "axis,crisv32-intc";
/linux-4.4.14/arch/metag/boot/dts/
Dtz1090.dtsi16 interrupt-parent = <&intc>;
18 intc: interrupt-controller { label
19 compatible = "img,meta-intc";
36 compatible = "img,pdc-intc";
/linux-4.4.14/arch/mips/boot/dts/qca/
Dar9132.dtsi19 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
108 compatible = "qca,ar9132-misc-intc",
109 "qca,ar7100-misc-intc";
/linux-4.4.14/arch/mips/boot/dts/brcm/
Dbcm3384_zephyr.dtsi63 compatible = "brcm,bcm3380-l2-intc";
75 compatible = "brcm,bcm3380-l2-intc";
87 compatible = "brcm,bcm3380-l2-intc";
Dbcm7125.dtsi53 compatible = "brcm,bcm7038-l1-intc";
64 compatible = "brcm,l2-intc";
85 compatible = "brcm,bcm7120-l2-intc";
Dbcm7358.dtsi49 compatible = "brcm,bcm7038-l1-intc";
60 compatible = "brcm,l2-intc";
81 compatible = "brcm,bcm7120-l2-intc";
96 compatible = "brcm,bcm7120-l2-intc";
Dbcm7360.dtsi49 compatible = "brcm,bcm7038-l1-intc";
60 compatible = "brcm,l2-intc";
81 compatible = "brcm,bcm7120-l2-intc";
96 compatible = "brcm,bcm7120-l2-intc";
Dbcm7420.dtsi53 compatible = "brcm,bcm7038-l1-intc";
64 compatible = "brcm,l2-intc";
86 compatible = "brcm,bcm7120-l2-intc";
Dbcm7362.dtsi55 compatible = "brcm,bcm7038-l1-intc";
66 compatible = "brcm,l2-intc";
87 compatible = "brcm,bcm7120-l2-intc";
102 compatible = "brcm,bcm7120-l2-intc";
Dbcm3384_viper.dtsi57 compatible = "brcm,bcm3380-l2-intc";
69 compatible = "brcm,bcm3380-l2-intc";
Dbcm7435.dtsi65 compatible = "brcm,bcm7038-l1-intc";
76 compatible = "brcm,l2-intc";
101 compatible = "brcm,bcm7120-l2-intc";
Dbcm7346.dtsi55 compatible = "brcm,bcm7038-l1-intc";
66 compatible = "brcm,l2-intc";
87 compatible = "brcm,bcm7120-l2-intc";
102 compatible = "brcm,bcm7120-l2-intc";
Dbcm7425.dtsi53 compatible = "brcm,bcm7038-l1-intc";
64 compatible = "brcm,l2-intc";
87 compatible = "brcm,bcm7120-l2-intc";
Dbcm6328.dtsi53 compatible = "brcm,bcm3380-l2-intc";
Dbcm6368.dtsi54 compatible = "brcm,bcm3380-l2-intc";
/linux-4.4.14/arch/arc/kernel/
Dmcip.c314 idu_of_init(struct device_node *intc, struct device_node *parent) in idu_of_init() argument
318 int nr_irqs = of_irq_count(intc); in idu_of_init()
326 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); in idu_of_init()
337 irq = irq_of_parse_and_map(intc, i); in idu_of_init()
Dintc-compact.c103 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) in init_onchip_IRQ() argument
108 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, in init_onchip_IRQ()
DMakefile13 obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o
14 obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
Dintc-arcv2.c136 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) in init_onchip_IRQ() argument
141 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, in init_onchip_IRQ()
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
Dtwl4030-audio.txt32 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
33 interrupt-parent = <&intc>;
Dtwl4030-power.txt40 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
41 interrupt-parent = <&intc>;
Dmax77802.txt23 interrupt-parent = <&intc>;
Dpalmas.txt39 interrupt-parent = <&intc>;
D88pm860x.txt34 interrupt-parent = <&intc>;
Dda9055.txt53 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/net/can/
Dxilinx_can.txt30 interrupt-parent = <&intc>;
40 interrupt-parent = <&intc>;
Dc_can.txt35 interrupt-parent = <&intc>;
46 interrupt-parent = <&intc>;
Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
/linux-4.4.14/arch/h8300/boot/dts/
Dh8300h_sim.dts53 compatible = "renesas,h8300h-intc", "renesas,h8300-intc";
Dh8s_sim.dts59 compatible = "renesas,h8s-intc", "renesas,h8300-intc";
Dedosk2674.dts60 compatible = "renesas,h8s-intc", "renesas,h8300-intc";
/linux-4.4.14/Documentation/devicetree/bindings/arm/ux500/
Dboards.txt46 interrupt-parent = <&intc>;
54 intc: interrupt-controller@a0411000 {
/linux-4.4.14/arch/sh/kernel/cpu/sh4a/
DMakefile11 obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
18 obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
/linux-4.4.14/arch/avr32/mach-at32ap/
Dintc.c22 struct intc { struct
47 static struct intc intc0 = { argument
DMakefile1 obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
/linux-4.4.14/arch/mips/xilfpga/
DMakefile6 obj-y += intc.o
/linux-4.4.14/drivers/sh/
DKconfig3 source "drivers/sh/intc/Kconfig"
DMakefile4 obj-$(CONFIG_SH_INTC) += intc/
/linux-4.4.14/arch/sh/kernel/cpu/irq/
DMakefile5 obj-$(CONFIG_CPU_SH5) += intc-sh5.o
/linux-4.4.14/arch/mips/include/asm/
Dtxx9pio.h21 __u32 intc; member
/linux-4.4.14/Documentation/devicetree/bindings/watchdog/
Drt2880-wdt.txt17 interrupt-parent = <&intc>;
Dcadence-wdt.txt19 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/timer/
Dcadence,ttc-timer.txt15 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/xillybus/
Dxillybus.txt19 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/serial/
Dingenic,uart.txt18 interrupt-parent = <&intc>;
Dqca,ar9330-uart.txt32 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt76 interrupt-parent = <&intc>;
91 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/gpio/
Dzx296702-gpio.txt19 interrupt-parent = <&intc>;
Dgpio-zynq.txt30 interrupt-parent = <&intc>;
Dgpio-davinci.txt36 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/i2c/
Di2c-jz4780.txt25 interrupt-parent = <&intc>;
Di2c-davinci.txt23 interrupt-parent = <&intc>;
/linux-4.4.14/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi74 intc: intc@fffc1000 { label
89 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/input/
De3x0-button.txt22 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dqca,ath79-pll.txt6 - compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
/linux-4.4.14/arch/powerpc/boot/dts/
Dtqm8xx.dts74 compatible = "intc,82527";
86 compatible = "intc,82527";
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Dspi-cadence.txt26 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/rtc/
Drtc-omap.txt29 interrupt-parent = <&intc>;
/linux-4.4.14/arch/mips/include/asm/mach-au1x00/
Dgpio-au1000.h25 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) argument
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Domap-mcbsp.txt34 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/display/tilcdc/
Dtilcdc.txt32 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/net/
Ddavinci_emac.txt40 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt32 interrupt-parent = <&intc>;
/linux-4.4.14/Documentation/devicetree/bindings/dma/
Djz4780-dma.txt27 interrupt-parent = <&intc>;

12