1/*
2 * MOXA ART SoCs IRQ chip driver.
3 *
4 * Copyright (C) 2013 Jonas Jensen
5 *
6 * Jonas Jensen <jonas.jensen@gmail.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/irqchip.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/irqdomain.h>
20
21#include <asm/exception.h>
22
23#define IRQ_SOURCE_REG		0
24#define IRQ_MASK_REG		0x04
25#define IRQ_CLEAR_REG		0x08
26#define IRQ_MODE_REG		0x0c
27#define IRQ_LEVEL_REG		0x10
28#define IRQ_STATUS_REG		0x14
29
30#define FIQ_SOURCE_REG		0x20
31#define FIQ_MASK_REG		0x24
32#define FIQ_CLEAR_REG		0x28
33#define FIQ_MODE_REG		0x2c
34#define FIQ_LEVEL_REG		0x30
35#define FIQ_STATUS_REG		0x34
36
37
38struct moxart_irq_data {
39	void __iomem *base;
40	struct irq_domain *domain;
41	unsigned int interrupt_mask;
42};
43
44static struct moxart_irq_data intc;
45
46static void __exception_irq_entry handle_irq(struct pt_regs *regs)
47{
48	u32 irqstat;
49	int hwirq;
50
51	irqstat = readl(intc.base + IRQ_STATUS_REG);
52
53	while (irqstat) {
54		hwirq = ffs(irqstat) - 1;
55		handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
56		irqstat &= ~(1 << hwirq);
57	}
58}
59
60static int __init moxart_of_intc_init(struct device_node *node,
61				      struct device_node *parent)
62{
63	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
64	int ret;
65	struct irq_chip_generic *gc;
66
67	intc.base = of_iomap(node, 0);
68	if (!intc.base) {
69		pr_err("%s: unable to map IC registers\n",
70		       node->full_name);
71		return -EINVAL;
72	}
73
74	intc.domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
75					    intc.base);
76	if (!intc.domain) {
77		pr_err("%s: unable to create IRQ domain\n", node->full_name);
78		return -EINVAL;
79	}
80
81	ret = irq_alloc_domain_generic_chips(intc.domain, 32, 1,
82					     "MOXARTINTC", handle_edge_irq,
83					     clr, 0, IRQ_GC_INIT_MASK_CACHE);
84	if (ret) {
85		pr_err("%s: could not allocate generic chip\n",
86		       node->full_name);
87		irq_domain_remove(intc.domain);
88		return -EINVAL;
89	}
90
91	ret = of_property_read_u32(node, "interrupt-mask",
92				   &intc.interrupt_mask);
93	if (ret)
94		pr_err("%s: could not read interrupt-mask DT property\n",
95		       node->full_name);
96
97	gc = irq_get_domain_generic_chip(intc.domain, 0);
98
99	gc->reg_base = intc.base;
100	gc->chip_types[0].regs.mask = IRQ_MASK_REG;
101	gc->chip_types[0].regs.ack = IRQ_CLEAR_REG;
102	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
103	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
104	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
105
106	writel(0, intc.base + IRQ_MASK_REG);
107	writel(0xffffffff, intc.base + IRQ_CLEAR_REG);
108
109	writel(intc.interrupt_mask, intc.base + IRQ_MODE_REG);
110	writel(intc.interrupt_mask, intc.base + IRQ_LEVEL_REG);
111
112	set_handle_irq(handle_irq);
113
114	return 0;
115}
116IRQCHIP_DECLARE(moxa_moxart_ic, "moxa,moxart-ic", moxart_of_intc_init);
117