Searched refs:i1 (Results 1 - 67 of 67) sorted by relevance

/linux-4.4.14/arch/arm64/crypto/
H A Daes-ce.S46 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3
49 .ifnb \i1
50 aes\de \i1\().16b, \k\().16b
51 aes\mc \i1\().16b, \i1\().16b
62 .macro round_Nx, enc, k, i0, i1, i2, i3
64 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3
66 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3
71 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3
73 .ifnb \i1
74 aes\de \i1\().16b, \k\().16b
81 .ifnb \i1
82 eor \i1\().16b, \i1\().16b, \k2\().16b
91 .macro do_block_Nx, enc, rounds, i0, i1, i2, i3
95 round_Nx \enc, v17, \i0, \i1, \i2, \i3
96 round_Nx \enc, v18, \i0, \i1, \i2, \i3
97 1111: round_Nx \enc, v19, \i0, \i1, \i2, \i3
98 round_Nx \enc, v20, \i0, \i1, \i2, \i3
100 round_Nx \enc, \key, \i0, \i1, \i2, \i3
102 fin_round_Nx \enc, v30, v31, \i0, \i1, \i2, \i3
109 .macro encrypt_block2x, i0, i1, rounds, t0, t1, t2
110 do_block_Nx e, \rounds, \i0, \i1
113 .macro encrypt_block4x, i0, i1, i2, i3, rounds, t0, t1, t2
114 do_block_Nx e, \rounds, \i0, \i1, \i2, \i3
121 .macro decrypt_block2x, i0, i1, rounds, t0, t1, t2
122 do_block_Nx d, \rounds, \i0, \i1
125 .macro decrypt_block4x, i0, i1, i2, i3, rounds, t0, t1, t2
126 do_block_Nx d, \rounds, \i0, \i1, \i2, \i3
/linux-4.4.14/arch/sparc/lib/
H A DNGmemcpy.S86 FUNC_NAME: /* %i0=dst, %i1=src, %i2=len */
95 or %o0, %i1, %i3
112 * %i1: src
119 LOAD(prefetch, %i1, #one_read)
129 EX_LD(LOAD(ldub, %i1, %g1))
131 add %i1, 1, %i1
150 andcc %i1, (16 - 1), %i4
157 sub %i1, %i4, %i1
163 EX_LD(LOAD_TWIN(%i1, %g2, %g3))
181 8: EX_LD(LOAD_TWIN(%i1 + %o4, %o2, %o3))
183 LOAD(prefetch, %i1 + %i3, #one_read)
188 EX_LD(LOAD_TWIN(%i1 + %o5, %g2, %g3))
194 EX_LD(LOAD_TWIN(%i1 + %o7, %o2, %o3))
200 EX_LD(LOAD_TWIN(%i1 + %i3, %g2, %g3))
201 add %i1, 64, %i1
212 add %i1, %i4, %i1
214 9: EX_LD(LOAD_TWIN(%i1 + %o4, %o2, %o3))
216 LOAD(prefetch, %i1 + %i3, #one_read)
221 EX_LD(LOAD_TWIN(%i1 + %o5, %g2, %g3))
227 EX_LD(LOAD_TWIN(%i1 + %o7, %o2, %o3))
233 EX_LD(LOAD_TWIN(%i1 + %i3, %g2, %g3))
234 add %i1, 64, %i1
245 add %i1, %i4, %i1
252 EX_LD(LOAD_TWIN(%i1, %o4, %o5))
257 1: EX_LD(LOAD_TWIN(%i1 + %o7, %o2, %o3))
258 LOAD(prefetch, %i1 + %o1, #one_read)
261 EX_LD(LOAD_TWIN(%i1 + %g2, %o4, %o5))
264 EX_LD(LOAD_TWIN(%i1 + %g3, %o2, %o3))
267 EX_LD(LOAD_TWIN(%i1 + %o1, %o4, %o5))
268 add %i1, 64, %i1
276 add %i1, 0x8, %i1
285 1: EX_LD(LOAD_TWIN(%i1 + %g0, %o4, %o5))
286 EX_LD(LOAD_TWIN(%i1 + %o7, %o2, %o3))
287 LOAD(prefetch, %i1 + %o1, #one_read)
290 EX_LD(LOAD_TWIN(%i1 + %g2, %o4, %o5))
293 EX_LD(LOAD_TWIN(%i1 + %g3, %o2, %o3))
294 add %i1, 64, %i1
312 sub %o0, %i1, %i3
318 sub %o0, %i1, %i3
324 EX_LD(LOAD(ldx, %i1, %o4))
325 add %i1, 0x08, %i1
326 EX_LD(LOAD(ldx, %i1, %g1))
327 sub %i1, 0x08, %i1
328 EX_ST(STORE(stx, %o4, %i1 + %i3))
329 add %i1, 0x8, %i1
330 EX_ST(STORE(stx, %g1, %i1 + %i3))
332 add %i1, 0x8, %i1
337 EX_LD(LOAD(ldx, %i1, %o4))
338 EX_ST(STORE(stx, %o4, %i1 + %i3))
339 add %i1, 0x8, %i1
344 EX_LD(LOAD(lduw, %i1, %i5))
345 EX_ST(STORE(stw, %i5, %i1 + %i3))
346 add %i1, 0x4, %i1
361 EX_LD(LOAD(ldub, %i1, %i5))
362 EX_ST(STORE(stb, %i5, %i1 + %i3))
364 add %i1, 1, %i1
366 2: add %i1, %i3, %o0
367 andcc %i1, 0x7, %g1
377 andn %i1, 0x7, %i1
378 EX_LD(LOAD(ldx, %i1, %g2))
382 1: add %i1, 0x8, %i1
383 EX_LD(LOAD(ldx, %i1, %g3))
395 add %i1, %g1, %i1
397 sub %o0, %i1, %i3
403 sub %o0, %i1, %i3
407 EX_LD(LOAD(lduw, %i1, %g1))
408 EX_ST(STORE(stw, %g1, %i1 + %i3))
410 add %i1, 4, %i1
418 EX_LD(LOAD(ldub, %i1, %g1))
419 EX_ST(STORE(stb, %g1, %i1 + %i3))
421 add %i1, 1, %i1
H A DNGpage.S23 prefetch [%i1 + 0x00], #one_read
24 prefetch [%i1 + 0x40], #one_read
26 1: prefetch [%i1 + 0x80], #one_read
27 prefetch [%i1 + 0xc0], #one_read
28 ldda [%i1 + 0x00] %asi, %o2
29 ldda [%i1 + 0x10] %asi, %o4
30 ldda [%i1 + 0x20] %asi, %l2
31 ldda [%i1 + 0x30] %asi, %l4
40 ldda [%i1 + 0x40] %asi, %o2
41 ldda [%i1 + 0x50] %asi, %o4
42 ldda [%i1 + 0x60] %asi, %l2
43 ldda [%i1 + 0x70] %asi, %l4
52 add %i1, 128, %i1
H A Dmemcpy.S382 ldub [%i1], %g5
383 add %i1, 1, %i1
389 ldub [%i1], %g3
390 add %i1, 2, %i1
393 ldub [%i1 - 1], %g3
397 and %i1, 3, %g2
399 and %i1, -4, %i1
412 ld [%i1], %i3
414 ld [%i1 + 4], %i4
418 ld [%i1], %i4
420 ld [%i1 + 4], %i5
423 add %i1, -4, %i1
425 ld [%i1], %g1
427 ld [%i1 + 4], %i3
430 add %i1, 4, %i1
432 ld [%i1], %i5
434 ld [%i1 + 4], %g1
437 add %i1, 8, %i1
439 ld [%i1], %i3
447 ld [%i1 + 4], %i4
453 ld [%i1 + 8], %i5
459 ld [%i1 + 12], %g1
464 add %i1, 16, %i1
468 ld [%i1], %i3
474 sub %i1, %g3, %i1
480 ldub [%i1], %g2
481 add %i1, 2, %i1
484 ldub [%i1 - 1], %g2
489 ldub [%i1], %g2
H A Dmuldi3.S25 wr %g0, %i1, %y
27 and %i1, %g2, %g2
65 mov %i1, %o0
H A Ddivdi3.S29 sub %g0,%i1,%o0
35 mov %o5,%i1
52 mov %i1,%i3
269 mov %l1,%i1
272 sub %g0,%i1,%o0
278 mov %l3,%i1
H A Dudivdi3.S28 mov %i1,%i3
257 mov %l1,%i1
H A Dchecksum_32.S567 mov %i1, %o0
574 add %i1, %i2, %i1
576 mov %i1, %o0
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4.xml.h352 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE() argument
354 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_OP() argument
374 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
376 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
378 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
380 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
382 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
384 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
396 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } REG_MDP4_OVLP_STAGE_CO3() argument
398 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } REG_MDP4_OVLP_STAGE_CO3_SEL() argument
414 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_MV() argument
416 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_MV_VAL() argument
418 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_BV() argument
420 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument
422 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_BV() argument
424 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_BV_VAL() argument
426 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_LV() argument
428 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument
430 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_LV() argument
432 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_LV_VAL() argument
438 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } REG_MDP4_LUTN_LUT() argument
440 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } REG_MDP4_LUTN_LUT_VAL() argument
569 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_MV() argument
571 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_MV_VAL() argument
573 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_BV() argument
575 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_BV_VAL() argument
577 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_BV() argument
579 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_BV_VAL() argument
581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_LV() argument
583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_LV_VAL() argument
585 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_LV() argument
587 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_LV_VAL() argument
820 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_MV() argument
822 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_MV_VAL() argument
824 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_BV() argument
826 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument
828 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_BV() argument
830 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_BV_VAL() argument
832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_LV() argument
834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument
836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_LV() argument
838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_LV_VAL() argument
/linux-4.4.14/arch/arm64/kvm/
H A Dsys_regs.h120 static inline int cmp_sys_reg(const struct sys_reg_desc *i1, cmp_sys_reg() argument
123 BUG_ON(i1 == i2); cmp_sys_reg()
124 if (!i1) cmp_sys_reg()
128 if (i1->Op0 != i2->Op0) cmp_sys_reg()
129 return i1->Op0 - i2->Op0; cmp_sys_reg()
130 if (i1->Op1 != i2->Op1) cmp_sys_reg()
131 return i1->Op1 - i2->Op1; cmp_sys_reg()
132 if (i1->CRn != i2->CRn) cmp_sys_reg()
133 return i1->CRn - i2->CRn; cmp_sys_reg()
134 if (i1->CRm != i2->CRm) cmp_sys_reg()
135 return i1->CRm - i2->CRm; cmp_sys_reg()
136 return i1->Op2 - i2->Op2; cmp_sys_reg()
H A Dsys_regs.c1617 const struct sys_reg_desc *i1, *i2, *end1, *end2; walk_sys_regs() local
1622 i1 = get_target_table(vcpu->arch.target, true, &num); walk_sys_regs()
1623 end1 = i1 + num; walk_sys_regs()
1627 BUG_ON(i1 == end1 || i2 == end2); walk_sys_regs()
1630 while (i1 || i2) { walk_sys_regs()
1631 int cmp = cmp_sys_reg(i1, i2); walk_sys_regs()
1635 if (i1->reg) { walk_sys_regs()
1636 if (!copy_reg_to_user(i1, &uind)) walk_sys_regs()
1649 if (cmp <= 0 && ++i1 == end1) walk_sys_regs()
1650 i1 = NULL; walk_sys_regs()
/linux-4.4.14/arch/arm/kernel/
H A Dinsn.c8 unsigned long s, j1, j2, i1, i2, imm10, imm11; __arm_gen_branch_thumb2() local
19 i1 = (offset >> 23) & 0x1; __arm_gen_branch_thumb2()
24 j1 = (!i1) ^ s; __arm_gen_branch_thumb2()
/linux-4.4.14/arch/arm/kvm/
H A Dcoproc.h128 static inline int cmp_reg(const struct coproc_reg *i1, cmp_reg() argument
131 BUG_ON(i1 == i2); cmp_reg()
132 if (!i1) cmp_reg()
136 if (i1->CRn != i2->CRn) cmp_reg()
137 return i1->CRn - i2->CRn; cmp_reg()
138 if (i1->CRm != i2->CRm) cmp_reg()
139 return i1->CRm - i2->CRm; cmp_reg()
140 if (i1->Op1 != i2->Op1) cmp_reg()
141 return i1->Op1 - i2->Op1; cmp_reg()
142 if (i1->Op2 != i2->Op2) cmp_reg()
143 return i1->Op2 - i2->Op2; cmp_reg()
144 return i2->is_64 - i1->is_64; cmp_reg()
H A Dcoproc.c1135 const struct coproc_reg *i1, *i2, *end1, *end2; walk_cp15() local
1140 i1 = get_target_table(vcpu->arch.target, &num); walk_cp15()
1141 end1 = i1 + num; walk_cp15()
1145 BUG_ON(i1 == end1 || i2 == end2); walk_cp15()
1148 while (i1 || i2) { walk_cp15()
1149 int cmp = cmp_reg(i1, i2); walk_cp15()
1153 if (i1->reg) { walk_cp15()
1154 if (!copy_reg_to_user(i1, &uind)) walk_cp15()
1167 if (cmp <= 0 && ++i1 == end1) walk_cp15()
1168 i1 = NULL; walk_cp15()
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp5/
H A Dmdp5.xml.h270 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_W() argument
272 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_W_REG() argument
292 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_R() argument
294 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_R_REG() argument
324 static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); } REG_MDP5_MDP_IGC() argument
326 static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } REG_MDP5_MDP_IGC_LUT() argument
328 static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } REG_MDP5_MDP_IGC_LUT_REG() argument
379 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } REG_MDP5_CTL_LAYER() argument
381 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } REG_MDP5_CTL_LAYER_REG() argument
514 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } REG_MDP5_CTL_LAYER_EXT() argument
516 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } REG_MDP5_CTL_LAYER_EXT_REG() argument
643 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
645 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
659 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
661 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
675 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
677 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
685 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
687 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
945 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT() argument
947 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT_LR() argument
973 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT_TB() argument
999 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument
1116 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND() argument
1118 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_OP_MODE() argument
1140 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_ALPHA() argument
1142 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_ALPHA() argument
1144 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
1146 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
1148 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
1150 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1152 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1154 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1156 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1158 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1689 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PRECLAMP() argument
1691 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument
1705 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument
1707 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument
1721 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PREBIAS() argument
1723 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument
1731 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTBIAS() argument
1733 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument
/linux-4.4.14/drivers/video/fbdev/
H A Dc2p_core.h20 static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, _transp() argument
23 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; _transp()
25 d[i1] ^= t; _transp()
/linux-4.4.14/drivers/isdn/mISDN/
H A Dl1oip_codec.c324 int i1, i2, c, sample; l1oip_4bit_alloc() local
338 i1 = 0; l1oip_4bit_alloc()
339 while (i1 < 256) { l1oip_4bit_alloc()
341 c = ulaw_to_4bit[i1]; l1oip_4bit_alloc()
343 c = alaw_to_4bit[i1]; l1oip_4bit_alloc()
346 table_com[(i1 << 8) | i2] |= (c << 4); l1oip_4bit_alloc()
347 table_com[(i2 << 8) | i1] |= c; l1oip_4bit_alloc()
350 i1++; l1oip_4bit_alloc()
354 i1 = 0; l1oip_4bit_alloc()
355 while (i1 < 16) { l1oip_4bit_alloc()
357 sample = _4bit_to_ulaw[i1]; l1oip_4bit_alloc()
359 sample = _4bit_to_alaw[i1]; l1oip_4bit_alloc()
362 table_dec[(i1 << 4) | i2] |= (sample << 8); l1oip_4bit_alloc()
363 table_dec[(i2 << 4) | i1] |= sample; l1oip_4bit_alloc()
366 i1++; l1oip_4bit_alloc()
H A Ddsp_cmx.c388 int memb = 0, i, ii, i1, i2; dsp_cmx_hardware() local
858 i1 = 0; dsp_cmx_hardware()
860 while (i1 < ii) { dsp_cmx_hardware()
861 if (freeslots[i1]) dsp_cmx_hardware()
863 i1++; dsp_cmx_hardware()
865 if (i1 == ii) { dsp_cmx_hardware()
875 i2 = i1 + 1; dsp_cmx_hardware()
893 member->dsp->pcm_slot_tx = i1; dsp_cmx_hardware()
896 nextm->dsp->pcm_slot_rx = i1; dsp_cmx_hardware()
/linux-4.4.14/include/sound/
H A Dpcm_params.h293 static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2) snd_interval_eq() argument
295 if (i1->empty) snd_interval_eq()
298 return i1->empty; snd_interval_eq()
299 return i1->min == i2->min && i1->openmin == i2->openmin && snd_interval_eq()
300 i1->max == i2->max && i1->openmax == i2->openmax; snd_interval_eq()
/linux-4.4.14/drivers/connector/
H A Dcn_queue.c68 int cn_cb_equal(struct cb_id *i1, struct cb_id *i2) cn_cb_equal() argument
70 return ((i1->idx == i2->idx) && (i1->val == i2->val)); cn_cb_equal()
/linux-4.4.14/arch/sparc/prom/
H A Dcif.S39 ldx [%i1 + 0x000], %l2
/linux-4.4.14/arch/sparc/include/asm/
H A Dttable.h244 stx %i1, [%sp + STACK_BIAS + 0x48]; \
265 stx %i1, [%sp + STACK_BIAS + 0x48]; \
296 stxa %i1, [%g1 + %g3] ASI; \
323 stxa %i1, [%sp + STACK_BIAS + 0x48] %asi; \
357 stx %i1, [%g3 + TI_REG_WINDOW + 0x48]; \
392 stwa %i1, [%g1 + %g3] ASI; \
422 stwa %i1, [%sp + 0x24] %asi; \
456 stw %i1, [%g3 + TI_REG_WINDOW + 0x24]; \
500 ldx [%sp + STACK_BIAS + 0x48], %i1; \
524 ldx [%sp + STACK_BIAS + 0x48], %i1; \
556 ldxa [%g1 + %g2] ASI, %i1; \
581 ldxa [%sp + STACK_BIAS + 0x48] %asi, %i1; \
616 lduwa [%g1 + %g2] ASI, %i1; \
644 lduwa [%sp + 0x24] %asi, %i1; \
H A Dswitch_to_64.h64 "i0", "i1", "i2", "i3", "i4", "i5", \
H A Dswitch_to_32.h98 "i0", "i1", "i2", "i3", "i4", "i5", \
/linux-4.4.14/include/net/sctp/
H A Dsm.h314 * Then, s1 is said to be equal to s2 if and only if i1 is equal to i2,
320 * (i1 < i2 and i2 - i1 < 2^(SERIAL_BITS - 1)) or
321 * (i1 > i2 and i1 - i2 > 2^(SERIAL_BITS - 1))
326 * (i1 < i2 and i2 - i1 > 2^(SERIAL_BITS - 1)) or
327 * (i1 > i2 and i1 - i2 < 2^(SERIAL_BITS - 1))
/linux-4.4.14/arch/cris/arch-v10/kernel/
H A Dtime.c149 IO_STATE( R_TIMER_CTRL, i1, clr) | timer_interrupt()
204 IO_STATE( R_TIMER_CTRL, i1, nop) | time_init()
214 IO_STATE( R_TIMER_CTRL, i1, nop) | time_init()
224 IO_STATE(R_TIMER_CTRL, i1, nop) | time_init()
234 IO_STATE(R_TIMER_CTRL, i1, nop) | time_init()
H A Dfasttimer.c195 IO_STATE(R_TIMER_CTRL, i1, clr); start_timer1()
358 *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i1, clr); timer1_handler()
/linux-4.4.14/arch/blackfin/include/asm/
H A Dcontext.S28 [--sp] = i1;
100 [--sp] = i1;
159 [--sp] = i1;
268 i1 = [sp++]; define
338 i1 = [sp++]; define
H A Ddpmc.h77 [--sp] = i1;
165 i1 = [sp++];
/linux-4.4.14/arch/parisc/math-emu/
H A Dfpudispatch.c1129 struct { u_int i1; u_int i2; } ints; decode_06() member in struct:__anon2224::__anon2225
1156 &mtmp.ints.i1,&status)) decode_06()
1159 &atmp.ints.i1,&atmp.ints.i1,&status)) decode_06()
1164 if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, decode_06()
1167 if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, decode_06()
1179 if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, decode_06()
1182 if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, decode_06()
1192 fpregs[tm] = mtmp.ints.i1; decode_06()
1194 fpregs[ta] = atmp.ints.i1; decode_06()
1226 if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, decode_06()
1229 if (sgl_to_sgl_fcnvfxt(&fpregs[ta],&atmp.ints.i1, decode_06()
1230 &atmp.ints.i1,&status)) decode_06()
1234 if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, decode_06()
1237 if (sgl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, decode_06()
1245 fpregs[tm] = mtmp.ints.i1; decode_06()
1246 fpregs[ta] = atmp.ints.i1; decode_06()
1268 struct { u_int i1; u_int i2; } ints; decode_26() member in struct:__anon2226::__anon2227
1291 if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status)) decode_26()
1293 if (dbl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status)) decode_26()
1299 fpregs[tm] = mtmp.ints.i1; decode_26()
1301 fpregs[ta] = atmp.ints.i1; decode_26()
1327 if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status)) decode_26()
1329 if (sgl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status)) decode_26()
1335 fpregs[tm] = mtmp.ints.i1; decode_26()
1336 fpregs[ta] = atmp.ints.i1; decode_26()
/linux-4.4.14/arch/sparc/kernel/
H A Dsyscalls.S167 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
181 srl %i1, 0, %o1
197 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
210 mov %i1, %o1
228 srl %i1, 0, %o1 ! IEU0 Group
250 mov %i1, %o1 ! IEU1
H A Dwinfixup.S64 stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
81 stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
H A Drtrap_64.S165 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
182 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
H A Dentry.S957 ld [%sp + STACKFRAME_SZ + PT_I1], %i1
969 mov %i1, %o1
1017 mov %i1, %o1
1175 mov %i1, %o1 ! udelay_val
1189 mov %i1, %o1 ! udelay_val
H A Detrap_64.S140 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
H A Dsun4d_smp.c299 register unsigned long a1 asm("i1") = arg1; sun4d_cross_call()
H A Dprocess_64.c119 printk("i0: %08x i1: %08x i2: %08x i3: %08x " show_regwindow32()
159 printk("i0: %016lx i1: %016lx i2: %016lx i3: %016lx\n", show_regwindow()
H A Dleon_smp.c389 register unsigned long a1 asm("i1") = arg1; leon_cross_call()
/linux-4.4.14/arch/ia64/include/asm/
H A Dkprobes.h35 #define BRL_INST(i1, i2) ((long)((0xcL << 37) | /* brl */ \
37 (((i1) & 1) << 36) | ((i2) << 13))) /* imm */
/linux-4.4.14/tools/perf/arch/sparc/util/
H A Ddwarf-regs.c21 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7",
/linux-4.4.14/tools/perf/util/
H A Dstring.c277 int i1 = strlen(s1); strtailcmp() local
279 while (--i1 >= 0 && --i2 >= 0) { strtailcmp()
280 if (s1[i1] != s2[i2]) strtailcmp()
281 return s1[i1] - s2[i2]; strtailcmp()
/linux-4.4.14/fs/jffs2/
H A Dcompr_rubin.c105 long i0, i1; encode() local
126 i1 = rs->p - i0; encode()
131 rs->p = i1; encode()
/linux-4.4.14/crypto/
H A Dvmac.c75 #define MUL32(i1, i2) ((u64)(u32)(i1)*(u32)(i2))
77 #define PMUL64(rh, rl, i1, i2) /* Assumes m doesn't overflow */ \
79 u64 _i1 = (i1), _i2 = (i2); \
86 #define MUL64(rh, rl, i1, i2) \
88 u64 _i1 = (i1), _i2 = (i2); \
/linux-4.4.14/arch/blackfin/include/uapi/asm/
H A Dptrace.h67 long i1; member in struct:pt_regs
/linux-4.4.14/arch/blackfin/kernel/
H A Dsignal.c65 RESTORE(i0); RESTORE(i1); RESTORE(i2); RESTORE(i3); rt_restore_sigcontext()
126 SETUP(i0); SETUP(i1); SETUP(i2); SETUP(i3); rt_setup_sigcontext()
H A Dkgdb.c33 gdb_regs[BFIN_I1] = regs->i1; pt_regs_to_gdb_regs()
109 regs->i1 = gdb_regs[BFIN_I1]; gdb_regs_to_pt_regs()
H A Dasm-offsets.c74 DEFINE(PT_I1, offsetof(struct pt_regs, i1)); main()
H A Dtrace.c974 fp->b1, fp->l1, fp->m1, fp->i1); show_regs()
/linux-4.4.14/arch/arm/crypto/
H A Daes-armv4.S279 and r8,lr,r2,lsr#16 @ i1
292 and r8,lr,r3,lsr#8 @ i1
341 and r8,lr,r2,lsr#16 @ i1
354 and r8,lr,r3,lsr#8 @ i1
974 and r8,lr,r2 @ i1
987 and r8,lr,r3,lsr#8 @ i1
1047 and r8,lr,r2 @ i1
1061 and r8,lr,r3,lsr#8 @ i1
/linux-4.4.14/drivers/staging/lustre/lustre/llite/
H A Dllite_lib.c2114 struct inode *i1, struct inode *i2, ll_prep_md_op_data()
2118 LASSERT(i1 != NULL); ll_prep_md_op_data()
2120 if (namelen > ll_i2sbi(i1)->ll_namelen) ll_prep_md_op_data()
2129 ll_i2gids(op_data->op_suppgids, i1, i2); ll_prep_md_op_data()
2130 op_data->op_fid1 = *ll_inode2fid(i1); ll_prep_md_op_data()
2156 if (opc == LUSTRE_OPC_CREATE && i1 == i2 && S_ISREG(i2->i_mode) && ll_prep_md_op_data()
2166 /* When called by ll_setattr_raw, file is i1. */ ll_prep_md_op_data()
2167 if (ll_i2info(i1)->lli_flags & LLIF_DATA_MODIFIED) ll_prep_md_op_data()
2113 ll_prep_md_op_data(struct md_op_data *op_data, struct inode *i1, struct inode *i2, const char *name, int namelen, int mode, __u32 opc, void *data) ll_prep_md_op_data() argument
H A Dnamei.c291 void ll_i2gids(__u32 *suppgids, struct inode *i1, struct inode *i2) ll_i2gids() argument
297 LASSERT(i1 != NULL); ll_i2gids()
300 suppgids[0] = ll_i2suppgid(i1); ll_i2gids()
H A Dllite_internal.h645 void ll_i2gids(__u32 *suppgids, struct inode *i1, struct inode *i2);
792 struct inode *i1, struct inode *i2,
/linux-4.4.14/drivers/isdn/hisax/
H A Dnj_s.c40 debugl1(cs, "tiger: i1 %x %x", s1val, val); netjet_s_interrupt()
H A Dnj_u.c40 debugl1(cs, "tiger: i1 %x %x", sval, val); netjet_u_interrupt()
/linux-4.4.14/drivers/block/
H A Dumem.c194 int i, i1; dump_regs() local
200 for (i1 = 0; i1 < 16; i1++) dump_regs()
/linux-4.4.14/arch/blackfin/mach-common/
H A Dinterrupt.S42 [--sp] = i1;
/linux-4.4.14/fs/logfs/
H A Dlogfs_abi.h38 * 1 - i1 indirect blocks
44 * 7 - ifile i1 indirect blocks
/linux-4.4.14/fs/fat/
H A Dinode.c1799 * write data and metadata corresponding to i1 and i2. The io is
1806 int fat_flush_inodes(struct super_block *sb, struct inode *i1, struct inode *i2) fat_flush_inodes() argument
1811 if (i1) fat_flush_inodes()
1812 ret = writeback_inode(i1); fat_flush_inodes()
H A Dfat.h381 extern int fat_flush_inodes(struct super_block *sb, struct inode *i1,
/linux-4.4.14/net/decnet/
H A Ddn_dev.c909 unsigned char *i1, *i2; dn_send_router_hello() local
946 i1 = ptr++; dn_send_router_hello()
954 *i1 = 8 + *i2; dn_send_router_hello()
/linux-4.4.14/drivers/isdn/i4l/
H A Disdn_net.c2027 isdn_net_swap_usage(int i1, int i2) isdn_net_swap_usage() argument
2029 int u1 = dev->usage[i1] & ISDN_USAGE_EXCLUSIVE; isdn_net_swap_usage()
2033 printk(KERN_DEBUG "n_fi: usage of %d and %d\n", i1, i2); isdn_net_swap_usage()
2035 dev->usage[i1] &= ~ISDN_USAGE_EXCLUSIVE; isdn_net_swap_usage()
2036 dev->usage[i1] |= u2; isdn_net_swap_usage()
/linux-4.4.14/arch/sparc/mm/
H A Dultra.S308 mov %i1, %o1
/linux-4.4.14/arch/x86/crypto/
H A Dchacha20-ssse3-x86_64.S126 # o1 = i1 ^ (x1 + s1)
/linux-4.4.14/arch/sparc/crypto/
H A Dcamellia_asm.S36 ld [%o0 + 0x04], %f1 ! i1, k[1]
/linux-4.4.14/sound/pci/cs46xx/
H A Dcs46xx_dsp_scb_types.h1126 u32 i1; member in struct:dsp_magic_snoop_task
H A Ddsp_spos_scb_lib.c1133 /* 1 */ 0, /* i1 */ cs46xx_dsp_create_magic_snoop_scb()
/linux-4.4.14/drivers/scsi/
H A Dadvansys.c349 ASC_SCSIQ_1 i1; member in struct:asc_risc_q

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