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/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5.xml.h207 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); } in REG_MDP5_MDP() argument
209 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0);… in REG_MDP5_MDP_HW_VERSION() argument
229 …tic inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0)… in REG_MDP5_MDP_DISP_INTF_SEL() argument
255 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); } in REG_MDP5_MDP_INTR_EN() argument
257 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0)… in REG_MDP5_MDP_INTR_STATUS() argument
259 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0);… in REG_MDP5_MDP_INTR_CLEAR() argument
261 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0… in REG_MDP5_MDP_HIST_INTR_EN() argument
263 … inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0)… in REG_MDP5_MDP_HIST_INTR_STATUS() argument
265 …c inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0)… in REG_MDP5_MDP_HIST_INTR_CLEAR() argument
267 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); } in REG_MDP5_MDP_SPARE_0() argument
[all …]
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4.xml.h318 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument
320 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument
322 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument
336 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument
338 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument
340 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE() argument
352 …tic inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE() argument
354 … inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_OP() argument
374 …e uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_O… in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
376 …e uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_O… in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
[all …]
/linux-4.4.14/arch/arm64/crypto/
Daes-ce.S46 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3
47 aes\de \i0\().16b, \k\().16b
48 aes\mc \i0\().16b, \i0\().16b
62 .macro round_Nx, enc, k, i0, i1, i2, i3
64 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3
66 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3
71 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3
72 aes\de \i0\().16b, \k\().16b
80 eor \i0\().16b, \i0\().16b, \k2\().16b
91 .macro do_block_Nx, enc, rounds, i0, i1, i2, i3
[all …]
/linux-4.4.14/arch/sparc/lib/
Ddivdi3.S25 cmp %i0,0
32 sub %g0,%i0,%o0
34 mov %o4,%i0
53 cmp %o4,%i0
57 subcc %i0,%o4,%g0
60 sub %i0,%o4,%i0 ! this kills msb of n
61 addx %i0,%i0,%i0 ! so this cannot give carry
64 subcc %i0,%o4,%g0
68 sub %i0,%o4,%i0 ! this kills msb of n
69 4: sub %i0,%o4,%i0
[all …]
Dudivdi3.S29 cmp %o3,%i0
34 subcc %i0,%o3,%g0
37 sub %i0,%o3,%i0 ! this kills msb of n
38 addx %i0,%i0,%i0 ! so this cannot give carry
41 subcc %i0,%o3,%g0
45 sub %i0,%o3,%i0 ! this kills msb of n
46 4: sub %i0,%o3,%i0
47 5: addxcc %i0,%i0,%i0
53 sub %i0,%o3,%i0
61 mov %i0,%o2
[all …]
Dxor.S257 sub %i0, 64, %i0
300 subcc %i0, 64, %i0
358 srlx %i0, 6, %g1
359 mov %i1, %i0
366 ldda [%i0 + 0x00] %asi, %o0 /* %o0/%o1 = dest + 0x00 */
367 ldda [%i0 + 0x10] %asi, %o2 /* %o2/%o3 = dest + 0x10 */
368 ldda [%i0 + 0x20] %asi, %o4 /* %o4/%o5 = dest + 0x20 */
369 ldda [%i0 + 0x30] %asi, %l2 /* %l2/%l3 = dest + 0x30 */
370 prefetch [%i0 + 0x40], #n_writes
373 stxa %o0, [%i0 + 0x00] %asi
[all …]
DNGpage.S32 stxa %o2, [%i0 + 0x00] %asi
33 stxa %o3, [%i0 + 0x08] %asi
34 stxa %o4, [%i0 + 0x10] %asi
35 stxa %o5, [%i0 + 0x18] %asi
36 stxa %l2, [%i0 + 0x20] %asi
37 stxa %l3, [%i0 + 0x28] %asi
38 stxa %l4, [%i0 + 0x30] %asi
39 stxa %l5, [%i0 + 0x38] %asi
44 stxa %o2, [%i0 + 0x40] %asi
45 stxa %o3, [%i0 + 0x48] %asi
[all …]
Dmemcpy.S376 andcc %i0, 3, %g0
378 andcc %i0, 1, %g0
380 andcc %i0, 2, %g0
384 stb %g5, [%i0]
387 add %i0, 1, %i0
391 stb %g3, [%i0]
394 add %i0, 2, %i0
395 stb %g3, [%i0 - 1]
413 add %i0, -8, %i0
419 add %i0, -12, %i0
[all …]
Dmuldi3.S69 mov %i0, %o0
73 mov %l2, %i0
74 add %l2, %l0, %i0
DNGmemcpy.S92 mov %i0, %o0
413 restore EX_RETVAL(%i0), %g0, %o0
423 restore EX_RETVAL(%i0), %g0, %o0
Dcopy_user.S375 mov %i0, %o0
Dchecksum_32.S566 mov %i0, %o1
/linux-4.4.14/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h356 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK() argument
358 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA() argument
570 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN() argument
572 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0() argument
574 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1() argument
576 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2() argument
578 …nline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH() argument
580 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0() argument
582 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1() argument
799 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN() argument
[all …]
Dmmss_cc.xml.h63 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0);… in REG_MMSS_CC_CLK() argument
65 …tic inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_CC() argument
82 …tic inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_MD() argument
96 …tic inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_NS() argument
/linux-4.4.14/drivers/gpu/drm/msm/adreno/
Da4xx.xml.h397 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT() argument
399 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL() argument
412 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } in REG_A4XX_RB_MRT_BUF_INFO() argument
445 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } in REG_A4XX_RB_MRT_BASE() argument
447 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL3() argument
455 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } in REG_A4XX_RB_MRT_BLEND_CONTROL() argument
901 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP() argument
903 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MIN() argument
905 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MAX() argument
911 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_TP() argument
[all …]
Da3xx.xml.h663 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT() argument
665 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT_REG() argument
964 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT() argument
966 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT_CONTROL() argument
989 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_INFO() argument
1016 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_BASE() argument
1024 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } in REG_A3XX_RB_MRT_BLEND_CONTROL() argument
1574 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK() argument
1576 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0;… in REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE() argument
1578 …ic inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET() argument
[all …]
Da2xx.xml.h455 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } in REG_A2XX_VSC_PIPE() argument
457 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } in REG_A2XX_VSC_PIPE_CONFIG() argument
459 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } in REG_A2XX_VSC_PIPE_DATA_ADDRESS() argument
461 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } in REG_A2XX_VSC_PIPE_DATA_LENGTH() argument
/linux-4.4.14/fs/jffs2/
Dcompr_rubin.c105 long i0, i1; in encode() local
119 i0 = A * rs->p / (A + B); in encode()
120 if (i0 <= 0) in encode()
121 i0 = 1; in encode()
123 if (i0 >= rs->p) in encode()
124 i0 = rs->p - 1; in encode()
126 i1 = rs->p - i0; in encode()
129 rs->p = i0; in encode()
132 rs->q += i0; in encode()
203 long i0, threshold; in decode() local
[all …]
/linux-4.4.14/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h144 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } in REG_HDMI_AVI_INFO() argument
148 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } in REG_HDMI_GENERIC0() argument
152 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } in REG_HDMI_GENERIC1() argument
154 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR() argument
156 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR_0() argument
164 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } in REG_HDMI_ACR_1() argument
361 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION() argument
363 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION_REG() argument
/linux-4.4.14/arch/cris/arch-v10/kernel/
Dtime.c152 IO_STATE( R_TIMER_CTRL, i0, clr) | in timer_interrupt()
156 *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr); in timer_interrupt()
207 IO_STATE( R_TIMER_CTRL, i0, nop) | in time_init()
217 IO_STATE( R_TIMER_CTRL, i0, nop) | in time_init()
227 IO_STATE(R_TIMER_CTRL, i0, nop) | in time_init()
237 IO_STATE(R_TIMER_CTRL, i0, nop) | in time_init()
/linux-4.4.14/arch/sparc/kernel/
Dsyscalls.S165 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
178 srl %i0, 0, %o0
195 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
208 mov %i0, %o0
224 srl %i0, 0, %o0 ! IEU0
235 mov %i0, %l5 ! IEU1
248 mov %i0, %o0 ! IEU0
259 mov %i0, %l5 ! IEU0
Dwinfixup.S63 stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
80 stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
Dentry.S955 ld [%sp + STACKFRAME_SZ + PT_I0], %i0
967 mov %i0, %o0
1016 mov %i0, %o0
1025 mov %i0, %l5
1171 mov %i0, %o0 ! round multiplier up so large ns ok
1184 mov %i0, %o0
1221 st %i0, [%sp + STACKFRAME_SZ + PT_G0] ! for restarting syscalls
Drtrap_64.S165 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
181 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
Dhvcalls.S697 mov %i0, %o0
709 mov %i0, %o0
Detrap_64.S139 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
/linux-4.4.14/drivers/gpu/drm/msm/edp/
Dedp.xml.h275 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } in REG_EDP_PHY_LN() argument
277 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } in REG_EDP_PHY_LN_PD_CTL() argument
/linux-4.4.14/arch/sparc/include/asm/
Dwinmacro.h20 std %i0, [%reg + RW_I0]; \
31 ldd [%reg + RW_I0], %i0; \
38 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
65 std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
Dttable.h243 stx %i0, [%sp + STACK_BIAS + 0x40]; \
264 stx %i0, [%sp + STACK_BIAS + 0x40]; \
295 stxa %i0, [%g1 + %g0] ASI; \
322 stxa %i0, [%sp + STACK_BIAS + 0x40] %asi; \
356 stx %i0, [%g3 + TI_REG_WINDOW + 0x40]; \
391 stwa %i0, [%g1 + %g0] ASI; \
421 stwa %i0, [%sp + 0x20] %asi; \
455 stw %i0, [%g3 + TI_REG_WINDOW + 0x20]; \
499 ldx [%sp + STACK_BIAS + 0x40], %i0; \
523 ldx [%sp + STACK_BIAS + 0x40], %i0; \
[all …]
Dhead_32.h66 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
/linux-4.4.14/arch/sparc/prom/
Dcif.S22 mov %i0, %o0 ! prom_args
41 mov %i0, %o0
/linux-4.4.14/arch/blackfin/include/asm/
Dcontext.S27 [--sp] = i0;
99 [--sp] = i0;
158 [--sp] = i0;
269 i0 = [sp++]; define
339 i0 = [sp++]; define
Ddpmc.h76 [--sp] = i0;
166 i0 = [sp++];
/linux-4.4.14/arch/sparc/power/
Dhibernate_asm.S41 mov %o0, %i0
44 mov %o0, %i0
/linux-4.4.14/arch/sparc/net/
Dbpf_jit_asm.S102 mov %i0, %o0; \
138 mov %i0, %o0; \
/linux-4.4.14/arch/arm/crypto/
Daes-armv4.S264 and r7,lr,r1,lsr#16 @ i0
277 and r7,lr,r2,lsr#8 @ i0
290 and r7,lr,r3 @ i0
326 and r7,lr,r1,lsr#16 @ i0
339 and r7,lr,r2,lsr#8 @ i0
352 and r7,lr,r3 @ i0
959 and r7,lr,r1 @ i0
972 and r7,lr,r2,lsr#8 @ i0
985 and r7,lr,r3,lsr#16 @ i0
1031 and r7,lr,r1 @ i0
[all …]
/linux-4.4.14/arch/blackfin/include/uapi/asm/
Dptrace.h68 long i0; member
/linux-4.4.14/drivers/char/hw_random/
Dn2-asm.S30 mov %i0, %o0
/linux-4.4.14/arch/blackfin/kernel/
Dsignal.c65 RESTORE(i0); RESTORE(i1); RESTORE(i2); RESTORE(i3); in rt_restore_sigcontext()
126 SETUP(i0); SETUP(i1); SETUP(i2); SETUP(i3); in rt_setup_sigcontext()
Dpseudodbg.c58 val = &fp->i0; in fix_up_reg()
Dkgdb.c32 gdb_regs[BFIN_I0] = regs->i0; in pt_regs_to_gdb_regs()
108 regs->i0 = gdb_regs[BFIN_I0]; in gdb_regs_to_pt_regs()
Dasm-offsets.c73 DEFINE(PT_I0, offsetof(struct pt_regs, i0)); in main()
Dtrace.c972 fp->b0, fp->l0, fp->m0, fp->i0); in show_regs()
/linux-4.4.14/drivers/gpu/drm/savage/
Dsavage_drv.h473 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ argument
475 ((n) << 16) | (i0))
/linux-4.4.14/arch/blackfin/mach-common/
Dinterrupt.S41 [--sp] = i0;
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s109 // set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host
124 // enable i0 delivery
133 // i0 handler
/linux-4.4.14/sound/pci/cs46xx/
Dcs46xx_dsp_scb_types.h1125 u32 i0; member
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
Dcom.fuc140 // setup i0 handler and route fifo and ctxswitch to it
164 // i0 handler
/linux-4.4.14/fs/jfs/
Djfs_dmap.c3388 int i, i0 = true, j, j0 = true, k, n; in dbExtendFS() local
3516 if (i0) { in dbExtendFS()
3530 i0 = false; in dbExtendFS()
/linux-4.4.14/arch/sparc/crypto/
Dcamellia_asm.S35 ld [%o0 + 0x00], %f0 ! i0, k[0]
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dgpc.fuc137 // setup i0 handler, and route all interrupts to it
Dhub.fuc83 // setup i0 handler, and route all interrupts to it
/linux-4.4.14/arch/x86/crypto/
Dchacha20-ssse3-x86_64.S121 # o0 = i0 ^ (x0 + s0)
/linux-4.4.14/arch/sparc/mm/
Dultra.S306 mov %i0, %o0