Lines Matching refs:i0
318 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument
320 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument
322 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument
336 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument
338 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument
340 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE() argument
352 …tic inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE() argument
354 … inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_OP() argument
374 …e uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_O… in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
376 …e uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_O… in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
378 …int32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
380 …int32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
382 …nt32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
384 …nt32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
396 …inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_CO3() argument
398 …ne uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_CO3_SEL() argument
401 …tic inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_LOW0() argument
403 …tic inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_LOW1() argument
405 …ic inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_HIGH0() argument
407 …ic inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_HIGH1() argument
409 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0… in REG_MDP4_OVLP_CSC_CONFIG() argument
411 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CSC() argument
414 …ic inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_O… in REG_MDP4_OVLP_CSC_MV() argument
416 …nline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_O… in REG_MDP4_OVLP_CSC_MV_VAL() argument
418 …nline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_BV() argument
420 …e uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument
422 …line uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_O… in REG_MDP4_OVLP_CSC_POST_BV() argument
424 … uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_O… in REG_MDP4_OVLP_CSC_POST_BV_VAL() argument
426 …nline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_LV() argument
428 …e uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument
430 …line uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_O… in REG_MDP4_OVLP_CSC_POST_LV() argument
432 … uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_O… in REG_MDP4_OVLP_CSC_POST_LV_VAL() argument
436 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } in REG_MDP4_LUTN() argument
438 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 +… in REG_MDP4_LUTN_LUT() argument
440 …tatic inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*… in REG_MDP4_LUTN_LUT_VAL() argument
444 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } in REG_MDP4_DMA_E_QUANT() argument
455 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA() argument
457 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)… in REG_MDP4_DMA_CONFIG() argument
486 …tic inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0)… in REG_MDP4_DMA_SRC_SIZE() argument
500 …tic inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0)… in REG_MDP4_DMA_SRC_BASE() argument
502 …c inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0)… in REG_MDP4_DMA_SRC_STRIDE() argument
504 …tic inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0)… in REG_MDP4_DMA_DST_SIZE() argument
518 … inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_SIZE() argument
532 … inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_BASE() argument
534 …c inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_POS() argument
548 …uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_BLEND_CONFIG() argument
558 … uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_BLEND_PARAM() argument
560 …ine uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0)… in REG_MDP4_DMA_BLEND_TRANS_LOW() argument
562 …ne uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0)… in REG_MDP4_DMA_BLEND_TRANS_HIGH() argument
564 …inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0)… in REG_MDP4_DMA_FETCH_CONFIG() argument
566 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } in REG_MDP4_DMA_CSC() argument
569 …nline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_D… in REG_MDP4_DMA_CSC_MV() argument
571 …e uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_D… in REG_MDP4_DMA_CSC_MV_VAL() argument
573 …e uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_D… in REG_MDP4_DMA_CSC_PRE_BV() argument
575 …nt32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_D… in REG_MDP4_DMA_CSC_PRE_BV_VAL() argument
577 … uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_D… in REG_MDP4_DMA_CSC_POST_BV() argument
579 …t32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_D… in REG_MDP4_DMA_CSC_POST_BV_VAL() argument
581 …e uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_D… in REG_MDP4_DMA_CSC_PRE_LV() argument
583 …nt32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_D… in REG_MDP4_DMA_CSC_PRE_LV_VAL() argument
585 … uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_D… in REG_MDP4_DMA_CSC_POST_LV() argument
587 …t32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_D… in REG_MDP4_DMA_CSC_POST_LV_VAL() argument
589 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE() argument
591 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_SIZE() argument
605 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_XY() argument
619 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } in REG_MDP4_PIPE_DST_SIZE() argument
633 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } in REG_MDP4_PIPE_DST_XY() argument
647 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0… in REG_MDP4_PIPE_SRCP0_BASE() argument
649 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0… in REG_MDP4_PIPE_SRCP1_BASE() argument
651 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0… in REG_MDP4_PIPE_SRCP2_BASE() argument
653 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0… in REG_MDP4_PIPE_SRCP3_BASE() argument
655 …c inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_STRIDE_A() argument
669 …c inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_STRIDE_B() argument
683 …ine uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } in REG_MDP4_PIPE_SSTILE_FRAME_SIZE() argument
697 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0… in REG_MDP4_PIPE_SRC_FORMAT() argument
758 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0… in REG_MDP4_PIPE_SRC_UNPACK() argument
784 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } in REG_MDP4_PIPE_OP_MODE() argument
809 …ic inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } in REG_MDP4_PIPE_PHASEX_STEP() argument
811 …ic inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } in REG_MDP4_PIPE_PHASEY_STEP() argument
813 …c inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } in REG_MDP4_PIPE_FETCH_CONFIG() argument
815 …ic inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } in REG_MDP4_PIPE_SOLID_COLOR() argument
817 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } in REG_MDP4_PIPE_CSC() argument
820 …inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000… in REG_MDP4_PIPE_CSC_MV() argument
822 …ne uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000… in REG_MDP4_PIPE_CSC_MV_VAL() argument
824 …ne uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_BV() argument
826 …int32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument
828 …e uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000… in REG_MDP4_PIPE_CSC_POST_BV() argument
830 …nt32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000… in REG_MDP4_PIPE_CSC_POST_BV_VAL() argument
832 …ne uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_LV() argument
834 …int32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument
836 …e uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000… in REG_MDP4_PIPE_CSC_POST_LV() argument
838 …nt32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000… in REG_MDP4_PIPE_CSC_POST_LV_VAL() argument
937 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } in REG_MDP4_LCDC_LVDS_MUX_CTL() argument
939 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0() argument
965 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4() argument