Lines Matching refs:i0
207 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); } in REG_MDP5_MDP() argument
209 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0);… in REG_MDP5_MDP_HW_VERSION() argument
229 …tic inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0)… in REG_MDP5_MDP_DISP_INTF_SEL() argument
255 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); } in REG_MDP5_MDP_INTR_EN() argument
257 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0)… in REG_MDP5_MDP_INTR_STATUS() argument
259 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0);… in REG_MDP5_MDP_INTR_CLEAR() argument
261 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0… in REG_MDP5_MDP_HIST_INTR_EN() argument
263 … inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0)… in REG_MDP5_MDP_HIST_INTR_STATUS() argument
265 …c inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0)… in REG_MDP5_MDP_HIST_INTR_CLEAR() argument
267 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); } in REG_MDP5_MDP_SPARE_0() argument
270 …nline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_W() argument
272 …e uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_W_REG() argument
292 …nline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_R() argument
294 …e uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_R_REG() argument
324 …c inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __off… in REG_MDP5_MDP_IGC() argument
326 …int32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 … in REG_MDP5_MDP_IGC_LUT() argument
328 …2_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 … in REG_MDP5_MDP_IGC_LUT_REG() argument
340 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0… in REG_MDP5_MDP_SPLIT_DPL_EN() argument
342 …c inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0)… in REG_MDP5_MDP_SPLIT_DPL_UPPER() argument
348 …c inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0)… in REG_MDP5_MDP_SPLIT_DPL_LOWER() argument
365 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL() argument
379 …atic inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER() argument
381 … inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_REG() argument
445 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } in REG_MDP5_CTL_OP() argument
467 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } in REG_MDP5_CTL_FLUSH() argument
498 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } in REG_MDP5_CTL_START() argument
500 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } in REG_MDP5_CTL_PACK_3D() argument
514 … inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_EXT() argument
516 …ine uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_EXT_REG() argument
556 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } in REG_MDP5_PIPE() argument
558 …c inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0)… in REG_MDP5_PIPE_OP_MODE() argument
573 …ne uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_CTL_BASE() argument
575 …ne uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_LUT_BASE() argument
577 …ne uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_LUT_SWAP() argument
579 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0() argument
593 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1() argument
607 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2() argument
621 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3() argument
635 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4() argument
643 …2_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
645 …REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
659 …_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
661 …EG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
675 …32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
677 … REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
685 …2_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
687 …REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
695 … inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_SIZE() argument
709 …ine uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_IMG_SIZE() argument
723 …ic inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_XY() argument
737 … inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0)… in REG_MDP5_PIPE_OUT_SIZE() argument
751 …ic inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0)… in REG_MDP5_PIPE_OUT_XY() argument
765 …inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC0_ADDR() argument
767 …inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC1_ADDR() argument
769 …inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC2_ADDR() argument
771 …inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC3_ADDR() argument
773 …ine uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_STRIDE_A() argument
787 …ine uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_STRIDE_B() argument
801 …uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0)… in REG_MDP5_PIPE_STILE_FRAME_SIZE() argument
803 …nline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_FORMAT() argument
857 …nline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_UNPACK() argument
883 …line uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_OP_MODE() argument
900 …nt32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_CONSTANT_COLOR() argument
902 …ine uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0)… in REG_MDP5_PIPE_FETCH_CONFIG() argument
904 …inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0)… in REG_MDP5_PIPE_VC1_RANGE() argument
906 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0() argument
908 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1() argument
910 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2() argument
912 …nt32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS() argument
914 …int32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC0_ADDR() argument
916 …int32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC1_ADDR() argument
918 …int32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC2_ADDR() argument
920 …int32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC3_ADDR() argument
922 …nline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_DECIMATION() argument
945 … REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __o… in REG_MDP5_PIPE_SW_PIX_EXT() argument
947 …G_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __o… in REG_MDP5_PIPE_SW_PIX_EXT_LR() argument
973 …G_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __o… in REG_MDP5_PIPE_SW_PIX_EXT_TB() argument
999 …IPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __o… in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument
1013 …ine uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CONFIG() argument
1053 …nt32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_PHASE_STEP_X() argument
1055 …nt32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y() argument
1057 …2_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X() argument
1059 …2_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y() argument
1061 …nt32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_INIT_PHASE_X() argument
1063 …nt32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y() argument
1077 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } in REG_MDP5_LM() argument
1079 …ic inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0);… in REG_MDP5_LM_BLEND_COLOR_OUT() argument
1085 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } in REG_MDP5_LM_OUT_SIZE() argument
1099 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_0() argument
1101 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_1() argument
1116 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_L… in REG_MDP5_LM_BLEND() argument
1118 …nline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_… in REG_MDP5_LM_BLEND_OP_MODE() argument
1140 …line uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_… in REG_MDP5_LM_BLEND_FG_ALPHA() argument
1142 …line uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_… in REG_MDP5_LM_BLEND_BG_ALPHA() argument
1144 …int32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
1146 …int32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
1148 …nt32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
1150 …nt32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1152 …int32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1154 …int32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1156 …nt32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1158 …nt32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1160 …ic inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_IMG_SIZE() argument
1174 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_SIZE() argument
1188 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_XY() argument
1202 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_STRIDE() argument
1210 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_FORMAT() argument
1218 …c inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BASE_ADDR() argument
1220 …ic inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_START_XY() argument
1234 …nline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_CONFIG() argument
1244 …inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_PARAM() argument
1246 … uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0() argument
1248 … uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1() argument
1250 …uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0() argument
1252 …uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1() argument
1254 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } in REG_MDP5_LM_GC_LUT_BASE() argument
1266 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP() argument
1268 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP_OP_MODE() argument
1285 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);… in REG_MDP5_DSPP_PCC_BASE() argument
1287 …ic inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0)… in REG_MDP5_DSPP_DITHER_DEPTH() argument
1289 …c inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_CTL_BASE() argument
1291 …c inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_LUT_BASE() argument
1293 …c inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_LUT_SWAP() argument
1295 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } in REG_MDP5_DSPP_PA_BASE() argument
1297 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0… in REG_MDP5_DSPP_GAMUT_BASE() argument
1299 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } in REG_MDP5_DSPP_GC_BASE() argument
1311 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } in REG_MDP5_PP() argument
1313 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)… in REG_MDP5_PP_TEAR_CHECK_EN() argument
1315 … inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0);… in REG_MDP5_PP_SYNC_CONFIG_VSYNC() argument
1325 …inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0);… in REG_MDP5_PP_SYNC_CONFIG_HEIGHT() argument
1327 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);… in REG_MDP5_PP_SYNC_WRCOUNT() argument
1341 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0… in REG_MDP5_PP_VSYNC_INIT_VAL() argument
1343 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)… in REG_MDP5_PP_INT_COUNT_VAL() argument
1357 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); } in REG_MDP5_PP_SYNC_THRESH() argument
1371 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); } in REG_MDP5_PP_START_POS() argument
1373 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); } in REG_MDP5_PP_RD_PTR_IRQ() argument
1375 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); } in REG_MDP5_PP_WR_PTR_IRQ() argument
1377 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0… in REG_MDP5_PP_OUT_LINE_COUNT() argument
1379 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)… in REG_MDP5_PP_PP_LINE_COUNT() argument
1381 …inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0);… in REG_MDP5_PP_AUTOREFRESH_CONFIG() argument
1383 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); } in REG_MDP5_PP_FBC_MODE() argument
1385 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0… in REG_MDP5_PP_FBC_BUDGET_CTL() argument
1387 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0… in REG_MDP5_PP_FBC_LOSSY_MODE() argument
1402 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } in REG_MDP5_WB() argument
1404 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } in REG_MDP5_WB_DST_FORMAT() argument
1471 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } in REG_MDP5_WB_DST_OP_MODE() argument
1525 …c inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0);… in REG_MDP5_WB_DST_PACK_PATTERN() argument
1551 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } in REG_MDP5_WB_DST0_ADDR() argument
1553 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } in REG_MDP5_WB_DST1_ADDR() argument
1555 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } in REG_MDP5_WB_DST2_ADDR() argument
1557 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } in REG_MDP5_WB_DST3_ADDR() argument
1559 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0);… in REG_MDP5_WB_DST_YSTRIDE0() argument
1573 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0);… in REG_MDP5_WB_DST_YSTRIDE1() argument
1587 …nline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0);… in REG_MDP5_WB_DST_DITHER_BITDEPTH() argument
1589 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW0() argument
1591 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW1() argument
1593 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW2() argument
1595 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW3() argument
1597 …c inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0);… in REG_MDP5_WB_DST_WRITE_CONFIG() argument
1599 … inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0);… in REG_MDP5_WB_ROTATION_DNSCALER() argument
1601 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_X_0_3() argument
1603 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_X_1_2() argument
1605 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_Y_0_3() argument
1607 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_Y_1_2() argument
1609 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); } in REG_MDP5_WB_OUT_SIZE() argument
1623 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0)… in REG_MDP5_WB_ALPHA_X_VALUE() argument
1625 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_0() argument
1639 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_1() argument
1653 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_2() argument
1667 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_3() argument
1681 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_4() argument
1689 …e uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_… in REG_MDP5_WB_CSC_COMP_PRECLAMP() argument
1691 …nt32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_… in REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument
1705 … uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument
1707 …t32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument
1721 …ne uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_… in REG_MDP5_WB_CSC_COMP_PREBIAS() argument
1723 …int32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_… in REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument
1731 …e uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTBIAS() argument
1733 …nt32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument
1752 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF() argument
1754 …nline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0)… in REG_MDP5_INTF_TIMING_ENGINE_EN() argument
1756 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } in REG_MDP5_INTF_CONFIG() argument
1758 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)… in REG_MDP5_INTF_HSYNC_CTL() argument
1772 …inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_PERIOD_F0() argument
1774 …inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_PERIOD_F1() argument
1776 …ic inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_LEN_F0() argument
1778 …ic inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_LEN_F1() argument
1780 …line uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VSTART_F0() argument
1782 …line uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VSTART_F1() argument
1784 …inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VEND_F0() argument
1786 …inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VEND_F1() argument
1788 …nline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VSTART_F0() argument
1797 …nline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VSTART_F1() argument
1805 … inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VEND_F0() argument
1807 … inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VEND_F1() argument
1809 …ic inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_HCTL() argument
1823 …tic inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_HCTL() argument
1838 …ic inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0)… in REG_MDP5_INTF_BORDER_COLOR() argument
1840 …inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0)… in REG_MDP5_INTF_UNDERFLOW_COLOR() argument
1842 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0… in REG_MDP5_INTF_HSYNC_SKEW() argument
1844 …ic inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0)… in REG_MDP5_INTF_POLARITY_CTL() argument
1849 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);… in REG_MDP5_INTF_TEST_CTL() argument
1851 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR0() argument
1853 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR1() argument
1855 …int32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0)… in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN() argument
1857 …ic inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0)… in REG_MDP5_INTF_PANEL_FORMAT() argument
1859 …ne uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0)… in REG_MDP5_INTF_FRAME_LINE_COUNT_EN() argument
1861 …tic inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0)… in REG_MDP5_INTF_FRAME_COUNT() argument
1863 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0… in REG_MDP5_INTF_LINE_COUNT() argument
1865 …nline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_CONFIG() argument
1867 … uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF() argument
1869 …e uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF() argument
1871 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0… in REG_MDP5_INTF_TPG_ENABLE() argument
1873 …nline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_MAIN_CONTROL() argument
1875 …nline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_VIDEO_CONFIG() argument
1877 …e uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_COMPONENT_LIMITS() argument
1879 …c inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_RECTANGLE() argument
1881 …line uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_INITIAL_VALUE() argument
1883 …2_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME() argument
1885 …inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_RGB_MAPPING() argument
1895 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD() argument
1897 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD_BYPASS() argument
1899 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_0() argument
1901 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_1() argument
1903 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } in REG_MDP5_AD_FRAME_SIZE() argument
1905 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_0() argument
1907 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_1() argument
1909 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } in REG_MDP5_AD_STR_MAN() argument
1911 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } in REG_MDP5_AD_VAR() argument
1913 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } in REG_MDP5_AD_DITH() argument
1915 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } in REG_MDP5_AD_DITH_CTRL() argument
1917 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } in REG_MDP5_AD_AMP_LIM() argument
1919 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } in REG_MDP5_AD_SLOPE() argument
1921 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } in REG_MDP5_AD_BW_LVL() argument
1923 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } in REG_MDP5_AD_LOGO_POS() argument
1925 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } in REG_MDP5_AD_LUT_FI() argument
1927 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } in REG_MDP5_AD_LUT_CC() argument
1929 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } in REG_MDP5_AD_STR_LIM() argument
1931 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } in REG_MDP5_AD_CALIB_AB() argument
1933 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } in REG_MDP5_AD_CALIB_CD() argument
1935 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } in REG_MDP5_AD_MODE_SEL() argument
1937 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } in REG_MDP5_AD_TFILT_CTRL() argument
1939 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } in REG_MDP5_AD_BL_MINMAX() argument
1941 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } in REG_MDP5_AD_BL() argument
1943 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } in REG_MDP5_AD_BL_MAX() argument
1945 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } in REG_MDP5_AD_AL() argument
1947 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } in REG_MDP5_AD_AL_MIN() argument
1949 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } in REG_MDP5_AD_AL_FILT() argument
1951 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } in REG_MDP5_AD_CFG_BUF() argument
1953 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } in REG_MDP5_AD_LUT_AL() argument
1955 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } in REG_MDP5_AD_TARG_STR() argument
1957 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } in REG_MDP5_AD_START_CALC() argument
1959 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } in REG_MDP5_AD_STR_OUT() argument
1961 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } in REG_MDP5_AD_BL_OUT() argument
1963 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } in REG_MDP5_AD_CALC_DONE() argument