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Searched refs:csio_rd_reg32 (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/scsi/csiostor/
Dcsio_hw_t5.c62 csio_rd_reg32(hw, in csio_t5_set_mem_win()
186 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F) in csio_t5_mc_read()
201 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); in csio_t5_mc_read()
242 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F) in csio_t5_edc_read()
257 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); in csio_t5_edc_read()
301 edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A)); in csio_t5_memory_rw()
305 mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw, in csio_t5_memory_rw()
322 mem_reg = csio_rd_reg32(hw, in csio_t5_memory_rw()
348 csio_rd_reg32(hw, in csio_t5_memory_rw()
353 *buf++ = csio_rd_reg32(hw, mem_base + offset); in csio_t5_memory_rw()
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Dcsio_hw.c138 val = csio_rd_reg32(hw, reg); in csio_hw_wait_op_done_val()
167 val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask; in csio_hw_tp_wr_bits_indirect()
175 uint32_t val = csio_rd_reg32(hw, reg) & ~mask; in csio_set_reg_field()
179 csio_rd_reg32(hw, reg); in csio_set_reg_field()
399 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) in csio_hw_sf1_read()
407 *valp = csio_rd_reg32(hw, SF_DATA_A); in csio_hw_sf1_read()
429 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) in csio_hw_sf1_write()
798 while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) && in csio_hw_dev_ready()
896 pcie_fw = csio_rd_reg32(hw, PCIE_FW_A); in csio_do_hello()
1195 if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F)) in csio_hw_fw_restart()
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Dcsio_mb.c1109 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); in csio_mb_intr_enable()
1123 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); in csio_mb_intr_disable()
1172 csio_rd_reg32(hw, ctl_reg); in csio_mb_debug_cmd_handler()
1229 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1234 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1283 csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1298 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1468 pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A)); in csio_mb_isr_handler()
1469 cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A)); in csio_mb_isr_handler()
1485 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_isr_handler()
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Dcsio_wr.c59 sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A + in csio_get_flbuf_size()
1337 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2_A) + in csio_wr_fixup_host_params()
1341 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3_A) + in csio_wr_fixup_host_params()
1389 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A); in csio_wr_get_sge()
1415 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A); in csio_wr_get_sge()
1416 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A); in csio_wr_get_sge()
1417 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A); in csio_wr_get_sge()
1432 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A); in csio_wr_get_sge()
1461 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A); in csio_wr_set_sge()
Dcsio_hw.h505 #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r))) macro
Dcsio_init.c128 i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A); in csio_setup_debugfs()