Searched refs:apic_base (Results 1 – 9 of 9) sorted by relevance
118 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; in kvm_apic_hw_enabled()143 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; in apic_x2apic_mode()
1547 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) in kvm_free_lapic()1614 u64 old_value = vcpu->arch.apic_base; in kvm_lapic_set_base()1619 vcpu->arch.apic_base = value; in kvm_lapic_set_base()1623 vcpu->arch.apic_base = value; in kvm_lapic_set_base()1642 apic->base_address = apic->vcpu->arch.apic_base & in kvm_lapic_set_base()1651 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); in kvm_lapic_set_base()1703 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); in kvm_lapic_reset()1713 vcpu->arch.apic_base, apic->base_address); in kvm_lapic_reset()1809 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; in kvm_create_lapic()1894 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); in kvm_apic_post_state_restore()
281 return vcpu->arch.apic_base; in kvm_get_apic_base()287 u64 old_state = vcpu->arch.apic_base & in kvm_set_apic_base()5958 kvm_run->apic_base = kvm_get_apic_base(vcpu); in post_kvm_run_save()6947 sregs->apic_base = kvm_get_apic_base(vcpu); in kvm_arch_vcpu_ioctl_get_sregs()7035 apic_base_msr.data = sregs->apic_base; in kvm_arch_vcpu_ioctl_set_sregs()7517 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; in kvm_vcpu_is_bsp()
1123 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | in svm_vcpu_reset()1126 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; in svm_vcpu_reset()
2335 else if (vcpu->arch.apic_base & X2APIC_ENABLE) { in vmx_set_msr_bitmap()9348 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) in nested_vmx_msr_check_common()
152 __u64 apic_base; member
210 __u64 apic_base; member
401 u64 apic_base; member
351 __u64 apic_base;3080 __u64 apic_base;