1/* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22#include <linux/kvm_host.h> 23#include "irq.h" 24#include "mmu.h" 25#include "i8254.h" 26#include "tss.h" 27#include "kvm_cache_regs.h" 28#include "x86.h" 29#include "cpuid.h" 30#include "assigned-dev.h" 31#include "pmu.h" 32#include "hyperv.h" 33 34#include <linux/clocksource.h> 35#include <linux/interrupt.h> 36#include <linux/kvm.h> 37#include <linux/fs.h> 38#include <linux/vmalloc.h> 39#include <linux/module.h> 40#include <linux/mman.h> 41#include <linux/highmem.h> 42#include <linux/iommu.h> 43#include <linux/intel-iommu.h> 44#include <linux/cpufreq.h> 45#include <linux/user-return-notifier.h> 46#include <linux/srcu.h> 47#include <linux/slab.h> 48#include <linux/perf_event.h> 49#include <linux/uaccess.h> 50#include <linux/hash.h> 51#include <linux/pci.h> 52#include <linux/timekeeper_internal.h> 53#include <linux/pvclock_gtod.h> 54#include <linux/kvm_irqfd.h> 55#include <linux/irqbypass.h> 56#include <trace/events/kvm.h> 57 58#define CREATE_TRACE_POINTS 59#include "trace.h" 60 61#include <asm/debugreg.h> 62#include <asm/msr.h> 63#include <asm/desc.h> 64#include <asm/mce.h> 65#include <linux/kernel_stat.h> 66#include <asm/fpu/internal.h> /* Ugh! */ 67#include <asm/pvclock.h> 68#include <asm/div64.h> 69#include <asm/irq_remapping.h> 70 71#define MAX_IO_MSRS 256 72#define KVM_MAX_MCE_BANKS 32 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 74 75#define emul_to_vcpu(ctxt) \ 76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 77 78/* EFER defaults: 79 * - enable syscall per default because its emulated by KVM 80 * - enable LME and LMA per default on 64 bit KVM 81 */ 82#ifdef CONFIG_X86_64 83static 84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 85#else 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 87#endif 88 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 91 92static void update_cr8_intercept(struct kvm_vcpu *vcpu); 93static void process_nmi(struct kvm_vcpu *vcpu); 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 95 96struct kvm_x86_ops *kvm_x86_ops __read_mostly; 97EXPORT_SYMBOL_GPL(kvm_x86_ops); 98 99static bool __read_mostly ignore_msrs = 0; 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 101 102unsigned int min_timer_period_us = 500; 103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 104 105static bool __read_mostly kvmclock_periodic_sync = true; 106module_param(kvmclock_periodic_sync, bool, S_IRUGO); 107 108bool __read_mostly kvm_has_tsc_control; 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 110u32 __read_mostly kvm_max_guest_tsc_khz; 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 114u64 __read_mostly kvm_max_tsc_scaling_ratio; 115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 116static u64 __read_mostly kvm_default_tsc_scaling_ratio; 117 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 119static u32 __read_mostly tsc_tolerance_ppm = 250; 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 121 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */ 123unsigned int __read_mostly lapic_timer_advance_ns = 0; 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 125 126static bool __read_mostly backwards_tsc_observed = false; 127 128#define KVM_NR_SHARED_MSRS 16 129 130struct kvm_shared_msrs_global { 131 int nr; 132 u32 msrs[KVM_NR_SHARED_MSRS]; 133}; 134 135struct kvm_shared_msrs { 136 struct user_return_notifier urn; 137 bool registered; 138 struct kvm_shared_msr_values { 139 u64 host; 140 u64 curr; 141 } values[KVM_NR_SHARED_MSRS]; 142}; 143 144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 145static struct kvm_shared_msrs __percpu *shared_msrs; 146 147struct kvm_stats_debugfs_item debugfs_entries[] = { 148 { "pf_fixed", VCPU_STAT(pf_fixed) }, 149 { "pf_guest", VCPU_STAT(pf_guest) }, 150 { "tlb_flush", VCPU_STAT(tlb_flush) }, 151 { "invlpg", VCPU_STAT(invlpg) }, 152 { "exits", VCPU_STAT(exits) }, 153 { "io_exits", VCPU_STAT(io_exits) }, 154 { "mmio_exits", VCPU_STAT(mmio_exits) }, 155 { "signal_exits", VCPU_STAT(signal_exits) }, 156 { "irq_window", VCPU_STAT(irq_window_exits) }, 157 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 158 { "halt_exits", VCPU_STAT(halt_exits) }, 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 162 { "hypercalls", VCPU_STAT(hypercalls) }, 163 { "request_irq", VCPU_STAT(request_irq_exits) }, 164 { "irq_exits", VCPU_STAT(irq_exits) }, 165 { "host_state_reload", VCPU_STAT(host_state_reload) }, 166 { "efer_reload", VCPU_STAT(efer_reload) }, 167 { "fpu_reload", VCPU_STAT(fpu_reload) }, 168 { "insn_emulation", VCPU_STAT(insn_emulation) }, 169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 170 { "irq_injections", VCPU_STAT(irq_injections) }, 171 { "nmi_injections", VCPU_STAT(nmi_injections) }, 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 173 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 176 { "mmu_flooded", VM_STAT(mmu_flooded) }, 177 { "mmu_recycled", VM_STAT(mmu_recycled) }, 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 179 { "mmu_unsync", VM_STAT(mmu_unsync) }, 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 181 { "largepages", VM_STAT(lpages) }, 182 { NULL } 183}; 184 185u64 __read_mostly host_xcr0; 186 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 188 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 190{ 191 int i; 192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 193 vcpu->arch.apf.gfns[i] = ~0; 194} 195 196static void kvm_on_user_return(struct user_return_notifier *urn) 197{ 198 unsigned slot; 199 struct kvm_shared_msrs *locals 200 = container_of(urn, struct kvm_shared_msrs, urn); 201 struct kvm_shared_msr_values *values; 202 203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 204 values = &locals->values[slot]; 205 if (values->host != values->curr) { 206 wrmsrl(shared_msrs_global.msrs[slot], values->host); 207 values->curr = values->host; 208 } 209 } 210 locals->registered = false; 211 user_return_notifier_unregister(urn); 212} 213 214static void shared_msr_update(unsigned slot, u32 msr) 215{ 216 u64 value; 217 unsigned int cpu = smp_processor_id(); 218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 219 220 /* only read, and nobody should modify it at this time, 221 * so don't need lock */ 222 if (slot >= shared_msrs_global.nr) { 223 printk(KERN_ERR "kvm: invalid MSR slot!"); 224 return; 225 } 226 rdmsrl_safe(msr, &value); 227 smsr->values[slot].host = value; 228 smsr->values[slot].curr = value; 229} 230 231void kvm_define_shared_msr(unsigned slot, u32 msr) 232{ 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 234 shared_msrs_global.msrs[slot] = msr; 235 if (slot >= shared_msrs_global.nr) 236 shared_msrs_global.nr = slot + 1; 237} 238EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 239 240static void kvm_shared_msr_cpu_online(void) 241{ 242 unsigned i; 243 244 for (i = 0; i < shared_msrs_global.nr; ++i) 245 shared_msr_update(i, shared_msrs_global.msrs[i]); 246} 247 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 249{ 250 unsigned int cpu = smp_processor_id(); 251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 252 int err; 253 254 if (((value ^ smsr->values[slot].curr) & mask) == 0) 255 return 0; 256 smsr->values[slot].curr = value; 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 258 if (err) 259 return 1; 260 261 if (!smsr->registered) { 262 smsr->urn.on_user_return = kvm_on_user_return; 263 user_return_notifier_register(&smsr->urn); 264 smsr->registered = true; 265 } 266 return 0; 267} 268EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 269 270static void drop_user_return_notifiers(void) 271{ 272 unsigned int cpu = smp_processor_id(); 273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 274 275 if (smsr->registered) 276 kvm_on_user_return(&smsr->urn); 277} 278 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 280{ 281 return vcpu->arch.apic_base; 282} 283EXPORT_SYMBOL_GPL(kvm_get_apic_base); 284 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 286{ 287 u64 old_state = vcpu->arch.apic_base & 288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 289 u64 new_state = msr_info->data & 290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 293 294 if (!msr_info->host_initiated && 295 ((msr_info->data & reserved_bits) != 0 || 296 new_state == X2APIC_ENABLE || 297 (new_state == MSR_IA32_APICBASE_ENABLE && 298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 300 old_state == 0))) 301 return 1; 302 303 kvm_lapic_set_base(vcpu, msr_info->data); 304 return 0; 305} 306EXPORT_SYMBOL_GPL(kvm_set_apic_base); 307 308asmlinkage __visible void kvm_spurious_fault(void) 309{ 310 /* Fault while not rebooting. We want the trace. */ 311 BUG(); 312} 313EXPORT_SYMBOL_GPL(kvm_spurious_fault); 314 315#define EXCPT_BENIGN 0 316#define EXCPT_CONTRIBUTORY 1 317#define EXCPT_PF 2 318 319static int exception_class(int vector) 320{ 321 switch (vector) { 322 case PF_VECTOR: 323 return EXCPT_PF; 324 case DE_VECTOR: 325 case TS_VECTOR: 326 case NP_VECTOR: 327 case SS_VECTOR: 328 case GP_VECTOR: 329 return EXCPT_CONTRIBUTORY; 330 default: 331 break; 332 } 333 return EXCPT_BENIGN; 334} 335 336#define EXCPT_FAULT 0 337#define EXCPT_TRAP 1 338#define EXCPT_ABORT 2 339#define EXCPT_INTERRUPT 3 340 341static int exception_type(int vector) 342{ 343 unsigned int mask; 344 345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 346 return EXCPT_INTERRUPT; 347 348 mask = 1 << vector; 349 350 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 352 return EXCPT_TRAP; 353 354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 355 return EXCPT_ABORT; 356 357 /* Reserved exceptions will result in fault */ 358 return EXCPT_FAULT; 359} 360 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 362 unsigned nr, bool has_error, u32 error_code, 363 bool reinject) 364{ 365 u32 prev_nr; 366 int class1, class2; 367 368 kvm_make_request(KVM_REQ_EVENT, vcpu); 369 370 if (!vcpu->arch.exception.pending) { 371 queue: 372 if (has_error && !is_protmode(vcpu)) 373 has_error = false; 374 vcpu->arch.exception.pending = true; 375 vcpu->arch.exception.has_error_code = has_error; 376 vcpu->arch.exception.nr = nr; 377 vcpu->arch.exception.error_code = error_code; 378 vcpu->arch.exception.reinject = reinject; 379 return; 380 } 381 382 /* to check exception */ 383 prev_nr = vcpu->arch.exception.nr; 384 if (prev_nr == DF_VECTOR) { 385 /* triple fault -> shutdown */ 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 387 return; 388 } 389 class1 = exception_class(prev_nr); 390 class2 = exception_class(nr); 391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 393 /* generate double fault per SDM Table 5-5 */ 394 vcpu->arch.exception.pending = true; 395 vcpu->arch.exception.has_error_code = true; 396 vcpu->arch.exception.nr = DF_VECTOR; 397 vcpu->arch.exception.error_code = 0; 398 } else 399 /* replace previous exception with a new one in a hope 400 that instruction re-execution will regenerate lost 401 exception */ 402 goto queue; 403} 404 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 406{ 407 kvm_multiple_exception(vcpu, nr, false, 0, false); 408} 409EXPORT_SYMBOL_GPL(kvm_queue_exception); 410 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 412{ 413 kvm_multiple_exception(vcpu, nr, false, 0, true); 414} 415EXPORT_SYMBOL_GPL(kvm_requeue_exception); 416 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 418{ 419 if (err) 420 kvm_inject_gp(vcpu, 0); 421 else 422 kvm_x86_ops->skip_emulated_instruction(vcpu); 423} 424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 425 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 427{ 428 ++vcpu->stat.pf_guest; 429 vcpu->arch.cr2 = fault->address; 430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 431} 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 433 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 435{ 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 438 else 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 440 441 return fault->nested_page_fault; 442} 443 444void kvm_inject_nmi(struct kvm_vcpu *vcpu) 445{ 446 atomic_inc(&vcpu->arch.nmi_queued); 447 kvm_make_request(KVM_REQ_NMI, vcpu); 448} 449EXPORT_SYMBOL_GPL(kvm_inject_nmi); 450 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 452{ 453 kvm_multiple_exception(vcpu, nr, true, error_code, false); 454} 455EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 456 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 458{ 459 kvm_multiple_exception(vcpu, nr, true, error_code, true); 460} 461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 462 463/* 464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 465 * a #GP and return false. 466 */ 467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 468{ 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 470 return true; 471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 472 return false; 473} 474EXPORT_SYMBOL_GPL(kvm_require_cpl); 475 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 477{ 478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 479 return true; 480 481 kvm_queue_exception(vcpu, UD_VECTOR); 482 return false; 483} 484EXPORT_SYMBOL_GPL(kvm_require_dr); 485 486/* 487 * This function will be used to read from the physical memory of the currently 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 489 * can read from guest physical or from the guest's guest physical memory. 490 */ 491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 492 gfn_t ngfn, void *data, int offset, int len, 493 u32 access) 494{ 495 struct x86_exception exception; 496 gfn_t real_gfn; 497 gpa_t ngpa; 498 499 ngpa = gfn_to_gpa(ngfn); 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 501 if (real_gfn == UNMAPPED_GVA) 502 return -EFAULT; 503 504 real_gfn = gpa_to_gfn(real_gfn); 505 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 507} 508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 509 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 511 void *data, int offset, int len, u32 access) 512{ 513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 514 data, offset, len, access); 515} 516 517/* 518 * Load the pae pdptrs. Return true is they are all valid. 519 */ 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 521{ 522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 524 int i; 525 int ret; 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 527 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 529 offset * sizeof(u64), sizeof(pdpte), 530 PFERR_USER_MASK|PFERR_WRITE_MASK); 531 if (ret < 0) { 532 ret = 0; 533 goto out; 534 } 535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 536 if (is_present_gpte(pdpte[i]) && 537 (pdpte[i] & 538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 539 ret = 0; 540 goto out; 541 } 542 } 543 ret = 1; 544 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 546 __set_bit(VCPU_EXREG_PDPTR, 547 (unsigned long *)&vcpu->arch.regs_avail); 548 __set_bit(VCPU_EXREG_PDPTR, 549 (unsigned long *)&vcpu->arch.regs_dirty); 550out: 551 552 return ret; 553} 554EXPORT_SYMBOL_GPL(load_pdptrs); 555 556static bool pdptrs_changed(struct kvm_vcpu *vcpu) 557{ 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 559 bool changed = true; 560 int offset; 561 gfn_t gfn; 562 int r; 563 564 if (is_long_mode(vcpu) || !is_pae(vcpu)) 565 return false; 566 567 if (!test_bit(VCPU_EXREG_PDPTR, 568 (unsigned long *)&vcpu->arch.regs_avail)) 569 return true; 570 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 574 PFERR_USER_MASK | PFERR_WRITE_MASK); 575 if (r < 0) 576 goto out; 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 578out: 579 580 return changed; 581} 582 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 584{ 585 unsigned long old_cr0 = kvm_read_cr0(vcpu); 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 587 588 cr0 |= X86_CR0_ET; 589 590#ifdef CONFIG_X86_64 591 if (cr0 & 0xffffffff00000000UL) 592 return 1; 593#endif 594 595 cr0 &= ~CR0_RESERVED_BITS; 596 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 598 return 1; 599 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 601 return 1; 602 603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 604#ifdef CONFIG_X86_64 605 if ((vcpu->arch.efer & EFER_LME)) { 606 int cs_db, cs_l; 607 608 if (!is_pae(vcpu)) 609 return 1; 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 611 if (cs_l) 612 return 1; 613 } else 614#endif 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 616 kvm_read_cr3(vcpu))) 617 return 1; 618 } 619 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 621 return 1; 622 623 kvm_x86_ops->set_cr0(vcpu, cr0); 624 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 626 kvm_clear_async_pf_completion_queue(vcpu); 627 kvm_async_pf_hash_reset(vcpu); 628 } 629 630 if ((cr0 ^ old_cr0) & update_bits) 631 kvm_mmu_reset_context(vcpu); 632 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 634 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 637 638 return 0; 639} 640EXPORT_SYMBOL_GPL(kvm_set_cr0); 641 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 643{ 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 645} 646EXPORT_SYMBOL_GPL(kvm_lmsw); 647 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 649{ 650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 651 !vcpu->guest_xcr0_loaded) { 652 /* kvm_set_xcr() also depends on this */ 653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 654 vcpu->guest_xcr0_loaded = 1; 655 } 656} 657 658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 659{ 660 if (vcpu->guest_xcr0_loaded) { 661 if (vcpu->arch.xcr0 != host_xcr0) 662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 663 vcpu->guest_xcr0_loaded = 0; 664 } 665} 666 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 668{ 669 u64 xcr0 = xcr; 670 u64 old_xcr0 = vcpu->arch.xcr0; 671 u64 valid_bits; 672 673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 674 if (index != XCR_XFEATURE_ENABLED_MASK) 675 return 1; 676 if (!(xcr0 & XFEATURE_MASK_FP)) 677 return 1; 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 679 return 1; 680 681 /* 682 * Do not allow the guest to set bits that we do not support 683 * saving. However, xcr0 bit 0 is always set, even if the 684 * emulated CPU does not support XSAVE (see fx_init). 685 */ 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 687 if (xcr0 & ~valid_bits) 688 return 1; 689 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 691 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 692 return 1; 693 694 if (xcr0 & XFEATURE_MASK_AVX512) { 695 if (!(xcr0 & XFEATURE_MASK_YMM)) 696 return 1; 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 698 return 1; 699 } 700 vcpu->arch.xcr0 = xcr0; 701 702 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 703 kvm_update_cpuid(vcpu); 704 return 0; 705} 706 707int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 708{ 709 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 710 __kvm_set_xcr(vcpu, index, xcr)) { 711 kvm_inject_gp(vcpu, 0); 712 return 1; 713 } 714 return 0; 715} 716EXPORT_SYMBOL_GPL(kvm_set_xcr); 717 718int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 719{ 720 unsigned long old_cr4 = kvm_read_cr4(vcpu); 721 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 722 X86_CR4_SMEP | X86_CR4_SMAP; 723 724 if (cr4 & CR4_RESERVED_BITS) 725 return 1; 726 727 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 728 return 1; 729 730 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 731 return 1; 732 733 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 734 return 1; 735 736 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 737 return 1; 738 739 if (is_long_mode(vcpu)) { 740 if (!(cr4 & X86_CR4_PAE)) 741 return 1; 742 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 743 && ((cr4 ^ old_cr4) & pdptr_bits) 744 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 745 kvm_read_cr3(vcpu))) 746 return 1; 747 748 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 749 if (!guest_cpuid_has_pcid(vcpu)) 750 return 1; 751 752 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 753 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 754 return 1; 755 } 756 757 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 758 return 1; 759 760 if (((cr4 ^ old_cr4) & pdptr_bits) || 761 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 762 kvm_mmu_reset_context(vcpu); 763 764 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 765 kvm_update_cpuid(vcpu); 766 767 return 0; 768} 769EXPORT_SYMBOL_GPL(kvm_set_cr4); 770 771int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 772{ 773#ifdef CONFIG_X86_64 774 cr3 &= ~CR3_PCID_INVD; 775#endif 776 777 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 778 kvm_mmu_sync_roots(vcpu); 779 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 780 return 0; 781 } 782 783 if (is_long_mode(vcpu)) { 784 if (cr3 & CR3_L_MODE_RESERVED_BITS) 785 return 1; 786 } else if (is_pae(vcpu) && is_paging(vcpu) && 787 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 788 return 1; 789 790 vcpu->arch.cr3 = cr3; 791 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 792 kvm_mmu_new_cr3(vcpu); 793 return 0; 794} 795EXPORT_SYMBOL_GPL(kvm_set_cr3); 796 797int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 798{ 799 if (cr8 & CR8_RESERVED_BITS) 800 return 1; 801 if (lapic_in_kernel(vcpu)) 802 kvm_lapic_set_tpr(vcpu, cr8); 803 else 804 vcpu->arch.cr8 = cr8; 805 return 0; 806} 807EXPORT_SYMBOL_GPL(kvm_set_cr8); 808 809unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 810{ 811 if (lapic_in_kernel(vcpu)) 812 return kvm_lapic_get_cr8(vcpu); 813 else 814 return vcpu->arch.cr8; 815} 816EXPORT_SYMBOL_GPL(kvm_get_cr8); 817 818static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 819{ 820 int i; 821 822 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 823 for (i = 0; i < KVM_NR_DB_REGS; i++) 824 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 825 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 826 } 827} 828 829static void kvm_update_dr6(struct kvm_vcpu *vcpu) 830{ 831 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 832 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 833} 834 835static void kvm_update_dr7(struct kvm_vcpu *vcpu) 836{ 837 unsigned long dr7; 838 839 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 840 dr7 = vcpu->arch.guest_debug_dr7; 841 else 842 dr7 = vcpu->arch.dr7; 843 kvm_x86_ops->set_dr7(vcpu, dr7); 844 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 845 if (dr7 & DR7_BP_EN_MASK) 846 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 847} 848 849static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 850{ 851 u64 fixed = DR6_FIXED_1; 852 853 if (!guest_cpuid_has_rtm(vcpu)) 854 fixed |= DR6_RTM; 855 return fixed; 856} 857 858static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 859{ 860 switch (dr) { 861 case 0 ... 3: 862 vcpu->arch.db[dr] = val; 863 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 864 vcpu->arch.eff_db[dr] = val; 865 break; 866 case 4: 867 /* fall through */ 868 case 6: 869 if (val & 0xffffffff00000000ULL) 870 return -1; /* #GP */ 871 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 872 kvm_update_dr6(vcpu); 873 break; 874 case 5: 875 /* fall through */ 876 default: /* 7 */ 877 if (val & 0xffffffff00000000ULL) 878 return -1; /* #GP */ 879 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 880 kvm_update_dr7(vcpu); 881 break; 882 } 883 884 return 0; 885} 886 887int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 888{ 889 if (__kvm_set_dr(vcpu, dr, val)) { 890 kvm_inject_gp(vcpu, 0); 891 return 1; 892 } 893 return 0; 894} 895EXPORT_SYMBOL_GPL(kvm_set_dr); 896 897int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 898{ 899 switch (dr) { 900 case 0 ... 3: 901 *val = vcpu->arch.db[dr]; 902 break; 903 case 4: 904 /* fall through */ 905 case 6: 906 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 907 *val = vcpu->arch.dr6; 908 else 909 *val = kvm_x86_ops->get_dr6(vcpu); 910 break; 911 case 5: 912 /* fall through */ 913 default: /* 7 */ 914 *val = vcpu->arch.dr7; 915 break; 916 } 917 return 0; 918} 919EXPORT_SYMBOL_GPL(kvm_get_dr); 920 921bool kvm_rdpmc(struct kvm_vcpu *vcpu) 922{ 923 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 924 u64 data; 925 int err; 926 927 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 928 if (err) 929 return err; 930 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 931 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 932 return err; 933} 934EXPORT_SYMBOL_GPL(kvm_rdpmc); 935 936/* 937 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 938 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 939 * 940 * This list is modified at module load time to reflect the 941 * capabilities of the host cpu. This capabilities test skips MSRs that are 942 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 943 * may depend on host virtualization features rather than host cpu features. 944 */ 945 946static u32 msrs_to_save[] = { 947 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 948 MSR_STAR, 949#ifdef CONFIG_X86_64 950 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 951#endif 952 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 953 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 954}; 955 956static unsigned num_msrs_to_save; 957 958static u32 emulated_msrs[] = { 959 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 960 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 961 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 962 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 963 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 964 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 965 HV_X64_MSR_RESET, 966 HV_X64_MSR_VP_INDEX, 967 HV_X64_MSR_VP_RUNTIME, 968 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 969 MSR_KVM_PV_EOI_EN, 970 971 MSR_IA32_TSC_ADJUST, 972 MSR_IA32_TSCDEADLINE, 973 MSR_IA32_MISC_ENABLE, 974 MSR_IA32_MCG_STATUS, 975 MSR_IA32_MCG_CTL, 976 MSR_IA32_SMBASE, 977}; 978 979static unsigned num_emulated_msrs; 980 981bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 982{ 983 if (efer & efer_reserved_bits) 984 return false; 985 986 if (efer & EFER_FFXSR) { 987 struct kvm_cpuid_entry2 *feat; 988 989 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 990 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 991 return false; 992 } 993 994 if (efer & EFER_SVME) { 995 struct kvm_cpuid_entry2 *feat; 996 997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 998 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 999 return false; 1000 } 1001 1002 return true; 1003} 1004EXPORT_SYMBOL_GPL(kvm_valid_efer); 1005 1006static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1007{ 1008 u64 old_efer = vcpu->arch.efer; 1009 1010 if (!kvm_valid_efer(vcpu, efer)) 1011 return 1; 1012 1013 if (is_paging(vcpu) 1014 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1015 return 1; 1016 1017 efer &= ~EFER_LMA; 1018 efer |= vcpu->arch.efer & EFER_LMA; 1019 1020 kvm_x86_ops->set_efer(vcpu, efer); 1021 1022 /* Update reserved bits */ 1023 if ((efer ^ old_efer) & EFER_NX) 1024 kvm_mmu_reset_context(vcpu); 1025 1026 return 0; 1027} 1028 1029void kvm_enable_efer_bits(u64 mask) 1030{ 1031 efer_reserved_bits &= ~mask; 1032} 1033EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1034 1035/* 1036 * Writes msr value into into the appropriate "register". 1037 * Returns 0 on success, non-0 otherwise. 1038 * Assumes vcpu_load() was already called. 1039 */ 1040int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1041{ 1042 switch (msr->index) { 1043 case MSR_FS_BASE: 1044 case MSR_GS_BASE: 1045 case MSR_KERNEL_GS_BASE: 1046 case MSR_CSTAR: 1047 case MSR_LSTAR: 1048 if (is_noncanonical_address(msr->data)) 1049 return 1; 1050 break; 1051 case MSR_IA32_SYSENTER_EIP: 1052 case MSR_IA32_SYSENTER_ESP: 1053 /* 1054 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1055 * non-canonical address is written on Intel but not on 1056 * AMD (which ignores the top 32-bits, because it does 1057 * not implement 64-bit SYSENTER). 1058 * 1059 * 64-bit code should hence be able to write a non-canonical 1060 * value on AMD. Making the address canonical ensures that 1061 * vmentry does not fail on Intel after writing a non-canonical 1062 * value, and that something deterministic happens if the guest 1063 * invokes 64-bit SYSENTER. 1064 */ 1065 msr->data = get_canonical(msr->data); 1066 } 1067 return kvm_x86_ops->set_msr(vcpu, msr); 1068} 1069EXPORT_SYMBOL_GPL(kvm_set_msr); 1070 1071/* 1072 * Adapt set_msr() to msr_io()'s calling convention 1073 */ 1074static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1075{ 1076 struct msr_data msr; 1077 int r; 1078 1079 msr.index = index; 1080 msr.host_initiated = true; 1081 r = kvm_get_msr(vcpu, &msr); 1082 if (r) 1083 return r; 1084 1085 *data = msr.data; 1086 return 0; 1087} 1088 1089static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1090{ 1091 struct msr_data msr; 1092 1093 msr.data = *data; 1094 msr.index = index; 1095 msr.host_initiated = true; 1096 return kvm_set_msr(vcpu, &msr); 1097} 1098 1099#ifdef CONFIG_X86_64 1100struct pvclock_gtod_data { 1101 seqcount_t seq; 1102 1103 struct { /* extract of a clocksource struct */ 1104 int vclock_mode; 1105 cycle_t cycle_last; 1106 cycle_t mask; 1107 u32 mult; 1108 u32 shift; 1109 } clock; 1110 1111 u64 boot_ns; 1112 u64 nsec_base; 1113}; 1114 1115static struct pvclock_gtod_data pvclock_gtod_data; 1116 1117static void update_pvclock_gtod(struct timekeeper *tk) 1118{ 1119 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1120 u64 boot_ns; 1121 1122 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1123 1124 write_seqcount_begin(&vdata->seq); 1125 1126 /* copy pvclock gtod data */ 1127 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1128 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1129 vdata->clock.mask = tk->tkr_mono.mask; 1130 vdata->clock.mult = tk->tkr_mono.mult; 1131 vdata->clock.shift = tk->tkr_mono.shift; 1132 1133 vdata->boot_ns = boot_ns; 1134 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1135 1136 write_seqcount_end(&vdata->seq); 1137} 1138#endif 1139 1140void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1141{ 1142 /* 1143 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1144 * vcpu_enter_guest. This function is only called from 1145 * the physical CPU that is running vcpu. 1146 */ 1147 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1148} 1149 1150static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1151{ 1152 int version; 1153 int r; 1154 struct pvclock_wall_clock wc; 1155 struct timespec boot; 1156 1157 if (!wall_clock) 1158 return; 1159 1160 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1161 if (r) 1162 return; 1163 1164 if (version & 1) 1165 ++version; /* first time write, random junk */ 1166 1167 ++version; 1168 1169 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1170 1171 /* 1172 * The guest calculates current wall clock time by adding 1173 * system time (updated by kvm_guest_time_update below) to the 1174 * wall clock specified here. guest system time equals host 1175 * system time for us, thus we must fill in host boot time here. 1176 */ 1177 getboottime(&boot); 1178 1179 if (kvm->arch.kvmclock_offset) { 1180 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1181 boot = timespec_sub(boot, ts); 1182 } 1183 wc.sec = boot.tv_sec; 1184 wc.nsec = boot.tv_nsec; 1185 wc.version = version; 1186 1187 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1188 1189 version++; 1190 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1191} 1192 1193static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1194{ 1195 uint32_t quotient, remainder; 1196 1197 /* Don't try to replace with do_div(), this one calculates 1198 * "(dividend << 32) / divisor" */ 1199 __asm__ ( "divl %4" 1200 : "=a" (quotient), "=d" (remainder) 1201 : "0" (0), "1" (dividend), "r" (divisor) ); 1202 return quotient; 1203} 1204 1205static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1206 s8 *pshift, u32 *pmultiplier) 1207{ 1208 uint64_t scaled64; 1209 int32_t shift = 0; 1210 uint64_t tps64; 1211 uint32_t tps32; 1212 1213 tps64 = base_khz * 1000LL; 1214 scaled64 = scaled_khz * 1000LL; 1215 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1216 tps64 >>= 1; 1217 shift--; 1218 } 1219 1220 tps32 = (uint32_t)tps64; 1221 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1222 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1223 scaled64 >>= 1; 1224 else 1225 tps32 <<= 1; 1226 shift++; 1227 } 1228 1229 *pshift = shift; 1230 *pmultiplier = div_frac(scaled64, tps32); 1231 1232 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1233 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1234} 1235 1236#ifdef CONFIG_X86_64 1237static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1238#endif 1239 1240static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1241static unsigned long max_tsc_khz; 1242 1243static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1244{ 1245 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1246 vcpu->arch.virtual_tsc_shift); 1247} 1248 1249static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1250{ 1251 u64 v = (u64)khz * (1000000 + ppm); 1252 do_div(v, 1000000); 1253 return v; 1254} 1255 1256static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1257{ 1258 u64 ratio; 1259 1260 /* Guest TSC same frequency as host TSC? */ 1261 if (!scale) { 1262 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1263 return 0; 1264 } 1265 1266 /* TSC scaling supported? */ 1267 if (!kvm_has_tsc_control) { 1268 if (user_tsc_khz > tsc_khz) { 1269 vcpu->arch.tsc_catchup = 1; 1270 vcpu->arch.tsc_always_catchup = 1; 1271 return 0; 1272 } else { 1273 WARN(1, "user requested TSC rate below hardware speed\n"); 1274 return -1; 1275 } 1276 } 1277 1278 /* TSC scaling required - calculate ratio */ 1279 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1280 user_tsc_khz, tsc_khz); 1281 1282 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1283 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1284 user_tsc_khz); 1285 return -1; 1286 } 1287 1288 vcpu->arch.tsc_scaling_ratio = ratio; 1289 return 0; 1290} 1291 1292static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1293{ 1294 u32 thresh_lo, thresh_hi; 1295 int use_scaling = 0; 1296 1297 /* tsc_khz can be zero if TSC calibration fails */ 1298 if (this_tsc_khz == 0) { 1299 /* set tsc_scaling_ratio to a safe value */ 1300 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1301 return -1; 1302 } 1303 1304 /* Compute a scale to convert nanoseconds in TSC cycles */ 1305 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1306 &vcpu->arch.virtual_tsc_shift, 1307 &vcpu->arch.virtual_tsc_mult); 1308 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1309 1310 /* 1311 * Compute the variation in TSC rate which is acceptable 1312 * within the range of tolerance and decide if the 1313 * rate being applied is within that bounds of the hardware 1314 * rate. If so, no scaling or compensation need be done. 1315 */ 1316 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1317 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1318 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1319 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1320 use_scaling = 1; 1321 } 1322 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1323} 1324 1325static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1326{ 1327 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1328 vcpu->arch.virtual_tsc_mult, 1329 vcpu->arch.virtual_tsc_shift); 1330 tsc += vcpu->arch.this_tsc_write; 1331 return tsc; 1332} 1333 1334static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1335{ 1336#ifdef CONFIG_X86_64 1337 bool vcpus_matched; 1338 struct kvm_arch *ka = &vcpu->kvm->arch; 1339 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1340 1341 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1342 atomic_read(&vcpu->kvm->online_vcpus)); 1343 1344 /* 1345 * Once the masterclock is enabled, always perform request in 1346 * order to update it. 1347 * 1348 * In order to enable masterclock, the host clocksource must be TSC 1349 * and the vcpus need to have matched TSCs. When that happens, 1350 * perform request to enable masterclock. 1351 */ 1352 if (ka->use_master_clock || 1353 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1354 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1355 1356 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1357 atomic_read(&vcpu->kvm->online_vcpus), 1358 ka->use_master_clock, gtod->clock.vclock_mode); 1359#endif 1360} 1361 1362static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1363{ 1364 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1365 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1366} 1367 1368/* 1369 * Multiply tsc by a fixed point number represented by ratio. 1370 * 1371 * The most significant 64-N bits (mult) of ratio represent the 1372 * integral part of the fixed point number; the remaining N bits 1373 * (frac) represent the fractional part, ie. ratio represents a fixed 1374 * point number (mult + frac * 2^(-N)). 1375 * 1376 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1377 */ 1378static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1379{ 1380 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1381} 1382 1383u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1384{ 1385 u64 _tsc = tsc; 1386 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1387 1388 if (ratio != kvm_default_tsc_scaling_ratio) 1389 _tsc = __scale_tsc(ratio, tsc); 1390 1391 return _tsc; 1392} 1393EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1394 1395static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1396{ 1397 u64 tsc; 1398 1399 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1400 1401 return target_tsc - tsc; 1402} 1403 1404u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1405{ 1406 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc)); 1407} 1408EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1409 1410void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1411{ 1412 struct kvm *kvm = vcpu->kvm; 1413 u64 offset, ns, elapsed; 1414 unsigned long flags; 1415 s64 usdiff; 1416 bool matched; 1417 bool already_matched; 1418 u64 data = msr->data; 1419 1420 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1421 offset = kvm_compute_tsc_offset(vcpu, data); 1422 ns = get_kernel_ns(); 1423 elapsed = ns - kvm->arch.last_tsc_nsec; 1424 1425 if (vcpu->arch.virtual_tsc_khz) { 1426 int faulted = 0; 1427 1428 /* n.b - signed multiplication and division required */ 1429 usdiff = data - kvm->arch.last_tsc_write; 1430#ifdef CONFIG_X86_64 1431 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1432#else 1433 /* do_div() only does unsigned */ 1434 asm("1: idivl %[divisor]\n" 1435 "2: xor %%edx, %%edx\n" 1436 " movl $0, %[faulted]\n" 1437 "3:\n" 1438 ".section .fixup,\"ax\"\n" 1439 "4: movl $1, %[faulted]\n" 1440 " jmp 3b\n" 1441 ".previous\n" 1442 1443 _ASM_EXTABLE(1b, 4b) 1444 1445 : "=A"(usdiff), [faulted] "=r" (faulted) 1446 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1447 1448#endif 1449 do_div(elapsed, 1000); 1450 usdiff -= elapsed; 1451 if (usdiff < 0) 1452 usdiff = -usdiff; 1453 1454 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1455 if (faulted) 1456 usdiff = USEC_PER_SEC; 1457 } else 1458 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1459 1460 /* 1461 * Special case: TSC write with a small delta (1 second) of virtual 1462 * cycle time against real time is interpreted as an attempt to 1463 * synchronize the CPU. 1464 * 1465 * For a reliable TSC, we can match TSC offsets, and for an unstable 1466 * TSC, we add elapsed time in this computation. We could let the 1467 * compensation code attempt to catch up if we fall behind, but 1468 * it's better to try to match offsets from the beginning. 1469 */ 1470 if (usdiff < USEC_PER_SEC && 1471 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1472 if (!check_tsc_unstable()) { 1473 offset = kvm->arch.cur_tsc_offset; 1474 pr_debug("kvm: matched tsc offset for %llu\n", data); 1475 } else { 1476 u64 delta = nsec_to_cycles(vcpu, elapsed); 1477 data += delta; 1478 offset = kvm_compute_tsc_offset(vcpu, data); 1479 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1480 } 1481 matched = true; 1482 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1483 } else { 1484 /* 1485 * We split periods of matched TSC writes into generations. 1486 * For each generation, we track the original measured 1487 * nanosecond time, offset, and write, so if TSCs are in 1488 * sync, we can match exact offset, and if not, we can match 1489 * exact software computation in compute_guest_tsc() 1490 * 1491 * These values are tracked in kvm->arch.cur_xxx variables. 1492 */ 1493 kvm->arch.cur_tsc_generation++; 1494 kvm->arch.cur_tsc_nsec = ns; 1495 kvm->arch.cur_tsc_write = data; 1496 kvm->arch.cur_tsc_offset = offset; 1497 matched = false; 1498 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1499 kvm->arch.cur_tsc_generation, data); 1500 } 1501 1502 /* 1503 * We also track th most recent recorded KHZ, write and time to 1504 * allow the matching interval to be extended at each write. 1505 */ 1506 kvm->arch.last_tsc_nsec = ns; 1507 kvm->arch.last_tsc_write = data; 1508 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1509 1510 vcpu->arch.last_guest_tsc = data; 1511 1512 /* Keep track of which generation this VCPU has synchronized to */ 1513 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1514 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1515 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1516 1517 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1518 update_ia32_tsc_adjust_msr(vcpu, offset); 1519 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1520 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1521 1522 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1523 if (!matched) { 1524 kvm->arch.nr_vcpus_matched_tsc = 0; 1525 } else if (!already_matched) { 1526 kvm->arch.nr_vcpus_matched_tsc++; 1527 } 1528 1529 kvm_track_tsc_matching(vcpu); 1530 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1531} 1532 1533EXPORT_SYMBOL_GPL(kvm_write_tsc); 1534 1535static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1536 s64 adjustment) 1537{ 1538 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1539} 1540 1541static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1542{ 1543 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1544 WARN_ON(adjustment < 0); 1545 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1546 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1547} 1548 1549#ifdef CONFIG_X86_64 1550 1551static cycle_t read_tsc(void) 1552{ 1553 cycle_t ret = (cycle_t)rdtsc_ordered(); 1554 u64 last = pvclock_gtod_data.clock.cycle_last; 1555 1556 if (likely(ret >= last)) 1557 return ret; 1558 1559 /* 1560 * GCC likes to generate cmov here, but this branch is extremely 1561 * predictable (it's just a funciton of time and the likely is 1562 * very likely) and there's a data dependence, so force GCC 1563 * to generate a branch instead. I don't barrier() because 1564 * we don't actually need a barrier, and if this function 1565 * ever gets inlined it will generate worse code. 1566 */ 1567 asm volatile (""); 1568 return last; 1569} 1570 1571static inline u64 vgettsc(cycle_t *cycle_now) 1572{ 1573 long v; 1574 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1575 1576 *cycle_now = read_tsc(); 1577 1578 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1579 return v * gtod->clock.mult; 1580} 1581 1582static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1583{ 1584 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1585 unsigned long seq; 1586 int mode; 1587 u64 ns; 1588 1589 do { 1590 seq = read_seqcount_begin(>od->seq); 1591 mode = gtod->clock.vclock_mode; 1592 ns = gtod->nsec_base; 1593 ns += vgettsc(cycle_now); 1594 ns >>= gtod->clock.shift; 1595 ns += gtod->boot_ns; 1596 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1597 *t = ns; 1598 1599 return mode; 1600} 1601 1602/* returns true if host is using tsc clocksource */ 1603static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1604{ 1605 /* checked again under seqlock below */ 1606 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1607 return false; 1608 1609 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1610} 1611#endif 1612 1613/* 1614 * 1615 * Assuming a stable TSC across physical CPUS, and a stable TSC 1616 * across virtual CPUs, the following condition is possible. 1617 * Each numbered line represents an event visible to both 1618 * CPUs at the next numbered event. 1619 * 1620 * "timespecX" represents host monotonic time. "tscX" represents 1621 * RDTSC value. 1622 * 1623 * VCPU0 on CPU0 | VCPU1 on CPU1 1624 * 1625 * 1. read timespec0,tsc0 1626 * 2. | timespec1 = timespec0 + N 1627 * | tsc1 = tsc0 + M 1628 * 3. transition to guest | transition to guest 1629 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1630 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1631 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1632 * 1633 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1634 * 1635 * - ret0 < ret1 1636 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1637 * ... 1638 * - 0 < N - M => M < N 1639 * 1640 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1641 * always the case (the difference between two distinct xtime instances 1642 * might be smaller then the difference between corresponding TSC reads, 1643 * when updating guest vcpus pvclock areas). 1644 * 1645 * To avoid that problem, do not allow visibility of distinct 1646 * system_timestamp/tsc_timestamp values simultaneously: use a master 1647 * copy of host monotonic time values. Update that master copy 1648 * in lockstep. 1649 * 1650 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1651 * 1652 */ 1653 1654static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1655{ 1656#ifdef CONFIG_X86_64 1657 struct kvm_arch *ka = &kvm->arch; 1658 int vclock_mode; 1659 bool host_tsc_clocksource, vcpus_matched; 1660 1661 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1662 atomic_read(&kvm->online_vcpus)); 1663 1664 /* 1665 * If the host uses TSC clock, then passthrough TSC as stable 1666 * to the guest. 1667 */ 1668 host_tsc_clocksource = kvm_get_time_and_clockread( 1669 &ka->master_kernel_ns, 1670 &ka->master_cycle_now); 1671 1672 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1673 && !backwards_tsc_observed 1674 && !ka->boot_vcpu_runs_old_kvmclock; 1675 1676 if (ka->use_master_clock) 1677 atomic_set(&kvm_guest_has_master_clock, 1); 1678 1679 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1680 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1681 vcpus_matched); 1682#endif 1683} 1684 1685static void kvm_gen_update_masterclock(struct kvm *kvm) 1686{ 1687#ifdef CONFIG_X86_64 1688 int i; 1689 struct kvm_vcpu *vcpu; 1690 struct kvm_arch *ka = &kvm->arch; 1691 1692 spin_lock(&ka->pvclock_gtod_sync_lock); 1693 kvm_make_mclock_inprogress_request(kvm); 1694 /* no guest entries from this point */ 1695 pvclock_update_vm_gtod_copy(kvm); 1696 1697 kvm_for_each_vcpu(i, vcpu, kvm) 1698 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1699 1700 /* guest entries allowed */ 1701 kvm_for_each_vcpu(i, vcpu, kvm) 1702 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1703 1704 spin_unlock(&ka->pvclock_gtod_sync_lock); 1705#endif 1706} 1707 1708static int kvm_guest_time_update(struct kvm_vcpu *v) 1709{ 1710 unsigned long flags, this_tsc_khz, tgt_tsc_khz; 1711 struct kvm_vcpu_arch *vcpu = &v->arch; 1712 struct kvm_arch *ka = &v->kvm->arch; 1713 s64 kernel_ns; 1714 u64 tsc_timestamp, host_tsc; 1715 struct pvclock_vcpu_time_info guest_hv_clock; 1716 u8 pvclock_flags; 1717 bool use_master_clock; 1718 1719 kernel_ns = 0; 1720 host_tsc = 0; 1721 1722 /* 1723 * If the host uses TSC clock, then passthrough TSC as stable 1724 * to the guest. 1725 */ 1726 spin_lock(&ka->pvclock_gtod_sync_lock); 1727 use_master_clock = ka->use_master_clock; 1728 if (use_master_clock) { 1729 host_tsc = ka->master_cycle_now; 1730 kernel_ns = ka->master_kernel_ns; 1731 } 1732 spin_unlock(&ka->pvclock_gtod_sync_lock); 1733 1734 /* Keep irq disabled to prevent changes to the clock */ 1735 local_irq_save(flags); 1736 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1737 if (unlikely(this_tsc_khz == 0)) { 1738 local_irq_restore(flags); 1739 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1740 return 1; 1741 } 1742 if (!use_master_clock) { 1743 host_tsc = rdtsc(); 1744 kernel_ns = get_kernel_ns(); 1745 } 1746 1747 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1748 1749 /* 1750 * We may have to catch up the TSC to match elapsed wall clock 1751 * time for two reasons, even if kvmclock is used. 1752 * 1) CPU could have been running below the maximum TSC rate 1753 * 2) Broken TSC compensation resets the base at each VCPU 1754 * entry to avoid unknown leaps of TSC even when running 1755 * again on the same CPU. This may cause apparent elapsed 1756 * time to disappear, and the guest to stand still or run 1757 * very slowly. 1758 */ 1759 if (vcpu->tsc_catchup) { 1760 u64 tsc = compute_guest_tsc(v, kernel_ns); 1761 if (tsc > tsc_timestamp) { 1762 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1763 tsc_timestamp = tsc; 1764 } 1765 } 1766 1767 local_irq_restore(flags); 1768 1769 if (!vcpu->pv_time_enabled) 1770 return 0; 1771 1772 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1773 tgt_tsc_khz = kvm_has_tsc_control ? 1774 vcpu->virtual_tsc_khz : this_tsc_khz; 1775 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz, 1776 &vcpu->hv_clock.tsc_shift, 1777 &vcpu->hv_clock.tsc_to_system_mul); 1778 vcpu->hw_tsc_khz = this_tsc_khz; 1779 } 1780 1781 /* With all the info we got, fill in the values */ 1782 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1783 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1784 vcpu->last_guest_tsc = tsc_timestamp; 1785 1786 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1787 &guest_hv_clock, sizeof(guest_hv_clock)))) 1788 return 0; 1789 1790 /* This VCPU is paused, but it's legal for a guest to read another 1791 * VCPU's kvmclock, so we really have to follow the specification where 1792 * it says that version is odd if data is being modified, and even after 1793 * it is consistent. 1794 * 1795 * Version field updates must be kept separate. This is because 1796 * kvm_write_guest_cached might use a "rep movs" instruction, and 1797 * writes within a string instruction are weakly ordered. So there 1798 * are three writes overall. 1799 * 1800 * As a small optimization, only write the version field in the first 1801 * and third write. The vcpu->pv_time cache is still valid, because the 1802 * version field is the first in the struct. 1803 */ 1804 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1805 1806 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1807 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1808 &vcpu->hv_clock, 1809 sizeof(vcpu->hv_clock.version)); 1810 1811 smp_wmb(); 1812 1813 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1814 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1815 1816 if (vcpu->pvclock_set_guest_stopped_request) { 1817 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1818 vcpu->pvclock_set_guest_stopped_request = false; 1819 } 1820 1821 /* If the host uses TSC clocksource, then it is stable */ 1822 if (use_master_clock) 1823 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1824 1825 vcpu->hv_clock.flags = pvclock_flags; 1826 1827 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1828 1829 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1830 &vcpu->hv_clock, 1831 sizeof(vcpu->hv_clock)); 1832 1833 smp_wmb(); 1834 1835 vcpu->hv_clock.version++; 1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1837 &vcpu->hv_clock, 1838 sizeof(vcpu->hv_clock.version)); 1839 return 0; 1840} 1841 1842/* 1843 * kvmclock updates which are isolated to a given vcpu, such as 1844 * vcpu->cpu migration, should not allow system_timestamp from 1845 * the rest of the vcpus to remain static. Otherwise ntp frequency 1846 * correction applies to one vcpu's system_timestamp but not 1847 * the others. 1848 * 1849 * So in those cases, request a kvmclock update for all vcpus. 1850 * We need to rate-limit these requests though, as they can 1851 * considerably slow guests that have a large number of vcpus. 1852 * The time for a remote vcpu to update its kvmclock is bound 1853 * by the delay we use to rate-limit the updates. 1854 */ 1855 1856#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1857 1858static void kvmclock_update_fn(struct work_struct *work) 1859{ 1860 int i; 1861 struct delayed_work *dwork = to_delayed_work(work); 1862 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1863 kvmclock_update_work); 1864 struct kvm *kvm = container_of(ka, struct kvm, arch); 1865 struct kvm_vcpu *vcpu; 1866 1867 kvm_for_each_vcpu(i, vcpu, kvm) { 1868 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1869 kvm_vcpu_kick(vcpu); 1870 } 1871} 1872 1873static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1874{ 1875 struct kvm *kvm = v->kvm; 1876 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1878 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1879 KVMCLOCK_UPDATE_DELAY); 1880} 1881 1882#define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1883 1884static void kvmclock_sync_fn(struct work_struct *work) 1885{ 1886 struct delayed_work *dwork = to_delayed_work(work); 1887 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1888 kvmclock_sync_work); 1889 struct kvm *kvm = container_of(ka, struct kvm, arch); 1890 1891 if (!kvmclock_periodic_sync) 1892 return; 1893 1894 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1895 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1896 KVMCLOCK_SYNC_PERIOD); 1897} 1898 1899static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1900{ 1901 u64 mcg_cap = vcpu->arch.mcg_cap; 1902 unsigned bank_num = mcg_cap & 0xff; 1903 1904 switch (msr) { 1905 case MSR_IA32_MCG_STATUS: 1906 vcpu->arch.mcg_status = data; 1907 break; 1908 case MSR_IA32_MCG_CTL: 1909 if (!(mcg_cap & MCG_CTL_P)) 1910 return 1; 1911 if (data != 0 && data != ~(u64)0) 1912 return -1; 1913 vcpu->arch.mcg_ctl = data; 1914 break; 1915 default: 1916 if (msr >= MSR_IA32_MC0_CTL && 1917 msr < MSR_IA32_MCx_CTL(bank_num)) { 1918 u32 offset = msr - MSR_IA32_MC0_CTL; 1919 /* only 0 or all 1s can be written to IA32_MCi_CTL 1920 * some Linux kernels though clear bit 10 in bank 4 to 1921 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1922 * this to avoid an uncatched #GP in the guest 1923 */ 1924 if ((offset & 0x3) == 0 && 1925 data != 0 && (data | (1 << 10)) != ~(u64)0) 1926 return -1; 1927 vcpu->arch.mce_banks[offset] = data; 1928 break; 1929 } 1930 return 1; 1931 } 1932 return 0; 1933} 1934 1935static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1936{ 1937 struct kvm *kvm = vcpu->kvm; 1938 int lm = is_long_mode(vcpu); 1939 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1940 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1941 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1942 : kvm->arch.xen_hvm_config.blob_size_32; 1943 u32 page_num = data & ~PAGE_MASK; 1944 u64 page_addr = data & PAGE_MASK; 1945 u8 *page; 1946 int r; 1947 1948 r = -E2BIG; 1949 if (page_num >= blob_size) 1950 goto out; 1951 r = -ENOMEM; 1952 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1953 if (IS_ERR(page)) { 1954 r = PTR_ERR(page); 1955 goto out; 1956 } 1957 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 1958 goto out_free; 1959 r = 0; 1960out_free: 1961 kfree(page); 1962out: 1963 return r; 1964} 1965 1966static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1967{ 1968 gpa_t gpa = data & ~0x3f; 1969 1970 /* Bits 2:5 are reserved, Should be zero */ 1971 if (data & 0x3c) 1972 return 1; 1973 1974 vcpu->arch.apf.msr_val = data; 1975 1976 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1977 kvm_clear_async_pf_completion_queue(vcpu); 1978 kvm_async_pf_hash_reset(vcpu); 1979 return 0; 1980 } 1981 1982 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1983 sizeof(u32))) 1984 return 1; 1985 1986 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1987 kvm_async_pf_wakeup_all(vcpu); 1988 return 0; 1989} 1990 1991static void kvmclock_reset(struct kvm_vcpu *vcpu) 1992{ 1993 vcpu->arch.pv_time_enabled = false; 1994} 1995 1996static void accumulate_steal_time(struct kvm_vcpu *vcpu) 1997{ 1998 u64 delta; 1999 2000 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2001 return; 2002 2003 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2004 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2005 vcpu->arch.st.accum_steal = delta; 2006} 2007 2008static void record_steal_time(struct kvm_vcpu *vcpu) 2009{ 2010 accumulate_steal_time(vcpu); 2011 2012 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2013 return; 2014 2015 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2016 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2017 return; 2018 2019 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2020 vcpu->arch.st.steal.version += 2; 2021 vcpu->arch.st.accum_steal = 0; 2022 2023 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2024 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2025} 2026 2027int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2028{ 2029 bool pr = false; 2030 u32 msr = msr_info->index; 2031 u64 data = msr_info->data; 2032 2033 switch (msr) { 2034 case MSR_AMD64_NB_CFG: 2035 case MSR_IA32_UCODE_REV: 2036 case MSR_IA32_UCODE_WRITE: 2037 case MSR_VM_HSAVE_PA: 2038 case MSR_AMD64_PATCH_LOADER: 2039 case MSR_AMD64_BU_CFG2: 2040 break; 2041 2042 case MSR_EFER: 2043 return set_efer(vcpu, data); 2044 case MSR_K7_HWCR: 2045 data &= ~(u64)0x40; /* ignore flush filter disable */ 2046 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2047 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2048 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2049 if (data != 0) { 2050 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2051 data); 2052 return 1; 2053 } 2054 break; 2055 case MSR_FAM10H_MMIO_CONF_BASE: 2056 if (data != 0) { 2057 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2058 "0x%llx\n", data); 2059 return 1; 2060 } 2061 break; 2062 case MSR_IA32_DEBUGCTLMSR: 2063 if (!data) { 2064 /* We support the non-activated case already */ 2065 break; 2066 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2067 /* Values other than LBR and BTF are vendor-specific, 2068 thus reserved and should throw a #GP */ 2069 return 1; 2070 } 2071 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2072 __func__, data); 2073 break; 2074 case 0x200 ... 0x2ff: 2075 return kvm_mtrr_set_msr(vcpu, msr, data); 2076 case MSR_IA32_APICBASE: 2077 return kvm_set_apic_base(vcpu, msr_info); 2078 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2079 return kvm_x2apic_msr_write(vcpu, msr, data); 2080 case MSR_IA32_TSCDEADLINE: 2081 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2082 break; 2083 case MSR_IA32_TSC_ADJUST: 2084 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2085 if (!msr_info->host_initiated) { 2086 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2087 adjust_tsc_offset_guest(vcpu, adj); 2088 } 2089 vcpu->arch.ia32_tsc_adjust_msr = data; 2090 } 2091 break; 2092 case MSR_IA32_MISC_ENABLE: 2093 vcpu->arch.ia32_misc_enable_msr = data; 2094 break; 2095 case MSR_IA32_SMBASE: 2096 if (!msr_info->host_initiated) 2097 return 1; 2098 vcpu->arch.smbase = data; 2099 break; 2100 case MSR_KVM_WALL_CLOCK_NEW: 2101 case MSR_KVM_WALL_CLOCK: 2102 vcpu->kvm->arch.wall_clock = data; 2103 kvm_write_wall_clock(vcpu->kvm, data); 2104 break; 2105 case MSR_KVM_SYSTEM_TIME_NEW: 2106 case MSR_KVM_SYSTEM_TIME: { 2107 u64 gpa_offset; 2108 struct kvm_arch *ka = &vcpu->kvm->arch; 2109 2110 kvmclock_reset(vcpu); 2111 2112 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2113 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2114 2115 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2116 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2117 &vcpu->requests); 2118 2119 ka->boot_vcpu_runs_old_kvmclock = tmp; 2120 } 2121 2122 vcpu->arch.time = data; 2123 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2124 2125 /* we verify if the enable bit is set... */ 2126 if (!(data & 1)) 2127 break; 2128 2129 gpa_offset = data & ~(PAGE_MASK | 1); 2130 2131 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2132 &vcpu->arch.pv_time, data & ~1ULL, 2133 sizeof(struct pvclock_vcpu_time_info))) 2134 vcpu->arch.pv_time_enabled = false; 2135 else 2136 vcpu->arch.pv_time_enabled = true; 2137 2138 break; 2139 } 2140 case MSR_KVM_ASYNC_PF_EN: 2141 if (kvm_pv_enable_async_pf(vcpu, data)) 2142 return 1; 2143 break; 2144 case MSR_KVM_STEAL_TIME: 2145 2146 if (unlikely(!sched_info_on())) 2147 return 1; 2148 2149 if (data & KVM_STEAL_RESERVED_MASK) 2150 return 1; 2151 2152 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2153 data & KVM_STEAL_VALID_BITS, 2154 sizeof(struct kvm_steal_time))) 2155 return 1; 2156 2157 vcpu->arch.st.msr_val = data; 2158 2159 if (!(data & KVM_MSR_ENABLED)) 2160 break; 2161 2162 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2163 2164 break; 2165 case MSR_KVM_PV_EOI_EN: 2166 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2167 return 1; 2168 break; 2169 2170 case MSR_IA32_MCG_CTL: 2171 case MSR_IA32_MCG_STATUS: 2172 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2173 return set_msr_mce(vcpu, msr, data); 2174 2175 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2176 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2177 pr = true; /* fall through */ 2178 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2179 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2180 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2181 return kvm_pmu_set_msr(vcpu, msr_info); 2182 2183 if (pr || data != 0) 2184 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2185 "0x%x data 0x%llx\n", msr, data); 2186 break; 2187 case MSR_K7_CLK_CTL: 2188 /* 2189 * Ignore all writes to this no longer documented MSR. 2190 * Writes are only relevant for old K7 processors, 2191 * all pre-dating SVM, but a recommended workaround from 2192 * AMD for these chips. It is possible to specify the 2193 * affected processor models on the command line, hence 2194 * the need to ignore the workaround. 2195 */ 2196 break; 2197 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2198 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2199 case HV_X64_MSR_CRASH_CTL: 2200 return kvm_hv_set_msr_common(vcpu, msr, data, 2201 msr_info->host_initiated); 2202 case MSR_IA32_BBL_CR_CTL3: 2203 /* Drop writes to this legacy MSR -- see rdmsr 2204 * counterpart for further detail. 2205 */ 2206 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2207 break; 2208 case MSR_AMD64_OSVW_ID_LENGTH: 2209 if (!guest_cpuid_has_osvw(vcpu)) 2210 return 1; 2211 vcpu->arch.osvw.length = data; 2212 break; 2213 case MSR_AMD64_OSVW_STATUS: 2214 if (!guest_cpuid_has_osvw(vcpu)) 2215 return 1; 2216 vcpu->arch.osvw.status = data; 2217 break; 2218 default: 2219 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2220 return xen_hvm_config(vcpu, data); 2221 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2222 return kvm_pmu_set_msr(vcpu, msr_info); 2223 if (!ignore_msrs) { 2224 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2225 msr, data); 2226 return 1; 2227 } else { 2228 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2229 msr, data); 2230 break; 2231 } 2232 } 2233 return 0; 2234} 2235EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2236 2237 2238/* 2239 * Reads an msr value (of 'msr_index') into 'pdata'. 2240 * Returns 0 on success, non-0 otherwise. 2241 * Assumes vcpu_load() was already called. 2242 */ 2243int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2244{ 2245 return kvm_x86_ops->get_msr(vcpu, msr); 2246} 2247EXPORT_SYMBOL_GPL(kvm_get_msr); 2248 2249static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2250{ 2251 u64 data; 2252 u64 mcg_cap = vcpu->arch.mcg_cap; 2253 unsigned bank_num = mcg_cap & 0xff; 2254 2255 switch (msr) { 2256 case MSR_IA32_P5_MC_ADDR: 2257 case MSR_IA32_P5_MC_TYPE: 2258 data = 0; 2259 break; 2260 case MSR_IA32_MCG_CAP: 2261 data = vcpu->arch.mcg_cap; 2262 break; 2263 case MSR_IA32_MCG_CTL: 2264 if (!(mcg_cap & MCG_CTL_P)) 2265 return 1; 2266 data = vcpu->arch.mcg_ctl; 2267 break; 2268 case MSR_IA32_MCG_STATUS: 2269 data = vcpu->arch.mcg_status; 2270 break; 2271 default: 2272 if (msr >= MSR_IA32_MC0_CTL && 2273 msr < MSR_IA32_MCx_CTL(bank_num)) { 2274 u32 offset = msr - MSR_IA32_MC0_CTL; 2275 data = vcpu->arch.mce_banks[offset]; 2276 break; 2277 } 2278 return 1; 2279 } 2280 *pdata = data; 2281 return 0; 2282} 2283 2284int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2285{ 2286 switch (msr_info->index) { 2287 case MSR_IA32_PLATFORM_ID: 2288 case MSR_IA32_EBL_CR_POWERON: 2289 case MSR_IA32_DEBUGCTLMSR: 2290 case MSR_IA32_LASTBRANCHFROMIP: 2291 case MSR_IA32_LASTBRANCHTOIP: 2292 case MSR_IA32_LASTINTFROMIP: 2293 case MSR_IA32_LASTINTTOIP: 2294 case MSR_K8_SYSCFG: 2295 case MSR_K8_TSEG_ADDR: 2296 case MSR_K8_TSEG_MASK: 2297 case MSR_K7_HWCR: 2298 case MSR_VM_HSAVE_PA: 2299 case MSR_K8_INT_PENDING_MSG: 2300 case MSR_AMD64_NB_CFG: 2301 case MSR_FAM10H_MMIO_CONF_BASE: 2302 case MSR_AMD64_BU_CFG2: 2303 msr_info->data = 0; 2304 break; 2305 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2306 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2307 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2308 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2309 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2310 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2311 msr_info->data = 0; 2312 break; 2313 case MSR_IA32_UCODE_REV: 2314 msr_info->data = 0x100000000ULL; 2315 break; 2316 case MSR_MTRRcap: 2317 case 0x200 ... 0x2ff: 2318 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2319 case 0xcd: /* fsb frequency */ 2320 msr_info->data = 3; 2321 break; 2322 /* 2323 * MSR_EBC_FREQUENCY_ID 2324 * Conservative value valid for even the basic CPU models. 2325 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2326 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2327 * and 266MHz for model 3, or 4. Set Core Clock 2328 * Frequency to System Bus Frequency Ratio to 1 (bits 2329 * 31:24) even though these are only valid for CPU 2330 * models > 2, however guests may end up dividing or 2331 * multiplying by zero otherwise. 2332 */ 2333 case MSR_EBC_FREQUENCY_ID: 2334 msr_info->data = 1 << 24; 2335 break; 2336 case MSR_IA32_APICBASE: 2337 msr_info->data = kvm_get_apic_base(vcpu); 2338 break; 2339 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2340 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2341 break; 2342 case MSR_IA32_TSCDEADLINE: 2343 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2344 break; 2345 case MSR_IA32_TSC_ADJUST: 2346 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2347 break; 2348 case MSR_IA32_MISC_ENABLE: 2349 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2350 break; 2351 case MSR_IA32_SMBASE: 2352 if (!msr_info->host_initiated) 2353 return 1; 2354 msr_info->data = vcpu->arch.smbase; 2355 break; 2356 case MSR_IA32_PERF_STATUS: 2357 /* TSC increment by tick */ 2358 msr_info->data = 1000ULL; 2359 /* CPU multiplier */ 2360 msr_info->data |= (((uint64_t)4ULL) << 40); 2361 break; 2362 case MSR_EFER: 2363 msr_info->data = vcpu->arch.efer; 2364 break; 2365 case MSR_KVM_WALL_CLOCK: 2366 case MSR_KVM_WALL_CLOCK_NEW: 2367 msr_info->data = vcpu->kvm->arch.wall_clock; 2368 break; 2369 case MSR_KVM_SYSTEM_TIME: 2370 case MSR_KVM_SYSTEM_TIME_NEW: 2371 msr_info->data = vcpu->arch.time; 2372 break; 2373 case MSR_KVM_ASYNC_PF_EN: 2374 msr_info->data = vcpu->arch.apf.msr_val; 2375 break; 2376 case MSR_KVM_STEAL_TIME: 2377 msr_info->data = vcpu->arch.st.msr_val; 2378 break; 2379 case MSR_KVM_PV_EOI_EN: 2380 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2381 break; 2382 case MSR_IA32_P5_MC_ADDR: 2383 case MSR_IA32_P5_MC_TYPE: 2384 case MSR_IA32_MCG_CAP: 2385 case MSR_IA32_MCG_CTL: 2386 case MSR_IA32_MCG_STATUS: 2387 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2388 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2389 case MSR_K7_CLK_CTL: 2390 /* 2391 * Provide expected ramp-up count for K7. All other 2392 * are set to zero, indicating minimum divisors for 2393 * every field. 2394 * 2395 * This prevents guest kernels on AMD host with CPU 2396 * type 6, model 8 and higher from exploding due to 2397 * the rdmsr failing. 2398 */ 2399 msr_info->data = 0x20000000; 2400 break; 2401 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2402 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2403 case HV_X64_MSR_CRASH_CTL: 2404 return kvm_hv_get_msr_common(vcpu, 2405 msr_info->index, &msr_info->data); 2406 break; 2407 case MSR_IA32_BBL_CR_CTL3: 2408 /* This legacy MSR exists but isn't fully documented in current 2409 * silicon. It is however accessed by winxp in very narrow 2410 * scenarios where it sets bit #19, itself documented as 2411 * a "reserved" bit. Best effort attempt to source coherent 2412 * read data here should the balance of the register be 2413 * interpreted by the guest: 2414 * 2415 * L2 cache control register 3: 64GB range, 256KB size, 2416 * enabled, latency 0x1, configured 2417 */ 2418 msr_info->data = 0xbe702111; 2419 break; 2420 case MSR_AMD64_OSVW_ID_LENGTH: 2421 if (!guest_cpuid_has_osvw(vcpu)) 2422 return 1; 2423 msr_info->data = vcpu->arch.osvw.length; 2424 break; 2425 case MSR_AMD64_OSVW_STATUS: 2426 if (!guest_cpuid_has_osvw(vcpu)) 2427 return 1; 2428 msr_info->data = vcpu->arch.osvw.status; 2429 break; 2430 default: 2431 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2432 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2433 if (!ignore_msrs) { 2434 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); 2435 return 1; 2436 } else { 2437 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2438 msr_info->data = 0; 2439 } 2440 break; 2441 } 2442 return 0; 2443} 2444EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2445 2446/* 2447 * Read or write a bunch of msrs. All parameters are kernel addresses. 2448 * 2449 * @return number of msrs set successfully. 2450 */ 2451static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2452 struct kvm_msr_entry *entries, 2453 int (*do_msr)(struct kvm_vcpu *vcpu, 2454 unsigned index, u64 *data)) 2455{ 2456 int i, idx; 2457 2458 idx = srcu_read_lock(&vcpu->kvm->srcu); 2459 for (i = 0; i < msrs->nmsrs; ++i) 2460 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2461 break; 2462 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2463 2464 return i; 2465} 2466 2467/* 2468 * Read or write a bunch of msrs. Parameters are user addresses. 2469 * 2470 * @return number of msrs set successfully. 2471 */ 2472static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2473 int (*do_msr)(struct kvm_vcpu *vcpu, 2474 unsigned index, u64 *data), 2475 int writeback) 2476{ 2477 struct kvm_msrs msrs; 2478 struct kvm_msr_entry *entries; 2479 int r, n; 2480 unsigned size; 2481 2482 r = -EFAULT; 2483 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2484 goto out; 2485 2486 r = -E2BIG; 2487 if (msrs.nmsrs >= MAX_IO_MSRS) 2488 goto out; 2489 2490 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2491 entries = memdup_user(user_msrs->entries, size); 2492 if (IS_ERR(entries)) { 2493 r = PTR_ERR(entries); 2494 goto out; 2495 } 2496 2497 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2498 if (r < 0) 2499 goto out_free; 2500 2501 r = -EFAULT; 2502 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2503 goto out_free; 2504 2505 r = n; 2506 2507out_free: 2508 kfree(entries); 2509out: 2510 return r; 2511} 2512 2513int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2514{ 2515 int r; 2516 2517 switch (ext) { 2518 case KVM_CAP_IRQCHIP: 2519 case KVM_CAP_HLT: 2520 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2521 case KVM_CAP_SET_TSS_ADDR: 2522 case KVM_CAP_EXT_CPUID: 2523 case KVM_CAP_EXT_EMUL_CPUID: 2524 case KVM_CAP_CLOCKSOURCE: 2525 case KVM_CAP_PIT: 2526 case KVM_CAP_NOP_IO_DELAY: 2527 case KVM_CAP_MP_STATE: 2528 case KVM_CAP_SYNC_MMU: 2529 case KVM_CAP_USER_NMI: 2530 case KVM_CAP_REINJECT_CONTROL: 2531 case KVM_CAP_IRQ_INJECT_STATUS: 2532 case KVM_CAP_IOEVENTFD: 2533 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2534 case KVM_CAP_PIT2: 2535 case KVM_CAP_PIT_STATE2: 2536 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2537 case KVM_CAP_XEN_HVM: 2538 case KVM_CAP_ADJUST_CLOCK: 2539 case KVM_CAP_VCPU_EVENTS: 2540 case KVM_CAP_HYPERV: 2541 case KVM_CAP_HYPERV_VAPIC: 2542 case KVM_CAP_HYPERV_SPIN: 2543 case KVM_CAP_PCI_SEGMENT: 2544 case KVM_CAP_DEBUGREGS: 2545 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2546 case KVM_CAP_XSAVE: 2547 case KVM_CAP_ASYNC_PF: 2548 case KVM_CAP_GET_TSC_KHZ: 2549 case KVM_CAP_KVMCLOCK_CTRL: 2550 case KVM_CAP_READONLY_MEM: 2551 case KVM_CAP_HYPERV_TIME: 2552 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2553 case KVM_CAP_TSC_DEADLINE_TIMER: 2554 case KVM_CAP_ENABLE_CAP_VM: 2555 case KVM_CAP_DISABLE_QUIRKS: 2556 case KVM_CAP_SET_BOOT_CPU_ID: 2557 case KVM_CAP_SPLIT_IRQCHIP: 2558#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2559 case KVM_CAP_ASSIGN_DEV_IRQ: 2560 case KVM_CAP_PCI_2_3: 2561#endif 2562 r = 1; 2563 break; 2564 case KVM_CAP_X86_SMM: 2565 /* SMBASE is usually relocated above 1M on modern chipsets, 2566 * and SMM handlers might indeed rely on 4G segment limits, 2567 * so do not report SMM to be available if real mode is 2568 * emulated via vm86 mode. Still, do not go to great lengths 2569 * to avoid userspace's usage of the feature, because it is a 2570 * fringe case that is not enabled except via specific settings 2571 * of the module parameters. 2572 */ 2573 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2574 break; 2575 case KVM_CAP_COALESCED_MMIO: 2576 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2577 break; 2578 case KVM_CAP_VAPIC: 2579 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2580 break; 2581 case KVM_CAP_NR_VCPUS: 2582 r = KVM_SOFT_MAX_VCPUS; 2583 break; 2584 case KVM_CAP_MAX_VCPUS: 2585 r = KVM_MAX_VCPUS; 2586 break; 2587 case KVM_CAP_NR_MEMSLOTS: 2588 r = KVM_USER_MEM_SLOTS; 2589 break; 2590 case KVM_CAP_PV_MMU: /* obsolete */ 2591 r = 0; 2592 break; 2593#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2594 case KVM_CAP_IOMMU: 2595 r = iommu_present(&pci_bus_type); 2596 break; 2597#endif 2598 case KVM_CAP_MCE: 2599 r = KVM_MAX_MCE_BANKS; 2600 break; 2601 case KVM_CAP_XCRS: 2602 r = cpu_has_xsave; 2603 break; 2604 case KVM_CAP_TSC_CONTROL: 2605 r = kvm_has_tsc_control; 2606 break; 2607 default: 2608 r = 0; 2609 break; 2610 } 2611 return r; 2612 2613} 2614 2615long kvm_arch_dev_ioctl(struct file *filp, 2616 unsigned int ioctl, unsigned long arg) 2617{ 2618 void __user *argp = (void __user *)arg; 2619 long r; 2620 2621 switch (ioctl) { 2622 case KVM_GET_MSR_INDEX_LIST: { 2623 struct kvm_msr_list __user *user_msr_list = argp; 2624 struct kvm_msr_list msr_list; 2625 unsigned n; 2626 2627 r = -EFAULT; 2628 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2629 goto out; 2630 n = msr_list.nmsrs; 2631 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2632 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2633 goto out; 2634 r = -E2BIG; 2635 if (n < msr_list.nmsrs) 2636 goto out; 2637 r = -EFAULT; 2638 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2639 num_msrs_to_save * sizeof(u32))) 2640 goto out; 2641 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2642 &emulated_msrs, 2643 num_emulated_msrs * sizeof(u32))) 2644 goto out; 2645 r = 0; 2646 break; 2647 } 2648 case KVM_GET_SUPPORTED_CPUID: 2649 case KVM_GET_EMULATED_CPUID: { 2650 struct kvm_cpuid2 __user *cpuid_arg = argp; 2651 struct kvm_cpuid2 cpuid; 2652 2653 r = -EFAULT; 2654 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2655 goto out; 2656 2657 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2658 ioctl); 2659 if (r) 2660 goto out; 2661 2662 r = -EFAULT; 2663 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2664 goto out; 2665 r = 0; 2666 break; 2667 } 2668 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2669 u64 mce_cap; 2670 2671 mce_cap = KVM_MCE_CAP_SUPPORTED; 2672 r = -EFAULT; 2673 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2674 goto out; 2675 r = 0; 2676 break; 2677 } 2678 default: 2679 r = -EINVAL; 2680 } 2681out: 2682 return r; 2683} 2684 2685static void wbinvd_ipi(void *garbage) 2686{ 2687 wbinvd(); 2688} 2689 2690static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2691{ 2692 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2693} 2694 2695void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2696{ 2697 /* Address WBINVD may be executed by guest */ 2698 if (need_emulate_wbinvd(vcpu)) { 2699 if (kvm_x86_ops->has_wbinvd_exit()) 2700 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2701 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2702 smp_call_function_single(vcpu->cpu, 2703 wbinvd_ipi, NULL, 1); 2704 } 2705 2706 kvm_x86_ops->vcpu_load(vcpu, cpu); 2707 2708 /* Apply any externally detected TSC adjustments (due to suspend) */ 2709 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2710 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2711 vcpu->arch.tsc_offset_adjustment = 0; 2712 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2713 } 2714 2715 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2716 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2717 rdtsc() - vcpu->arch.last_host_tsc; 2718 if (tsc_delta < 0) 2719 mark_tsc_unstable("KVM discovered backwards TSC"); 2720 if (check_tsc_unstable()) { 2721 u64 offset = kvm_compute_tsc_offset(vcpu, 2722 vcpu->arch.last_guest_tsc); 2723 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2724 vcpu->arch.tsc_catchup = 1; 2725 } 2726 /* 2727 * On a host with synchronized TSC, there is no need to update 2728 * kvmclock on vcpu->cpu migration 2729 */ 2730 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2731 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2732 if (vcpu->cpu != cpu) 2733 kvm_migrate_timers(vcpu); 2734 vcpu->cpu = cpu; 2735 } 2736 2737 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2738 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 2739} 2740 2741void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2742{ 2743 kvm_x86_ops->vcpu_put(vcpu); 2744 kvm_put_guest_fpu(vcpu); 2745 vcpu->arch.last_host_tsc = rdtsc(); 2746} 2747 2748static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2749 struct kvm_lapic_state *s) 2750{ 2751 kvm_x86_ops->sync_pir_to_irr(vcpu); 2752 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2753 2754 return 0; 2755} 2756 2757static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2758 struct kvm_lapic_state *s) 2759{ 2760 kvm_apic_post_state_restore(vcpu, s); 2761 update_cr8_intercept(vcpu); 2762 2763 return 0; 2764} 2765 2766static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2767{ 2768 return (!lapic_in_kernel(vcpu) || 2769 kvm_apic_accept_pic_intr(vcpu)); 2770} 2771 2772/* 2773 * if userspace requested an interrupt window, check that the 2774 * interrupt window is open. 2775 * 2776 * No need to exit to userspace if we already have an interrupt queued. 2777 */ 2778static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2779{ 2780 return kvm_arch_interrupt_allowed(vcpu) && 2781 !kvm_cpu_has_interrupt(vcpu) && 2782 !kvm_event_needs_reinjection(vcpu) && 2783 kvm_cpu_accept_dm_intr(vcpu); 2784} 2785 2786static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2787 struct kvm_interrupt *irq) 2788{ 2789 if (irq->irq >= KVM_NR_INTERRUPTS) 2790 return -EINVAL; 2791 2792 if (!irqchip_in_kernel(vcpu->kvm)) { 2793 kvm_queue_interrupt(vcpu, irq->irq, false); 2794 kvm_make_request(KVM_REQ_EVENT, vcpu); 2795 return 0; 2796 } 2797 2798 /* 2799 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2800 * fail for in-kernel 8259. 2801 */ 2802 if (pic_in_kernel(vcpu->kvm)) 2803 return -ENXIO; 2804 2805 if (vcpu->arch.pending_external_vector != -1) 2806 return -EEXIST; 2807 2808 vcpu->arch.pending_external_vector = irq->irq; 2809 kvm_make_request(KVM_REQ_EVENT, vcpu); 2810 return 0; 2811} 2812 2813static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2814{ 2815 kvm_inject_nmi(vcpu); 2816 2817 return 0; 2818} 2819 2820static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2821{ 2822 kvm_make_request(KVM_REQ_SMI, vcpu); 2823 2824 return 0; 2825} 2826 2827static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2828 struct kvm_tpr_access_ctl *tac) 2829{ 2830 if (tac->flags) 2831 return -EINVAL; 2832 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2833 return 0; 2834} 2835 2836static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2837 u64 mcg_cap) 2838{ 2839 int r; 2840 unsigned bank_num = mcg_cap & 0xff, bank; 2841 2842 r = -EINVAL; 2843 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2844 goto out; 2845 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2846 goto out; 2847 r = 0; 2848 vcpu->arch.mcg_cap = mcg_cap; 2849 /* Init IA32_MCG_CTL to all 1s */ 2850 if (mcg_cap & MCG_CTL_P) 2851 vcpu->arch.mcg_ctl = ~(u64)0; 2852 /* Init IA32_MCi_CTL to all 1s */ 2853 for (bank = 0; bank < bank_num; bank++) 2854 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2855out: 2856 return r; 2857} 2858 2859static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2860 struct kvm_x86_mce *mce) 2861{ 2862 u64 mcg_cap = vcpu->arch.mcg_cap; 2863 unsigned bank_num = mcg_cap & 0xff; 2864 u64 *banks = vcpu->arch.mce_banks; 2865 2866 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2867 return -EINVAL; 2868 /* 2869 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2870 * reporting is disabled 2871 */ 2872 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2873 vcpu->arch.mcg_ctl != ~(u64)0) 2874 return 0; 2875 banks += 4 * mce->bank; 2876 /* 2877 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2878 * reporting is disabled for the bank 2879 */ 2880 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2881 return 0; 2882 if (mce->status & MCI_STATUS_UC) { 2883 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2884 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2885 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2886 return 0; 2887 } 2888 if (banks[1] & MCI_STATUS_VAL) 2889 mce->status |= MCI_STATUS_OVER; 2890 banks[2] = mce->addr; 2891 banks[3] = mce->misc; 2892 vcpu->arch.mcg_status = mce->mcg_status; 2893 banks[1] = mce->status; 2894 kvm_queue_exception(vcpu, MC_VECTOR); 2895 } else if (!(banks[1] & MCI_STATUS_VAL) 2896 || !(banks[1] & MCI_STATUS_UC)) { 2897 if (banks[1] & MCI_STATUS_VAL) 2898 mce->status |= MCI_STATUS_OVER; 2899 banks[2] = mce->addr; 2900 banks[3] = mce->misc; 2901 banks[1] = mce->status; 2902 } else 2903 banks[1] |= MCI_STATUS_OVER; 2904 return 0; 2905} 2906 2907static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2908 struct kvm_vcpu_events *events) 2909{ 2910 process_nmi(vcpu); 2911 events->exception.injected = 2912 vcpu->arch.exception.pending && 2913 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2914 events->exception.nr = vcpu->arch.exception.nr; 2915 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2916 events->exception.pad = 0; 2917 events->exception.error_code = vcpu->arch.exception.error_code; 2918 2919 events->interrupt.injected = 2920 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2921 events->interrupt.nr = vcpu->arch.interrupt.nr; 2922 events->interrupt.soft = 0; 2923 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 2924 2925 events->nmi.injected = vcpu->arch.nmi_injected; 2926 events->nmi.pending = vcpu->arch.nmi_pending != 0; 2927 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 2928 events->nmi.pad = 0; 2929 2930 events->sipi_vector = 0; /* never valid when reporting to user space */ 2931 2932 events->smi.smm = is_smm(vcpu); 2933 events->smi.pending = vcpu->arch.smi_pending; 2934 events->smi.smm_inside_nmi = 2935 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 2936 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 2937 2938 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 2939 | KVM_VCPUEVENT_VALID_SHADOW 2940 | KVM_VCPUEVENT_VALID_SMM); 2941 memset(&events->reserved, 0, sizeof(events->reserved)); 2942} 2943 2944static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 2945 struct kvm_vcpu_events *events) 2946{ 2947 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 2948 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 2949 | KVM_VCPUEVENT_VALID_SHADOW 2950 | KVM_VCPUEVENT_VALID_SMM)) 2951 return -EINVAL; 2952 2953 process_nmi(vcpu); 2954 vcpu->arch.exception.pending = events->exception.injected; 2955 vcpu->arch.exception.nr = events->exception.nr; 2956 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 2957 vcpu->arch.exception.error_code = events->exception.error_code; 2958 2959 vcpu->arch.interrupt.pending = events->interrupt.injected; 2960 vcpu->arch.interrupt.nr = events->interrupt.nr; 2961 vcpu->arch.interrupt.soft = events->interrupt.soft; 2962 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 2963 kvm_x86_ops->set_interrupt_shadow(vcpu, 2964 events->interrupt.shadow); 2965 2966 vcpu->arch.nmi_injected = events->nmi.injected; 2967 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 2968 vcpu->arch.nmi_pending = events->nmi.pending; 2969 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 2970 2971 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 2972 kvm_vcpu_has_lapic(vcpu)) 2973 vcpu->arch.apic->sipi_vector = events->sipi_vector; 2974 2975 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 2976 if (events->smi.smm) 2977 vcpu->arch.hflags |= HF_SMM_MASK; 2978 else 2979 vcpu->arch.hflags &= ~HF_SMM_MASK; 2980 vcpu->arch.smi_pending = events->smi.pending; 2981 if (events->smi.smm_inside_nmi) 2982 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 2983 else 2984 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 2985 if (kvm_vcpu_has_lapic(vcpu)) { 2986 if (events->smi.latched_init) 2987 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 2988 else 2989 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 2990 } 2991 } 2992 2993 kvm_make_request(KVM_REQ_EVENT, vcpu); 2994 2995 return 0; 2996} 2997 2998static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 2999 struct kvm_debugregs *dbgregs) 3000{ 3001 unsigned long val; 3002 3003 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3004 kvm_get_dr(vcpu, 6, &val); 3005 dbgregs->dr6 = val; 3006 dbgregs->dr7 = vcpu->arch.dr7; 3007 dbgregs->flags = 0; 3008 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3009} 3010 3011static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3012 struct kvm_debugregs *dbgregs) 3013{ 3014 if (dbgregs->flags) 3015 return -EINVAL; 3016 3017 if (dbgregs->dr6 & ~0xffffffffull) 3018 return -EINVAL; 3019 if (dbgregs->dr7 & ~0xffffffffull) 3020 return -EINVAL; 3021 3022 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3023 kvm_update_dr0123(vcpu); 3024 vcpu->arch.dr6 = dbgregs->dr6; 3025 kvm_update_dr6(vcpu); 3026 vcpu->arch.dr7 = dbgregs->dr7; 3027 kvm_update_dr7(vcpu); 3028 3029 return 0; 3030} 3031 3032#define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3033 3034static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3035{ 3036 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3037 u64 xstate_bv = xsave->header.xfeatures; 3038 u64 valid; 3039 3040 /* 3041 * Copy legacy XSAVE area, to avoid complications with CPUID 3042 * leaves 0 and 1 in the loop below. 3043 */ 3044 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3045 3046 /* Set XSTATE_BV */ 3047 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3048 3049 /* 3050 * Copy each region from the possibly compacted offset to the 3051 * non-compacted offset. 3052 */ 3053 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3054 while (valid) { 3055 u64 feature = valid & -valid; 3056 int index = fls64(feature) - 1; 3057 void *src = get_xsave_addr(xsave, feature); 3058 3059 if (src) { 3060 u32 size, offset, ecx, edx; 3061 cpuid_count(XSTATE_CPUID, index, 3062 &size, &offset, &ecx, &edx); 3063 memcpy(dest + offset, src, size); 3064 } 3065 3066 valid -= feature; 3067 } 3068} 3069 3070static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3071{ 3072 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3073 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3074 u64 valid; 3075 3076 /* 3077 * Copy legacy XSAVE area, to avoid complications with CPUID 3078 * leaves 0 and 1 in the loop below. 3079 */ 3080 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3081 3082 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3083 xsave->header.xfeatures = xstate_bv; 3084 if (cpu_has_xsaves) 3085 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3086 3087 /* 3088 * Copy each region from the non-compacted offset to the 3089 * possibly compacted offset. 3090 */ 3091 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3092 while (valid) { 3093 u64 feature = valid & -valid; 3094 int index = fls64(feature) - 1; 3095 void *dest = get_xsave_addr(xsave, feature); 3096 3097 if (dest) { 3098 u32 size, offset, ecx, edx; 3099 cpuid_count(XSTATE_CPUID, index, 3100 &size, &offset, &ecx, &edx); 3101 memcpy(dest, src + offset, size); 3102 } 3103 3104 valid -= feature; 3105 } 3106} 3107 3108static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3109 struct kvm_xsave *guest_xsave) 3110{ 3111 if (cpu_has_xsave) { 3112 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3113 fill_xsave((u8 *) guest_xsave->region, vcpu); 3114 } else { 3115 memcpy(guest_xsave->region, 3116 &vcpu->arch.guest_fpu.state.fxsave, 3117 sizeof(struct fxregs_state)); 3118 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3119 XFEATURE_MASK_FPSSE; 3120 } 3121} 3122 3123static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3124 struct kvm_xsave *guest_xsave) 3125{ 3126 u64 xstate_bv = 3127 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3128 3129 if (cpu_has_xsave) { 3130 /* 3131 * Here we allow setting states that are not present in 3132 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3133 * with old userspace. 3134 */ 3135 if (xstate_bv & ~kvm_supported_xcr0()) 3136 return -EINVAL; 3137 load_xsave(vcpu, (u8 *)guest_xsave->region); 3138 } else { 3139 if (xstate_bv & ~XFEATURE_MASK_FPSSE) 3140 return -EINVAL; 3141 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3142 guest_xsave->region, sizeof(struct fxregs_state)); 3143 } 3144 return 0; 3145} 3146 3147static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3148 struct kvm_xcrs *guest_xcrs) 3149{ 3150 if (!cpu_has_xsave) { 3151 guest_xcrs->nr_xcrs = 0; 3152 return; 3153 } 3154 3155 guest_xcrs->nr_xcrs = 1; 3156 guest_xcrs->flags = 0; 3157 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3158 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3159} 3160 3161static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3162 struct kvm_xcrs *guest_xcrs) 3163{ 3164 int i, r = 0; 3165 3166 if (!cpu_has_xsave) 3167 return -EINVAL; 3168 3169 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3170 return -EINVAL; 3171 3172 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3173 /* Only support XCR0 currently */ 3174 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3175 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3176 guest_xcrs->xcrs[i].value); 3177 break; 3178 } 3179 if (r) 3180 r = -EINVAL; 3181 return r; 3182} 3183 3184/* 3185 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3186 * stopped by the hypervisor. This function will be called from the host only. 3187 * EINVAL is returned when the host attempts to set the flag for a guest that 3188 * does not support pv clocks. 3189 */ 3190static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3191{ 3192 if (!vcpu->arch.pv_time_enabled) 3193 return -EINVAL; 3194 vcpu->arch.pvclock_set_guest_stopped_request = true; 3195 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3196 return 0; 3197} 3198 3199long kvm_arch_vcpu_ioctl(struct file *filp, 3200 unsigned int ioctl, unsigned long arg) 3201{ 3202 struct kvm_vcpu *vcpu = filp->private_data; 3203 void __user *argp = (void __user *)arg; 3204 int r; 3205 union { 3206 struct kvm_lapic_state *lapic; 3207 struct kvm_xsave *xsave; 3208 struct kvm_xcrs *xcrs; 3209 void *buffer; 3210 } u; 3211 3212 u.buffer = NULL; 3213 switch (ioctl) { 3214 case KVM_GET_LAPIC: { 3215 r = -EINVAL; 3216 if (!vcpu->arch.apic) 3217 goto out; 3218 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3219 3220 r = -ENOMEM; 3221 if (!u.lapic) 3222 goto out; 3223 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3224 if (r) 3225 goto out; 3226 r = -EFAULT; 3227 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3228 goto out; 3229 r = 0; 3230 break; 3231 } 3232 case KVM_SET_LAPIC: { 3233 r = -EINVAL; 3234 if (!vcpu->arch.apic) 3235 goto out; 3236 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3237 if (IS_ERR(u.lapic)) 3238 return PTR_ERR(u.lapic); 3239 3240 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3241 break; 3242 } 3243 case KVM_INTERRUPT: { 3244 struct kvm_interrupt irq; 3245 3246 r = -EFAULT; 3247 if (copy_from_user(&irq, argp, sizeof irq)) 3248 goto out; 3249 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3250 break; 3251 } 3252 case KVM_NMI: { 3253 r = kvm_vcpu_ioctl_nmi(vcpu); 3254 break; 3255 } 3256 case KVM_SMI: { 3257 r = kvm_vcpu_ioctl_smi(vcpu); 3258 break; 3259 } 3260 case KVM_SET_CPUID: { 3261 struct kvm_cpuid __user *cpuid_arg = argp; 3262 struct kvm_cpuid cpuid; 3263 3264 r = -EFAULT; 3265 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3266 goto out; 3267 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3268 break; 3269 } 3270 case KVM_SET_CPUID2: { 3271 struct kvm_cpuid2 __user *cpuid_arg = argp; 3272 struct kvm_cpuid2 cpuid; 3273 3274 r = -EFAULT; 3275 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3276 goto out; 3277 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3278 cpuid_arg->entries); 3279 break; 3280 } 3281 case KVM_GET_CPUID2: { 3282 struct kvm_cpuid2 __user *cpuid_arg = argp; 3283 struct kvm_cpuid2 cpuid; 3284 3285 r = -EFAULT; 3286 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3287 goto out; 3288 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3289 cpuid_arg->entries); 3290 if (r) 3291 goto out; 3292 r = -EFAULT; 3293 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3294 goto out; 3295 r = 0; 3296 break; 3297 } 3298 case KVM_GET_MSRS: 3299 r = msr_io(vcpu, argp, do_get_msr, 1); 3300 break; 3301 case KVM_SET_MSRS: 3302 r = msr_io(vcpu, argp, do_set_msr, 0); 3303 break; 3304 case KVM_TPR_ACCESS_REPORTING: { 3305 struct kvm_tpr_access_ctl tac; 3306 3307 r = -EFAULT; 3308 if (copy_from_user(&tac, argp, sizeof tac)) 3309 goto out; 3310 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3311 if (r) 3312 goto out; 3313 r = -EFAULT; 3314 if (copy_to_user(argp, &tac, sizeof tac)) 3315 goto out; 3316 r = 0; 3317 break; 3318 }; 3319 case KVM_SET_VAPIC_ADDR: { 3320 struct kvm_vapic_addr va; 3321 3322 r = -EINVAL; 3323 if (!lapic_in_kernel(vcpu)) 3324 goto out; 3325 r = -EFAULT; 3326 if (copy_from_user(&va, argp, sizeof va)) 3327 goto out; 3328 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3329 break; 3330 } 3331 case KVM_X86_SETUP_MCE: { 3332 u64 mcg_cap; 3333 3334 r = -EFAULT; 3335 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3336 goto out; 3337 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3338 break; 3339 } 3340 case KVM_X86_SET_MCE: { 3341 struct kvm_x86_mce mce; 3342 3343 r = -EFAULT; 3344 if (copy_from_user(&mce, argp, sizeof mce)) 3345 goto out; 3346 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3347 break; 3348 } 3349 case KVM_GET_VCPU_EVENTS: { 3350 struct kvm_vcpu_events events; 3351 3352 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3353 3354 r = -EFAULT; 3355 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3356 break; 3357 r = 0; 3358 break; 3359 } 3360 case KVM_SET_VCPU_EVENTS: { 3361 struct kvm_vcpu_events events; 3362 3363 r = -EFAULT; 3364 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3365 break; 3366 3367 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3368 break; 3369 } 3370 case KVM_GET_DEBUGREGS: { 3371 struct kvm_debugregs dbgregs; 3372 3373 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3374 3375 r = -EFAULT; 3376 if (copy_to_user(argp, &dbgregs, 3377 sizeof(struct kvm_debugregs))) 3378 break; 3379 r = 0; 3380 break; 3381 } 3382 case KVM_SET_DEBUGREGS: { 3383 struct kvm_debugregs dbgregs; 3384 3385 r = -EFAULT; 3386 if (copy_from_user(&dbgregs, argp, 3387 sizeof(struct kvm_debugregs))) 3388 break; 3389 3390 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3391 break; 3392 } 3393 case KVM_GET_XSAVE: { 3394 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3395 r = -ENOMEM; 3396 if (!u.xsave) 3397 break; 3398 3399 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3400 3401 r = -EFAULT; 3402 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3403 break; 3404 r = 0; 3405 break; 3406 } 3407 case KVM_SET_XSAVE: { 3408 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3409 if (IS_ERR(u.xsave)) 3410 return PTR_ERR(u.xsave); 3411 3412 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3413 break; 3414 } 3415 case KVM_GET_XCRS: { 3416 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3417 r = -ENOMEM; 3418 if (!u.xcrs) 3419 break; 3420 3421 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3422 3423 r = -EFAULT; 3424 if (copy_to_user(argp, u.xcrs, 3425 sizeof(struct kvm_xcrs))) 3426 break; 3427 r = 0; 3428 break; 3429 } 3430 case KVM_SET_XCRS: { 3431 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3432 if (IS_ERR(u.xcrs)) 3433 return PTR_ERR(u.xcrs); 3434 3435 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3436 break; 3437 } 3438 case KVM_SET_TSC_KHZ: { 3439 u32 user_tsc_khz; 3440 3441 r = -EINVAL; 3442 user_tsc_khz = (u32)arg; 3443 3444 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3445 goto out; 3446 3447 if (user_tsc_khz == 0) 3448 user_tsc_khz = tsc_khz; 3449 3450 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3451 r = 0; 3452 3453 goto out; 3454 } 3455 case KVM_GET_TSC_KHZ: { 3456 r = vcpu->arch.virtual_tsc_khz; 3457 goto out; 3458 } 3459 case KVM_KVMCLOCK_CTRL: { 3460 r = kvm_set_guest_paused(vcpu); 3461 goto out; 3462 } 3463 default: 3464 r = -EINVAL; 3465 } 3466out: 3467 kfree(u.buffer); 3468 return r; 3469} 3470 3471int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3472{ 3473 return VM_FAULT_SIGBUS; 3474} 3475 3476static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3477{ 3478 int ret; 3479 3480 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3481 return -EINVAL; 3482 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3483 return ret; 3484} 3485 3486static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3487 u64 ident_addr) 3488{ 3489 kvm->arch.ept_identity_map_addr = ident_addr; 3490 return 0; 3491} 3492 3493static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3494 u32 kvm_nr_mmu_pages) 3495{ 3496 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3497 return -EINVAL; 3498 3499 mutex_lock(&kvm->slots_lock); 3500 3501 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3502 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3503 3504 mutex_unlock(&kvm->slots_lock); 3505 return 0; 3506} 3507 3508static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3509{ 3510 return kvm->arch.n_max_mmu_pages; 3511} 3512 3513static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3514{ 3515 int r; 3516 3517 r = 0; 3518 switch (chip->chip_id) { 3519 case KVM_IRQCHIP_PIC_MASTER: 3520 memcpy(&chip->chip.pic, 3521 &pic_irqchip(kvm)->pics[0], 3522 sizeof(struct kvm_pic_state)); 3523 break; 3524 case KVM_IRQCHIP_PIC_SLAVE: 3525 memcpy(&chip->chip.pic, 3526 &pic_irqchip(kvm)->pics[1], 3527 sizeof(struct kvm_pic_state)); 3528 break; 3529 case KVM_IRQCHIP_IOAPIC: 3530 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3531 break; 3532 default: 3533 r = -EINVAL; 3534 break; 3535 } 3536 return r; 3537} 3538 3539static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3540{ 3541 int r; 3542 3543 r = 0; 3544 switch (chip->chip_id) { 3545 case KVM_IRQCHIP_PIC_MASTER: 3546 spin_lock(&pic_irqchip(kvm)->lock); 3547 memcpy(&pic_irqchip(kvm)->pics[0], 3548 &chip->chip.pic, 3549 sizeof(struct kvm_pic_state)); 3550 spin_unlock(&pic_irqchip(kvm)->lock); 3551 break; 3552 case KVM_IRQCHIP_PIC_SLAVE: 3553 spin_lock(&pic_irqchip(kvm)->lock); 3554 memcpy(&pic_irqchip(kvm)->pics[1], 3555 &chip->chip.pic, 3556 sizeof(struct kvm_pic_state)); 3557 spin_unlock(&pic_irqchip(kvm)->lock); 3558 break; 3559 case KVM_IRQCHIP_IOAPIC: 3560 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3561 break; 3562 default: 3563 r = -EINVAL; 3564 break; 3565 } 3566 kvm_pic_update_irq(pic_irqchip(kvm)); 3567 return r; 3568} 3569 3570static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3571{ 3572 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3573 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3574 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3575 return 0; 3576} 3577 3578static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3579{ 3580 int i; 3581 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3582 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3583 for (i = 0; i < 3; i++) 3584 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0); 3585 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3586 return 0; 3587} 3588 3589static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3590{ 3591 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3592 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3593 sizeof(ps->channels)); 3594 ps->flags = kvm->arch.vpit->pit_state.flags; 3595 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3596 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3597 return 0; 3598} 3599 3600static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3601{ 3602 int start = 0; 3603 int i; 3604 u32 prev_legacy, cur_legacy; 3605 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3606 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3607 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3608 if (!prev_legacy && cur_legacy) 3609 start = 1; 3610 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3611 sizeof(kvm->arch.vpit->pit_state.channels)); 3612 kvm->arch.vpit->pit_state.flags = ps->flags; 3613 for (i = 0; i < 3; i++) 3614 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count, 3615 start && i == 0); 3616 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3617 return 0; 3618} 3619 3620static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3621 struct kvm_reinject_control *control) 3622{ 3623 if (!kvm->arch.vpit) 3624 return -ENXIO; 3625 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3626 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3627 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3628 return 0; 3629} 3630 3631/** 3632 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3633 * @kvm: kvm instance 3634 * @log: slot id and address to which we copy the log 3635 * 3636 * Steps 1-4 below provide general overview of dirty page logging. See 3637 * kvm_get_dirty_log_protect() function description for additional details. 3638 * 3639 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3640 * always flush the TLB (step 4) even if previous step failed and the dirty 3641 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3642 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3643 * writes will be marked dirty for next log read. 3644 * 3645 * 1. Take a snapshot of the bit and clear it if needed. 3646 * 2. Write protect the corresponding page. 3647 * 3. Copy the snapshot to the userspace. 3648 * 4. Flush TLB's if needed. 3649 */ 3650int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3651{ 3652 bool is_dirty = false; 3653 int r; 3654 3655 mutex_lock(&kvm->slots_lock); 3656 3657 /* 3658 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3659 */ 3660 if (kvm_x86_ops->flush_log_dirty) 3661 kvm_x86_ops->flush_log_dirty(kvm); 3662 3663 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3664 3665 /* 3666 * All the TLBs can be flushed out of mmu lock, see the comments in 3667 * kvm_mmu_slot_remove_write_access(). 3668 */ 3669 lockdep_assert_held(&kvm->slots_lock); 3670 if (is_dirty) 3671 kvm_flush_remote_tlbs(kvm); 3672 3673 mutex_unlock(&kvm->slots_lock); 3674 return r; 3675} 3676 3677int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3678 bool line_status) 3679{ 3680 if (!irqchip_in_kernel(kvm)) 3681 return -ENXIO; 3682 3683 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3684 irq_event->irq, irq_event->level, 3685 line_status); 3686 return 0; 3687} 3688 3689static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3690 struct kvm_enable_cap *cap) 3691{ 3692 int r; 3693 3694 if (cap->flags) 3695 return -EINVAL; 3696 3697 switch (cap->cap) { 3698 case KVM_CAP_DISABLE_QUIRKS: 3699 kvm->arch.disabled_quirks = cap->args[0]; 3700 r = 0; 3701 break; 3702 case KVM_CAP_SPLIT_IRQCHIP: { 3703 mutex_lock(&kvm->lock); 3704 r = -EINVAL; 3705 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3706 goto split_irqchip_unlock; 3707 r = -EEXIST; 3708 if (irqchip_in_kernel(kvm)) 3709 goto split_irqchip_unlock; 3710 if (atomic_read(&kvm->online_vcpus)) 3711 goto split_irqchip_unlock; 3712 r = kvm_setup_empty_irq_routing(kvm); 3713 if (r) 3714 goto split_irqchip_unlock; 3715 /* Pairs with irqchip_in_kernel. */ 3716 smp_wmb(); 3717 kvm->arch.irqchip_split = true; 3718 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 3719 r = 0; 3720split_irqchip_unlock: 3721 mutex_unlock(&kvm->lock); 3722 break; 3723 } 3724 default: 3725 r = -EINVAL; 3726 break; 3727 } 3728 return r; 3729} 3730 3731long kvm_arch_vm_ioctl(struct file *filp, 3732 unsigned int ioctl, unsigned long arg) 3733{ 3734 struct kvm *kvm = filp->private_data; 3735 void __user *argp = (void __user *)arg; 3736 int r = -ENOTTY; 3737 /* 3738 * This union makes it completely explicit to gcc-3.x 3739 * that these two variables' stack usage should be 3740 * combined, not added together. 3741 */ 3742 union { 3743 struct kvm_pit_state ps; 3744 struct kvm_pit_state2 ps2; 3745 struct kvm_pit_config pit_config; 3746 } u; 3747 3748 switch (ioctl) { 3749 case KVM_SET_TSS_ADDR: 3750 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3751 break; 3752 case KVM_SET_IDENTITY_MAP_ADDR: { 3753 u64 ident_addr; 3754 3755 r = -EFAULT; 3756 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3757 goto out; 3758 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3759 break; 3760 } 3761 case KVM_SET_NR_MMU_PAGES: 3762 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3763 break; 3764 case KVM_GET_NR_MMU_PAGES: 3765 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3766 break; 3767 case KVM_CREATE_IRQCHIP: { 3768 struct kvm_pic *vpic; 3769 3770 mutex_lock(&kvm->lock); 3771 r = -EEXIST; 3772 if (kvm->arch.vpic) 3773 goto create_irqchip_unlock; 3774 r = -EINVAL; 3775 if (atomic_read(&kvm->online_vcpus)) 3776 goto create_irqchip_unlock; 3777 r = -ENOMEM; 3778 vpic = kvm_create_pic(kvm); 3779 if (vpic) { 3780 r = kvm_ioapic_init(kvm); 3781 if (r) { 3782 mutex_lock(&kvm->slots_lock); 3783 kvm_destroy_pic(vpic); 3784 mutex_unlock(&kvm->slots_lock); 3785 goto create_irqchip_unlock; 3786 } 3787 } else 3788 goto create_irqchip_unlock; 3789 r = kvm_setup_default_irq_routing(kvm); 3790 if (r) { 3791 mutex_lock(&kvm->slots_lock); 3792 mutex_lock(&kvm->irq_lock); 3793 kvm_ioapic_destroy(kvm); 3794 kvm_destroy_pic(vpic); 3795 mutex_unlock(&kvm->irq_lock); 3796 mutex_unlock(&kvm->slots_lock); 3797 goto create_irqchip_unlock; 3798 } 3799 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3800 smp_wmb(); 3801 kvm->arch.vpic = vpic; 3802 create_irqchip_unlock: 3803 mutex_unlock(&kvm->lock); 3804 break; 3805 } 3806 case KVM_CREATE_PIT: 3807 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3808 goto create_pit; 3809 case KVM_CREATE_PIT2: 3810 r = -EFAULT; 3811 if (copy_from_user(&u.pit_config, argp, 3812 sizeof(struct kvm_pit_config))) 3813 goto out; 3814 create_pit: 3815 mutex_lock(&kvm->slots_lock); 3816 r = -EEXIST; 3817 if (kvm->arch.vpit) 3818 goto create_pit_unlock; 3819 r = -ENOMEM; 3820 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3821 if (kvm->arch.vpit) 3822 r = 0; 3823 create_pit_unlock: 3824 mutex_unlock(&kvm->slots_lock); 3825 break; 3826 case KVM_GET_IRQCHIP: { 3827 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3828 struct kvm_irqchip *chip; 3829 3830 chip = memdup_user(argp, sizeof(*chip)); 3831 if (IS_ERR(chip)) { 3832 r = PTR_ERR(chip); 3833 goto out; 3834 } 3835 3836 r = -ENXIO; 3837 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3838 goto get_irqchip_out; 3839 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3840 if (r) 3841 goto get_irqchip_out; 3842 r = -EFAULT; 3843 if (copy_to_user(argp, chip, sizeof *chip)) 3844 goto get_irqchip_out; 3845 r = 0; 3846 get_irqchip_out: 3847 kfree(chip); 3848 break; 3849 } 3850 case KVM_SET_IRQCHIP: { 3851 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3852 struct kvm_irqchip *chip; 3853 3854 chip = memdup_user(argp, sizeof(*chip)); 3855 if (IS_ERR(chip)) { 3856 r = PTR_ERR(chip); 3857 goto out; 3858 } 3859 3860 r = -ENXIO; 3861 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3862 goto set_irqchip_out; 3863 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3864 if (r) 3865 goto set_irqchip_out; 3866 r = 0; 3867 set_irqchip_out: 3868 kfree(chip); 3869 break; 3870 } 3871 case KVM_GET_PIT: { 3872 r = -EFAULT; 3873 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3874 goto out; 3875 r = -ENXIO; 3876 if (!kvm->arch.vpit) 3877 goto out; 3878 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3879 if (r) 3880 goto out; 3881 r = -EFAULT; 3882 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3883 goto out; 3884 r = 0; 3885 break; 3886 } 3887 case KVM_SET_PIT: { 3888 r = -EFAULT; 3889 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3890 goto out; 3891 r = -ENXIO; 3892 if (!kvm->arch.vpit) 3893 goto out; 3894 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3895 break; 3896 } 3897 case KVM_GET_PIT2: { 3898 r = -ENXIO; 3899 if (!kvm->arch.vpit) 3900 goto out; 3901 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3902 if (r) 3903 goto out; 3904 r = -EFAULT; 3905 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3906 goto out; 3907 r = 0; 3908 break; 3909 } 3910 case KVM_SET_PIT2: { 3911 r = -EFAULT; 3912 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3913 goto out; 3914 r = -ENXIO; 3915 if (!kvm->arch.vpit) 3916 goto out; 3917 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3918 break; 3919 } 3920 case KVM_REINJECT_CONTROL: { 3921 struct kvm_reinject_control control; 3922 r = -EFAULT; 3923 if (copy_from_user(&control, argp, sizeof(control))) 3924 goto out; 3925 r = kvm_vm_ioctl_reinject(kvm, &control); 3926 break; 3927 } 3928 case KVM_SET_BOOT_CPU_ID: 3929 r = 0; 3930 mutex_lock(&kvm->lock); 3931 if (atomic_read(&kvm->online_vcpus) != 0) 3932 r = -EBUSY; 3933 else 3934 kvm->arch.bsp_vcpu_id = arg; 3935 mutex_unlock(&kvm->lock); 3936 break; 3937 case KVM_XEN_HVM_CONFIG: { 3938 r = -EFAULT; 3939 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 3940 sizeof(struct kvm_xen_hvm_config))) 3941 goto out; 3942 r = -EINVAL; 3943 if (kvm->arch.xen_hvm_config.flags) 3944 goto out; 3945 r = 0; 3946 break; 3947 } 3948 case KVM_SET_CLOCK: { 3949 struct kvm_clock_data user_ns; 3950 u64 now_ns; 3951 s64 delta; 3952 3953 r = -EFAULT; 3954 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 3955 goto out; 3956 3957 r = -EINVAL; 3958 if (user_ns.flags) 3959 goto out; 3960 3961 r = 0; 3962 local_irq_disable(); 3963 now_ns = get_kernel_ns(); 3964 delta = user_ns.clock - now_ns; 3965 local_irq_enable(); 3966 kvm->arch.kvmclock_offset = delta; 3967 kvm_gen_update_masterclock(kvm); 3968 break; 3969 } 3970 case KVM_GET_CLOCK: { 3971 struct kvm_clock_data user_ns; 3972 u64 now_ns; 3973 3974 local_irq_disable(); 3975 now_ns = get_kernel_ns(); 3976 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 3977 local_irq_enable(); 3978 user_ns.flags = 0; 3979 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 3980 3981 r = -EFAULT; 3982 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 3983 goto out; 3984 r = 0; 3985 break; 3986 } 3987 case KVM_ENABLE_CAP: { 3988 struct kvm_enable_cap cap; 3989 3990 r = -EFAULT; 3991 if (copy_from_user(&cap, argp, sizeof(cap))) 3992 goto out; 3993 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 3994 break; 3995 } 3996 default: 3997 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 3998 } 3999out: 4000 return r; 4001} 4002 4003static void kvm_init_msr_list(void) 4004{ 4005 u32 dummy[2]; 4006 unsigned i, j; 4007 4008 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4009 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4010 continue; 4011 4012 /* 4013 * Even MSRs that are valid in the host may not be exposed 4014 * to the guests in some cases. 4015 */ 4016 switch (msrs_to_save[i]) { 4017 case MSR_IA32_BNDCFGS: 4018 if (!kvm_x86_ops->mpx_supported()) 4019 continue; 4020 break; 4021 case MSR_TSC_AUX: 4022 if (!kvm_x86_ops->rdtscp_supported()) 4023 continue; 4024 break; 4025 default: 4026 break; 4027 } 4028 4029 if (j < i) 4030 msrs_to_save[j] = msrs_to_save[i]; 4031 j++; 4032 } 4033 num_msrs_to_save = j; 4034 4035 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4036 switch (emulated_msrs[i]) { 4037 case MSR_IA32_SMBASE: 4038 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4039 continue; 4040 break; 4041 default: 4042 break; 4043 } 4044 4045 if (j < i) 4046 emulated_msrs[j] = emulated_msrs[i]; 4047 j++; 4048 } 4049 num_emulated_msrs = j; 4050} 4051 4052static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4053 const void *v) 4054{ 4055 int handled = 0; 4056 int n; 4057 4058 do { 4059 n = min(len, 8); 4060 if (!(vcpu->arch.apic && 4061 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4062 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4063 break; 4064 handled += n; 4065 addr += n; 4066 len -= n; 4067 v += n; 4068 } while (len); 4069 4070 return handled; 4071} 4072 4073static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4074{ 4075 int handled = 0; 4076 int n; 4077 4078 do { 4079 n = min(len, 8); 4080 if (!(vcpu->arch.apic && 4081 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4082 addr, n, v)) 4083 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4084 break; 4085 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4086 handled += n; 4087 addr += n; 4088 len -= n; 4089 v += n; 4090 } while (len); 4091 4092 return handled; 4093} 4094 4095static void kvm_set_segment(struct kvm_vcpu *vcpu, 4096 struct kvm_segment *var, int seg) 4097{ 4098 kvm_x86_ops->set_segment(vcpu, var, seg); 4099} 4100 4101void kvm_get_segment(struct kvm_vcpu *vcpu, 4102 struct kvm_segment *var, int seg) 4103{ 4104 kvm_x86_ops->get_segment(vcpu, var, seg); 4105} 4106 4107gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4108 struct x86_exception *exception) 4109{ 4110 gpa_t t_gpa; 4111 4112 BUG_ON(!mmu_is_nested(vcpu)); 4113 4114 /* NPT walks are always user-walks */ 4115 access |= PFERR_USER_MASK; 4116 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4117 4118 return t_gpa; 4119} 4120 4121gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4122 struct x86_exception *exception) 4123{ 4124 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4125 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4126} 4127 4128 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4129 struct x86_exception *exception) 4130{ 4131 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4132 access |= PFERR_FETCH_MASK; 4133 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4134} 4135 4136gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4137 struct x86_exception *exception) 4138{ 4139 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4140 access |= PFERR_WRITE_MASK; 4141 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4142} 4143 4144/* uses this to access any guest's mapped memory without checking CPL */ 4145gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4146 struct x86_exception *exception) 4147{ 4148 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4149} 4150 4151static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4152 struct kvm_vcpu *vcpu, u32 access, 4153 struct x86_exception *exception) 4154{ 4155 void *data = val; 4156 int r = X86EMUL_CONTINUE; 4157 4158 while (bytes) { 4159 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4160 exception); 4161 unsigned offset = addr & (PAGE_SIZE-1); 4162 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4163 int ret; 4164 4165 if (gpa == UNMAPPED_GVA) 4166 return X86EMUL_PROPAGATE_FAULT; 4167 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4168 offset, toread); 4169 if (ret < 0) { 4170 r = X86EMUL_IO_NEEDED; 4171 goto out; 4172 } 4173 4174 bytes -= toread; 4175 data += toread; 4176 addr += toread; 4177 } 4178out: 4179 return r; 4180} 4181 4182/* used for instruction fetching */ 4183static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4184 gva_t addr, void *val, unsigned int bytes, 4185 struct x86_exception *exception) 4186{ 4187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4188 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4189 unsigned offset; 4190 int ret; 4191 4192 /* Inline kvm_read_guest_virt_helper for speed. */ 4193 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4194 exception); 4195 if (unlikely(gpa == UNMAPPED_GVA)) 4196 return X86EMUL_PROPAGATE_FAULT; 4197 4198 offset = addr & (PAGE_SIZE-1); 4199 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4200 bytes = (unsigned)PAGE_SIZE - offset; 4201 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4202 offset, bytes); 4203 if (unlikely(ret < 0)) 4204 return X86EMUL_IO_NEEDED; 4205 4206 return X86EMUL_CONTINUE; 4207} 4208 4209int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4210 gva_t addr, void *val, unsigned int bytes, 4211 struct x86_exception *exception) 4212{ 4213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4214 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4215 4216 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4217 exception); 4218} 4219EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4220 4221static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4222 gva_t addr, void *val, unsigned int bytes, 4223 struct x86_exception *exception) 4224{ 4225 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4226 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4227} 4228 4229static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4230 unsigned long addr, void *val, unsigned int bytes) 4231{ 4232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4233 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4234 4235 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4236} 4237 4238int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4239 gva_t addr, void *val, 4240 unsigned int bytes, 4241 struct x86_exception *exception) 4242{ 4243 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4244 void *data = val; 4245 int r = X86EMUL_CONTINUE; 4246 4247 while (bytes) { 4248 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4249 PFERR_WRITE_MASK, 4250 exception); 4251 unsigned offset = addr & (PAGE_SIZE-1); 4252 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4253 int ret; 4254 4255 if (gpa == UNMAPPED_GVA) 4256 return X86EMUL_PROPAGATE_FAULT; 4257 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4258 if (ret < 0) { 4259 r = X86EMUL_IO_NEEDED; 4260 goto out; 4261 } 4262 4263 bytes -= towrite; 4264 data += towrite; 4265 addr += towrite; 4266 } 4267out: 4268 return r; 4269} 4270EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4271 4272static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4273 gpa_t *gpa, struct x86_exception *exception, 4274 bool write) 4275{ 4276 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4277 | (write ? PFERR_WRITE_MASK : 0); 4278 4279 if (vcpu_match_mmio_gva(vcpu, gva) 4280 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4281 vcpu->arch.access, access)) { 4282 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4283 (gva & (PAGE_SIZE - 1)); 4284 trace_vcpu_match_mmio(gva, *gpa, write, false); 4285 return 1; 4286 } 4287 4288 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4289 4290 if (*gpa == UNMAPPED_GVA) 4291 return -1; 4292 4293 /* For APIC access vmexit */ 4294 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4295 return 1; 4296 4297 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4298 trace_vcpu_match_mmio(gva, *gpa, write, true); 4299 return 1; 4300 } 4301 4302 return 0; 4303} 4304 4305int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4306 const void *val, int bytes) 4307{ 4308 int ret; 4309 4310 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4311 if (ret < 0) 4312 return 0; 4313 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4314 return 1; 4315} 4316 4317struct read_write_emulator_ops { 4318 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4319 int bytes); 4320 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4321 void *val, int bytes); 4322 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4323 int bytes, void *val); 4324 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4325 void *val, int bytes); 4326 bool write; 4327}; 4328 4329static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4330{ 4331 if (vcpu->mmio_read_completed) { 4332 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4333 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4334 vcpu->mmio_read_completed = 0; 4335 return 1; 4336 } 4337 4338 return 0; 4339} 4340 4341static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4342 void *val, int bytes) 4343{ 4344 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4345} 4346 4347static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4348 void *val, int bytes) 4349{ 4350 return emulator_write_phys(vcpu, gpa, val, bytes); 4351} 4352 4353static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4354{ 4355 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4356 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4357} 4358 4359static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4360 void *val, int bytes) 4361{ 4362 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4363 return X86EMUL_IO_NEEDED; 4364} 4365 4366static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4367 void *val, int bytes) 4368{ 4369 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4370 4371 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4372 return X86EMUL_CONTINUE; 4373} 4374 4375static const struct read_write_emulator_ops read_emultor = { 4376 .read_write_prepare = read_prepare, 4377 .read_write_emulate = read_emulate, 4378 .read_write_mmio = vcpu_mmio_read, 4379 .read_write_exit_mmio = read_exit_mmio, 4380}; 4381 4382static const struct read_write_emulator_ops write_emultor = { 4383 .read_write_emulate = write_emulate, 4384 .read_write_mmio = write_mmio, 4385 .read_write_exit_mmio = write_exit_mmio, 4386 .write = true, 4387}; 4388 4389static int emulator_read_write_onepage(unsigned long addr, void *val, 4390 unsigned int bytes, 4391 struct x86_exception *exception, 4392 struct kvm_vcpu *vcpu, 4393 const struct read_write_emulator_ops *ops) 4394{ 4395 gpa_t gpa; 4396 int handled, ret; 4397 bool write = ops->write; 4398 struct kvm_mmio_fragment *frag; 4399 4400 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4401 4402 if (ret < 0) 4403 return X86EMUL_PROPAGATE_FAULT; 4404 4405 /* For APIC access vmexit */ 4406 if (ret) 4407 goto mmio; 4408 4409 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4410 return X86EMUL_CONTINUE; 4411 4412mmio: 4413 /* 4414 * Is this MMIO handled locally? 4415 */ 4416 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4417 if (handled == bytes) 4418 return X86EMUL_CONTINUE; 4419 4420 gpa += handled; 4421 bytes -= handled; 4422 val += handled; 4423 4424 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4425 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4426 frag->gpa = gpa; 4427 frag->data = val; 4428 frag->len = bytes; 4429 return X86EMUL_CONTINUE; 4430} 4431 4432static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4433 unsigned long addr, 4434 void *val, unsigned int bytes, 4435 struct x86_exception *exception, 4436 const struct read_write_emulator_ops *ops) 4437{ 4438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4439 gpa_t gpa; 4440 int rc; 4441 4442 if (ops->read_write_prepare && 4443 ops->read_write_prepare(vcpu, val, bytes)) 4444 return X86EMUL_CONTINUE; 4445 4446 vcpu->mmio_nr_fragments = 0; 4447 4448 /* Crossing a page boundary? */ 4449 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4450 int now; 4451 4452 now = -addr & ~PAGE_MASK; 4453 rc = emulator_read_write_onepage(addr, val, now, exception, 4454 vcpu, ops); 4455 4456 if (rc != X86EMUL_CONTINUE) 4457 return rc; 4458 addr += now; 4459 if (ctxt->mode != X86EMUL_MODE_PROT64) 4460 addr = (u32)addr; 4461 val += now; 4462 bytes -= now; 4463 } 4464 4465 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4466 vcpu, ops); 4467 if (rc != X86EMUL_CONTINUE) 4468 return rc; 4469 4470 if (!vcpu->mmio_nr_fragments) 4471 return rc; 4472 4473 gpa = vcpu->mmio_fragments[0].gpa; 4474 4475 vcpu->mmio_needed = 1; 4476 vcpu->mmio_cur_fragment = 0; 4477 4478 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4479 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4480 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4481 vcpu->run->mmio.phys_addr = gpa; 4482 4483 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4484} 4485 4486static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4487 unsigned long addr, 4488 void *val, 4489 unsigned int bytes, 4490 struct x86_exception *exception) 4491{ 4492 return emulator_read_write(ctxt, addr, val, bytes, 4493 exception, &read_emultor); 4494} 4495 4496static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4497 unsigned long addr, 4498 const void *val, 4499 unsigned int bytes, 4500 struct x86_exception *exception) 4501{ 4502 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4503 exception, &write_emultor); 4504} 4505 4506#define CMPXCHG_TYPE(t, ptr, old, new) \ 4507 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4508 4509#ifdef CONFIG_X86_64 4510# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4511#else 4512# define CMPXCHG64(ptr, old, new) \ 4513 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4514#endif 4515 4516static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4517 unsigned long addr, 4518 const void *old, 4519 const void *new, 4520 unsigned int bytes, 4521 struct x86_exception *exception) 4522{ 4523 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4524 gpa_t gpa; 4525 struct page *page; 4526 char *kaddr; 4527 bool exchanged; 4528 4529 /* guests cmpxchg8b have to be emulated atomically */ 4530 if (bytes > 8 || (bytes & (bytes - 1))) 4531 goto emul_write; 4532 4533 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4534 4535 if (gpa == UNMAPPED_GVA || 4536 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4537 goto emul_write; 4538 4539 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4540 goto emul_write; 4541 4542 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4543 if (is_error_page(page)) 4544 goto emul_write; 4545 4546 kaddr = kmap_atomic(page); 4547 kaddr += offset_in_page(gpa); 4548 switch (bytes) { 4549 case 1: 4550 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4551 break; 4552 case 2: 4553 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4554 break; 4555 case 4: 4556 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4557 break; 4558 case 8: 4559 exchanged = CMPXCHG64(kaddr, old, new); 4560 break; 4561 default: 4562 BUG(); 4563 } 4564 kunmap_atomic(kaddr); 4565 kvm_release_page_dirty(page); 4566 4567 if (!exchanged) 4568 return X86EMUL_CMPXCHG_FAILED; 4569 4570 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4571 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4572 4573 return X86EMUL_CONTINUE; 4574 4575emul_write: 4576 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4577 4578 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4579} 4580 4581static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4582{ 4583 /* TODO: String I/O for in kernel device */ 4584 int r; 4585 4586 if (vcpu->arch.pio.in) 4587 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4588 vcpu->arch.pio.size, pd); 4589 else 4590 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4591 vcpu->arch.pio.port, vcpu->arch.pio.size, 4592 pd); 4593 return r; 4594} 4595 4596static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4597 unsigned short port, void *val, 4598 unsigned int count, bool in) 4599{ 4600 vcpu->arch.pio.port = port; 4601 vcpu->arch.pio.in = in; 4602 vcpu->arch.pio.count = count; 4603 vcpu->arch.pio.size = size; 4604 4605 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4606 vcpu->arch.pio.count = 0; 4607 return 1; 4608 } 4609 4610 vcpu->run->exit_reason = KVM_EXIT_IO; 4611 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4612 vcpu->run->io.size = size; 4613 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4614 vcpu->run->io.count = count; 4615 vcpu->run->io.port = port; 4616 4617 return 0; 4618} 4619 4620static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4621 int size, unsigned short port, void *val, 4622 unsigned int count) 4623{ 4624 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4625 int ret; 4626 4627 if (vcpu->arch.pio.count) 4628 goto data_avail; 4629 4630 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4631 if (ret) { 4632data_avail: 4633 memcpy(val, vcpu->arch.pio_data, size * count); 4634 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4635 vcpu->arch.pio.count = 0; 4636 return 1; 4637 } 4638 4639 return 0; 4640} 4641 4642static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4643 int size, unsigned short port, 4644 const void *val, unsigned int count) 4645{ 4646 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4647 4648 memcpy(vcpu->arch.pio_data, val, size * count); 4649 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4650 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4651} 4652 4653static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4654{ 4655 return kvm_x86_ops->get_segment_base(vcpu, seg); 4656} 4657 4658static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4659{ 4660 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4661} 4662 4663int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4664{ 4665 if (!need_emulate_wbinvd(vcpu)) 4666 return X86EMUL_CONTINUE; 4667 4668 if (kvm_x86_ops->has_wbinvd_exit()) { 4669 int cpu = get_cpu(); 4670 4671 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4672 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4673 wbinvd_ipi, NULL, 1); 4674 put_cpu(); 4675 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4676 } else 4677 wbinvd(); 4678 return X86EMUL_CONTINUE; 4679} 4680 4681int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4682{ 4683 kvm_x86_ops->skip_emulated_instruction(vcpu); 4684 return kvm_emulate_wbinvd_noskip(vcpu); 4685} 4686EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4687 4688 4689 4690static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4691{ 4692 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4693} 4694 4695static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4696 unsigned long *dest) 4697{ 4698 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4699} 4700 4701static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4702 unsigned long value) 4703{ 4704 4705 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4706} 4707 4708static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4709{ 4710 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4711} 4712 4713static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4714{ 4715 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4716 unsigned long value; 4717 4718 switch (cr) { 4719 case 0: 4720 value = kvm_read_cr0(vcpu); 4721 break; 4722 case 2: 4723 value = vcpu->arch.cr2; 4724 break; 4725 case 3: 4726 value = kvm_read_cr3(vcpu); 4727 break; 4728 case 4: 4729 value = kvm_read_cr4(vcpu); 4730 break; 4731 case 8: 4732 value = kvm_get_cr8(vcpu); 4733 break; 4734 default: 4735 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4736 return 0; 4737 } 4738 4739 return value; 4740} 4741 4742static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4743{ 4744 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4745 int res = 0; 4746 4747 switch (cr) { 4748 case 0: 4749 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4750 break; 4751 case 2: 4752 vcpu->arch.cr2 = val; 4753 break; 4754 case 3: 4755 res = kvm_set_cr3(vcpu, val); 4756 break; 4757 case 4: 4758 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4759 break; 4760 case 8: 4761 res = kvm_set_cr8(vcpu, val); 4762 break; 4763 default: 4764 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4765 res = -1; 4766 } 4767 4768 return res; 4769} 4770 4771static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4772{ 4773 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4774} 4775 4776static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4777{ 4778 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4779} 4780 4781static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4782{ 4783 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4784} 4785 4786static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4787{ 4788 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4789} 4790 4791static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4792{ 4793 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4794} 4795 4796static unsigned long emulator_get_cached_segment_base( 4797 struct x86_emulate_ctxt *ctxt, int seg) 4798{ 4799 return get_segment_base(emul_to_vcpu(ctxt), seg); 4800} 4801 4802static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4803 struct desc_struct *desc, u32 *base3, 4804 int seg) 4805{ 4806 struct kvm_segment var; 4807 4808 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4809 *selector = var.selector; 4810 4811 if (var.unusable) { 4812 memset(desc, 0, sizeof(*desc)); 4813 return false; 4814 } 4815 4816 if (var.g) 4817 var.limit >>= 12; 4818 set_desc_limit(desc, var.limit); 4819 set_desc_base(desc, (unsigned long)var.base); 4820#ifdef CONFIG_X86_64 4821 if (base3) 4822 *base3 = var.base >> 32; 4823#endif 4824 desc->type = var.type; 4825 desc->s = var.s; 4826 desc->dpl = var.dpl; 4827 desc->p = var.present; 4828 desc->avl = var.avl; 4829 desc->l = var.l; 4830 desc->d = var.db; 4831 desc->g = var.g; 4832 4833 return true; 4834} 4835 4836static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4837 struct desc_struct *desc, u32 base3, 4838 int seg) 4839{ 4840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4841 struct kvm_segment var; 4842 4843 var.selector = selector; 4844 var.base = get_desc_base(desc); 4845#ifdef CONFIG_X86_64 4846 var.base |= ((u64)base3) << 32; 4847#endif 4848 var.limit = get_desc_limit(desc); 4849 if (desc->g) 4850 var.limit = (var.limit << 12) | 0xfff; 4851 var.type = desc->type; 4852 var.dpl = desc->dpl; 4853 var.db = desc->d; 4854 var.s = desc->s; 4855 var.l = desc->l; 4856 var.g = desc->g; 4857 var.avl = desc->avl; 4858 var.present = desc->p; 4859 var.unusable = !var.present; 4860 var.padding = 0; 4861 4862 kvm_set_segment(vcpu, &var, seg); 4863 return; 4864} 4865 4866static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4867 u32 msr_index, u64 *pdata) 4868{ 4869 struct msr_data msr; 4870 int r; 4871 4872 msr.index = msr_index; 4873 msr.host_initiated = false; 4874 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 4875 if (r) 4876 return r; 4877 4878 *pdata = msr.data; 4879 return 0; 4880} 4881 4882static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4883 u32 msr_index, u64 data) 4884{ 4885 struct msr_data msr; 4886 4887 msr.data = data; 4888 msr.index = msr_index; 4889 msr.host_initiated = false; 4890 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4891} 4892 4893static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 4894{ 4895 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4896 4897 return vcpu->arch.smbase; 4898} 4899 4900static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 4901{ 4902 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4903 4904 vcpu->arch.smbase = smbase; 4905} 4906 4907static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4908 u32 pmc) 4909{ 4910 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 4911} 4912 4913static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4914 u32 pmc, u64 *pdata) 4915{ 4916 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 4917} 4918 4919static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4920{ 4921 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4922} 4923 4924static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4925{ 4926 preempt_disable(); 4927 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4928 /* 4929 * CR0.TS may reference the host fpu state, not the guest fpu state, 4930 * so it may be clear at this point. 4931 */ 4932 clts(); 4933} 4934 4935static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4936{ 4937 preempt_enable(); 4938} 4939 4940static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4941 struct x86_instruction_info *info, 4942 enum x86_intercept_stage stage) 4943{ 4944 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4945} 4946 4947static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4948 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4949{ 4950 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4951} 4952 4953static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4954{ 4955 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4956} 4957 4958static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4959{ 4960 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4961} 4962 4963static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 4964{ 4965 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 4966} 4967 4968static const struct x86_emulate_ops emulate_ops = { 4969 .read_gpr = emulator_read_gpr, 4970 .write_gpr = emulator_write_gpr, 4971 .read_std = kvm_read_guest_virt_system, 4972 .write_std = kvm_write_guest_virt_system, 4973 .read_phys = kvm_read_guest_phys_system, 4974 .fetch = kvm_fetch_guest_virt, 4975 .read_emulated = emulator_read_emulated, 4976 .write_emulated = emulator_write_emulated, 4977 .cmpxchg_emulated = emulator_cmpxchg_emulated, 4978 .invlpg = emulator_invlpg, 4979 .pio_in_emulated = emulator_pio_in_emulated, 4980 .pio_out_emulated = emulator_pio_out_emulated, 4981 .get_segment = emulator_get_segment, 4982 .set_segment = emulator_set_segment, 4983 .get_cached_segment_base = emulator_get_cached_segment_base, 4984 .get_gdt = emulator_get_gdt, 4985 .get_idt = emulator_get_idt, 4986 .set_gdt = emulator_set_gdt, 4987 .set_idt = emulator_set_idt, 4988 .get_cr = emulator_get_cr, 4989 .set_cr = emulator_set_cr, 4990 .cpl = emulator_get_cpl, 4991 .get_dr = emulator_get_dr, 4992 .set_dr = emulator_set_dr, 4993 .get_smbase = emulator_get_smbase, 4994 .set_smbase = emulator_set_smbase, 4995 .set_msr = emulator_set_msr, 4996 .get_msr = emulator_get_msr, 4997 .check_pmc = emulator_check_pmc, 4998 .read_pmc = emulator_read_pmc, 4999 .halt = emulator_halt, 5000 .wbinvd = emulator_wbinvd, 5001 .fix_hypercall = emulator_fix_hypercall, 5002 .get_fpu = emulator_get_fpu, 5003 .put_fpu = emulator_put_fpu, 5004 .intercept = emulator_intercept, 5005 .get_cpuid = emulator_get_cpuid, 5006 .set_nmi_mask = emulator_set_nmi_mask, 5007}; 5008 5009static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5010{ 5011 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5012 /* 5013 * an sti; sti; sequence only disable interrupts for the first 5014 * instruction. So, if the last instruction, be it emulated or 5015 * not, left the system with the INT_STI flag enabled, it 5016 * means that the last instruction is an sti. We should not 5017 * leave the flag on in this case. The same goes for mov ss 5018 */ 5019 if (int_shadow & mask) 5020 mask = 0; 5021 if (unlikely(int_shadow || mask)) { 5022 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5023 if (!mask) 5024 kvm_make_request(KVM_REQ_EVENT, vcpu); 5025 } 5026} 5027 5028static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5029{ 5030 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5031 if (ctxt->exception.vector == PF_VECTOR) 5032 return kvm_propagate_fault(vcpu, &ctxt->exception); 5033 5034 if (ctxt->exception.error_code_valid) 5035 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5036 ctxt->exception.error_code); 5037 else 5038 kvm_queue_exception(vcpu, ctxt->exception.vector); 5039 return false; 5040} 5041 5042static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5043{ 5044 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5045 int cs_db, cs_l; 5046 5047 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5048 5049 ctxt->eflags = kvm_get_rflags(vcpu); 5050 ctxt->eip = kvm_rip_read(vcpu); 5051 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5052 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5053 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5054 cs_db ? X86EMUL_MODE_PROT32 : 5055 X86EMUL_MODE_PROT16; 5056 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5057 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5058 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5059 ctxt->emul_flags = vcpu->arch.hflags; 5060 5061 init_decode_cache(ctxt); 5062 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5063} 5064 5065int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5066{ 5067 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5068 int ret; 5069 5070 init_emulate_ctxt(vcpu); 5071 5072 ctxt->op_bytes = 2; 5073 ctxt->ad_bytes = 2; 5074 ctxt->_eip = ctxt->eip + inc_eip; 5075 ret = emulate_int_real(ctxt, irq); 5076 5077 if (ret != X86EMUL_CONTINUE) 5078 return EMULATE_FAIL; 5079 5080 ctxt->eip = ctxt->_eip; 5081 kvm_rip_write(vcpu, ctxt->eip); 5082 kvm_set_rflags(vcpu, ctxt->eflags); 5083 5084 if (irq == NMI_VECTOR) 5085 vcpu->arch.nmi_pending = 0; 5086 else 5087 vcpu->arch.interrupt.pending = false; 5088 5089 return EMULATE_DONE; 5090} 5091EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5092 5093static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5094{ 5095 int r = EMULATE_DONE; 5096 5097 ++vcpu->stat.insn_emulation_fail; 5098 trace_kvm_emulate_insn_failed(vcpu); 5099 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5100 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5101 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5102 vcpu->run->internal.ndata = 0; 5103 r = EMULATE_FAIL; 5104 } 5105 kvm_queue_exception(vcpu, UD_VECTOR); 5106 5107 return r; 5108} 5109 5110static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5111 bool write_fault_to_shadow_pgtable, 5112 int emulation_type) 5113{ 5114 gpa_t gpa = cr2; 5115 pfn_t pfn; 5116 5117 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5118 return false; 5119 5120 if (!vcpu->arch.mmu.direct_map) { 5121 /* 5122 * Write permission should be allowed since only 5123 * write access need to be emulated. 5124 */ 5125 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5126 5127 /* 5128 * If the mapping is invalid in guest, let cpu retry 5129 * it to generate fault. 5130 */ 5131 if (gpa == UNMAPPED_GVA) 5132 return true; 5133 } 5134 5135 /* 5136 * Do not retry the unhandleable instruction if it faults on the 5137 * readonly host memory, otherwise it will goto a infinite loop: 5138 * retry instruction -> write #PF -> emulation fail -> retry 5139 * instruction -> ... 5140 */ 5141 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5142 5143 /* 5144 * If the instruction failed on the error pfn, it can not be fixed, 5145 * report the error to userspace. 5146 */ 5147 if (is_error_noslot_pfn(pfn)) 5148 return false; 5149 5150 kvm_release_pfn_clean(pfn); 5151 5152 /* The instructions are well-emulated on direct mmu. */ 5153 if (vcpu->arch.mmu.direct_map) { 5154 unsigned int indirect_shadow_pages; 5155 5156 spin_lock(&vcpu->kvm->mmu_lock); 5157 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5158 spin_unlock(&vcpu->kvm->mmu_lock); 5159 5160 if (indirect_shadow_pages) 5161 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5162 5163 return true; 5164 } 5165 5166 /* 5167 * if emulation was due to access to shadowed page table 5168 * and it failed try to unshadow page and re-enter the 5169 * guest to let CPU execute the instruction. 5170 */ 5171 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5172 5173 /* 5174 * If the access faults on its page table, it can not 5175 * be fixed by unprotecting shadow page and it should 5176 * be reported to userspace. 5177 */ 5178 return !write_fault_to_shadow_pgtable; 5179} 5180 5181static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5182 unsigned long cr2, int emulation_type) 5183{ 5184 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5185 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5186 5187 last_retry_eip = vcpu->arch.last_retry_eip; 5188 last_retry_addr = vcpu->arch.last_retry_addr; 5189 5190 /* 5191 * If the emulation is caused by #PF and it is non-page_table 5192 * writing instruction, it means the VM-EXIT is caused by shadow 5193 * page protected, we can zap the shadow page and retry this 5194 * instruction directly. 5195 * 5196 * Note: if the guest uses a non-page-table modifying instruction 5197 * on the PDE that points to the instruction, then we will unmap 5198 * the instruction and go to an infinite loop. So, we cache the 5199 * last retried eip and the last fault address, if we meet the eip 5200 * and the address again, we can break out of the potential infinite 5201 * loop. 5202 */ 5203 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5204 5205 if (!(emulation_type & EMULTYPE_RETRY)) 5206 return false; 5207 5208 if (x86_page_table_writing_insn(ctxt)) 5209 return false; 5210 5211 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5212 return false; 5213 5214 vcpu->arch.last_retry_eip = ctxt->eip; 5215 vcpu->arch.last_retry_addr = cr2; 5216 5217 if (!vcpu->arch.mmu.direct_map) 5218 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5219 5220 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5221 5222 return true; 5223} 5224 5225static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5226static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5227 5228static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5229{ 5230 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5231 /* This is a good place to trace that we are exiting SMM. */ 5232 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5233 5234 if (unlikely(vcpu->arch.smi_pending)) { 5235 kvm_make_request(KVM_REQ_SMI, vcpu); 5236 vcpu->arch.smi_pending = 0; 5237 } else { 5238 /* Process a latched INIT, if any. */ 5239 kvm_make_request(KVM_REQ_EVENT, vcpu); 5240 } 5241 } 5242 5243 kvm_mmu_reset_context(vcpu); 5244} 5245 5246static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5247{ 5248 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5249 5250 vcpu->arch.hflags = emul_flags; 5251 5252 if (changed & HF_SMM_MASK) 5253 kvm_smm_changed(vcpu); 5254} 5255 5256static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5257 unsigned long *db) 5258{ 5259 u32 dr6 = 0; 5260 int i; 5261 u32 enable, rwlen; 5262 5263 enable = dr7; 5264 rwlen = dr7 >> 16; 5265 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5266 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5267 dr6 |= (1 << i); 5268 return dr6; 5269} 5270 5271static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5272{ 5273 struct kvm_run *kvm_run = vcpu->run; 5274 5275 /* 5276 * rflags is the old, "raw" value of the flags. The new value has 5277 * not been saved yet. 5278 * 5279 * This is correct even for TF set by the guest, because "the 5280 * processor will not generate this exception after the instruction 5281 * that sets the TF flag". 5282 */ 5283 if (unlikely(rflags & X86_EFLAGS_TF)) { 5284 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5285 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5286 DR6_RTM; 5287 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5288 kvm_run->debug.arch.exception = DB_VECTOR; 5289 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5290 *r = EMULATE_USER_EXIT; 5291 } else { 5292 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5293 /* 5294 * "Certain debug exceptions may clear bit 0-3. The 5295 * remaining contents of the DR6 register are never 5296 * cleared by the processor". 5297 */ 5298 vcpu->arch.dr6 &= ~15; 5299 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5300 kvm_queue_exception(vcpu, DB_VECTOR); 5301 } 5302 } 5303} 5304 5305static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5306{ 5307 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5308 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5309 struct kvm_run *kvm_run = vcpu->run; 5310 unsigned long eip = kvm_get_linear_rip(vcpu); 5311 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5312 vcpu->arch.guest_debug_dr7, 5313 vcpu->arch.eff_db); 5314 5315 if (dr6 != 0) { 5316 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5317 kvm_run->debug.arch.pc = eip; 5318 kvm_run->debug.arch.exception = DB_VECTOR; 5319 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5320 *r = EMULATE_USER_EXIT; 5321 return true; 5322 } 5323 } 5324 5325 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5326 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5327 unsigned long eip = kvm_get_linear_rip(vcpu); 5328 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5329 vcpu->arch.dr7, 5330 vcpu->arch.db); 5331 5332 if (dr6 != 0) { 5333 vcpu->arch.dr6 &= ~15; 5334 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5335 kvm_queue_exception(vcpu, DB_VECTOR); 5336 *r = EMULATE_DONE; 5337 return true; 5338 } 5339 } 5340 5341 return false; 5342} 5343 5344int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5345 unsigned long cr2, 5346 int emulation_type, 5347 void *insn, 5348 int insn_len) 5349{ 5350 int r; 5351 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5352 bool writeback = true; 5353 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5354 5355 /* 5356 * Clear write_fault_to_shadow_pgtable here to ensure it is 5357 * never reused. 5358 */ 5359 vcpu->arch.write_fault_to_shadow_pgtable = false; 5360 kvm_clear_exception_queue(vcpu); 5361 5362 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5363 init_emulate_ctxt(vcpu); 5364 5365 /* 5366 * We will reenter on the same instruction since 5367 * we do not set complete_userspace_io. This does not 5368 * handle watchpoints yet, those would be handled in 5369 * the emulate_ops. 5370 */ 5371 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5372 return r; 5373 5374 ctxt->interruptibility = 0; 5375 ctxt->have_exception = false; 5376 ctxt->exception.vector = -1; 5377 ctxt->perm_ok = false; 5378 5379 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5380 5381 r = x86_decode_insn(ctxt, insn, insn_len); 5382 5383 trace_kvm_emulate_insn_start(vcpu); 5384 ++vcpu->stat.insn_emulation; 5385 if (r != EMULATION_OK) { 5386 if (emulation_type & EMULTYPE_TRAP_UD) 5387 return EMULATE_FAIL; 5388 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5389 emulation_type)) 5390 return EMULATE_DONE; 5391 if (emulation_type & EMULTYPE_SKIP) 5392 return EMULATE_FAIL; 5393 return handle_emulation_failure(vcpu); 5394 } 5395 } 5396 5397 if (emulation_type & EMULTYPE_SKIP) { 5398 kvm_rip_write(vcpu, ctxt->_eip); 5399 if (ctxt->eflags & X86_EFLAGS_RF) 5400 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5401 return EMULATE_DONE; 5402 } 5403 5404 if (retry_instruction(ctxt, cr2, emulation_type)) 5405 return EMULATE_DONE; 5406 5407 /* this is needed for vmware backdoor interface to work since it 5408 changes registers values during IO operation */ 5409 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5410 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5411 emulator_invalidate_register_cache(ctxt); 5412 } 5413 5414restart: 5415 r = x86_emulate_insn(ctxt); 5416 5417 if (r == EMULATION_INTERCEPTED) 5418 return EMULATE_DONE; 5419 5420 if (r == EMULATION_FAILED) { 5421 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5422 emulation_type)) 5423 return EMULATE_DONE; 5424 5425 return handle_emulation_failure(vcpu); 5426 } 5427 5428 if (ctxt->have_exception) { 5429 r = EMULATE_DONE; 5430 if (inject_emulated_exception(vcpu)) 5431 return r; 5432 } else if (vcpu->arch.pio.count) { 5433 if (!vcpu->arch.pio.in) { 5434 /* FIXME: return into emulator if single-stepping. */ 5435 vcpu->arch.pio.count = 0; 5436 } else { 5437 writeback = false; 5438 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5439 } 5440 r = EMULATE_USER_EXIT; 5441 } else if (vcpu->mmio_needed) { 5442 if (!vcpu->mmio_is_write) 5443 writeback = false; 5444 r = EMULATE_USER_EXIT; 5445 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5446 } else if (r == EMULATION_RESTART) 5447 goto restart; 5448 else 5449 r = EMULATE_DONE; 5450 5451 if (writeback) { 5452 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5453 toggle_interruptibility(vcpu, ctxt->interruptibility); 5454 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5455 if (vcpu->arch.hflags != ctxt->emul_flags) 5456 kvm_set_hflags(vcpu, ctxt->emul_flags); 5457 kvm_rip_write(vcpu, ctxt->eip); 5458 if (r == EMULATE_DONE) 5459 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5460 if (!ctxt->have_exception || 5461 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5462 __kvm_set_rflags(vcpu, ctxt->eflags); 5463 5464 /* 5465 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5466 * do nothing, and it will be requested again as soon as 5467 * the shadow expires. But we still need to check here, 5468 * because POPF has no interrupt shadow. 5469 */ 5470 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5471 kvm_make_request(KVM_REQ_EVENT, vcpu); 5472 } else 5473 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5474 5475 return r; 5476} 5477EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5478 5479int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5480{ 5481 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5482 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5483 size, port, &val, 1); 5484 /* do not return to emulator after return from userspace */ 5485 vcpu->arch.pio.count = 0; 5486 return ret; 5487} 5488EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5489 5490static void tsc_bad(void *info) 5491{ 5492 __this_cpu_write(cpu_tsc_khz, 0); 5493} 5494 5495static void tsc_khz_changed(void *data) 5496{ 5497 struct cpufreq_freqs *freq = data; 5498 unsigned long khz = 0; 5499 5500 if (data) 5501 khz = freq->new; 5502 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5503 khz = cpufreq_quick_get(raw_smp_processor_id()); 5504 if (!khz) 5505 khz = tsc_khz; 5506 __this_cpu_write(cpu_tsc_khz, khz); 5507} 5508 5509static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5510 void *data) 5511{ 5512 struct cpufreq_freqs *freq = data; 5513 struct kvm *kvm; 5514 struct kvm_vcpu *vcpu; 5515 int i, send_ipi = 0; 5516 5517 /* 5518 * We allow guests to temporarily run on slowing clocks, 5519 * provided we notify them after, or to run on accelerating 5520 * clocks, provided we notify them before. Thus time never 5521 * goes backwards. 5522 * 5523 * However, we have a problem. We can't atomically update 5524 * the frequency of a given CPU from this function; it is 5525 * merely a notifier, which can be called from any CPU. 5526 * Changing the TSC frequency at arbitrary points in time 5527 * requires a recomputation of local variables related to 5528 * the TSC for each VCPU. We must flag these local variables 5529 * to be updated and be sure the update takes place with the 5530 * new frequency before any guests proceed. 5531 * 5532 * Unfortunately, the combination of hotplug CPU and frequency 5533 * change creates an intractable locking scenario; the order 5534 * of when these callouts happen is undefined with respect to 5535 * CPU hotplug, and they can race with each other. As such, 5536 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5537 * undefined; you can actually have a CPU frequency change take 5538 * place in between the computation of X and the setting of the 5539 * variable. To protect against this problem, all updates of 5540 * the per_cpu tsc_khz variable are done in an interrupt 5541 * protected IPI, and all callers wishing to update the value 5542 * must wait for a synchronous IPI to complete (which is trivial 5543 * if the caller is on the CPU already). This establishes the 5544 * necessary total order on variable updates. 5545 * 5546 * Note that because a guest time update may take place 5547 * anytime after the setting of the VCPU's request bit, the 5548 * correct TSC value must be set before the request. However, 5549 * to ensure the update actually makes it to any guest which 5550 * starts running in hardware virtualization between the set 5551 * and the acquisition of the spinlock, we must also ping the 5552 * CPU after setting the request bit. 5553 * 5554 */ 5555 5556 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5557 return 0; 5558 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5559 return 0; 5560 5561 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5562 5563 spin_lock(&kvm_lock); 5564 list_for_each_entry(kvm, &vm_list, vm_list) { 5565 kvm_for_each_vcpu(i, vcpu, kvm) { 5566 if (vcpu->cpu != freq->cpu) 5567 continue; 5568 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5569 if (vcpu->cpu != smp_processor_id()) 5570 send_ipi = 1; 5571 } 5572 } 5573 spin_unlock(&kvm_lock); 5574 5575 if (freq->old < freq->new && send_ipi) { 5576 /* 5577 * We upscale the frequency. Must make the guest 5578 * doesn't see old kvmclock values while running with 5579 * the new frequency, otherwise we risk the guest sees 5580 * time go backwards. 5581 * 5582 * In case we update the frequency for another cpu 5583 * (which might be in guest context) send an interrupt 5584 * to kick the cpu out of guest context. Next time 5585 * guest context is entered kvmclock will be updated, 5586 * so the guest will not see stale values. 5587 */ 5588 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5589 } 5590 return 0; 5591} 5592 5593static struct notifier_block kvmclock_cpufreq_notifier_block = { 5594 .notifier_call = kvmclock_cpufreq_notifier 5595}; 5596 5597static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5598 unsigned long action, void *hcpu) 5599{ 5600 unsigned int cpu = (unsigned long)hcpu; 5601 5602 switch (action) { 5603 case CPU_ONLINE: 5604 case CPU_DOWN_FAILED: 5605 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5606 break; 5607 case CPU_DOWN_PREPARE: 5608 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5609 break; 5610 } 5611 return NOTIFY_OK; 5612} 5613 5614static struct notifier_block kvmclock_cpu_notifier_block = { 5615 .notifier_call = kvmclock_cpu_notifier, 5616 .priority = -INT_MAX 5617}; 5618 5619static void kvm_timer_init(void) 5620{ 5621 int cpu; 5622 5623 max_tsc_khz = tsc_khz; 5624 5625 cpu_notifier_register_begin(); 5626 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5627#ifdef CONFIG_CPU_FREQ 5628 struct cpufreq_policy policy; 5629 memset(&policy, 0, sizeof(policy)); 5630 cpu = get_cpu(); 5631 cpufreq_get_policy(&policy, cpu); 5632 if (policy.cpuinfo.max_freq) 5633 max_tsc_khz = policy.cpuinfo.max_freq; 5634 put_cpu(); 5635#endif 5636 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5637 CPUFREQ_TRANSITION_NOTIFIER); 5638 } 5639 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5640 for_each_online_cpu(cpu) 5641 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5642 5643 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5644 cpu_notifier_register_done(); 5645 5646} 5647 5648static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5649 5650int kvm_is_in_guest(void) 5651{ 5652 return __this_cpu_read(current_vcpu) != NULL; 5653} 5654 5655static int kvm_is_user_mode(void) 5656{ 5657 int user_mode = 3; 5658 5659 if (__this_cpu_read(current_vcpu)) 5660 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5661 5662 return user_mode != 0; 5663} 5664 5665static unsigned long kvm_get_guest_ip(void) 5666{ 5667 unsigned long ip = 0; 5668 5669 if (__this_cpu_read(current_vcpu)) 5670 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5671 5672 return ip; 5673} 5674 5675static struct perf_guest_info_callbacks kvm_guest_cbs = { 5676 .is_in_guest = kvm_is_in_guest, 5677 .is_user_mode = kvm_is_user_mode, 5678 .get_guest_ip = kvm_get_guest_ip, 5679}; 5680 5681void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5682{ 5683 __this_cpu_write(current_vcpu, vcpu); 5684} 5685EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5686 5687void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5688{ 5689 __this_cpu_write(current_vcpu, NULL); 5690} 5691EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5692 5693static void kvm_set_mmio_spte_mask(void) 5694{ 5695 u64 mask; 5696 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5697 5698 /* 5699 * Set the reserved bits and the present bit of an paging-structure 5700 * entry to generate page fault with PFER.RSV = 1. 5701 */ 5702 /* Mask the reserved physical address bits. */ 5703 mask = rsvd_bits(maxphyaddr, 51); 5704 5705 /* Bit 62 is always reserved for 32bit host. */ 5706 mask |= 0x3ull << 62; 5707 5708 /* Set the present bit. */ 5709 mask |= 1ull; 5710 5711#ifdef CONFIG_X86_64 5712 /* 5713 * If reserved bit is not supported, clear the present bit to disable 5714 * mmio page fault. 5715 */ 5716 if (maxphyaddr == 52) 5717 mask &= ~1ull; 5718#endif 5719 5720 kvm_mmu_set_mmio_spte_mask(mask); 5721} 5722 5723#ifdef CONFIG_X86_64 5724static void pvclock_gtod_update_fn(struct work_struct *work) 5725{ 5726 struct kvm *kvm; 5727 5728 struct kvm_vcpu *vcpu; 5729 int i; 5730 5731 spin_lock(&kvm_lock); 5732 list_for_each_entry(kvm, &vm_list, vm_list) 5733 kvm_for_each_vcpu(i, vcpu, kvm) 5734 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5735 atomic_set(&kvm_guest_has_master_clock, 0); 5736 spin_unlock(&kvm_lock); 5737} 5738 5739static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5740 5741/* 5742 * Notification about pvclock gtod data update. 5743 */ 5744static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5745 void *priv) 5746{ 5747 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5748 struct timekeeper *tk = priv; 5749 5750 update_pvclock_gtod(tk); 5751 5752 /* disable master clock if host does not trust, or does not 5753 * use, TSC clocksource 5754 */ 5755 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5756 atomic_read(&kvm_guest_has_master_clock) != 0) 5757 queue_work(system_long_wq, &pvclock_gtod_work); 5758 5759 return 0; 5760} 5761 5762static struct notifier_block pvclock_gtod_notifier = { 5763 .notifier_call = pvclock_gtod_notify, 5764}; 5765#endif 5766 5767int kvm_arch_init(void *opaque) 5768{ 5769 int r; 5770 struct kvm_x86_ops *ops = opaque; 5771 5772 if (kvm_x86_ops) { 5773 printk(KERN_ERR "kvm: already loaded the other module\n"); 5774 r = -EEXIST; 5775 goto out; 5776 } 5777 5778 if (!ops->cpu_has_kvm_support()) { 5779 printk(KERN_ERR "kvm: no hardware support\n"); 5780 r = -EOPNOTSUPP; 5781 goto out; 5782 } 5783 if (ops->disabled_by_bios()) { 5784 printk(KERN_ERR "kvm: disabled by bios\n"); 5785 r = -EOPNOTSUPP; 5786 goto out; 5787 } 5788 5789 r = -ENOMEM; 5790 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5791 if (!shared_msrs) { 5792 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5793 goto out; 5794 } 5795 5796 r = kvm_mmu_module_init(); 5797 if (r) 5798 goto out_free_percpu; 5799 5800 kvm_set_mmio_spte_mask(); 5801 5802 kvm_x86_ops = ops; 5803 5804 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5805 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5806 5807 kvm_timer_init(); 5808 5809 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5810 5811 if (cpu_has_xsave) 5812 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5813 5814 kvm_lapic_init(); 5815#ifdef CONFIG_X86_64 5816 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5817#endif 5818 5819 return 0; 5820 5821out_free_percpu: 5822 free_percpu(shared_msrs); 5823out: 5824 return r; 5825} 5826 5827void kvm_arch_exit(void) 5828{ 5829 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5830 5831 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5832 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5833 CPUFREQ_TRANSITION_NOTIFIER); 5834 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5835#ifdef CONFIG_X86_64 5836 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5837#endif 5838 kvm_x86_ops = NULL; 5839 kvm_mmu_module_exit(); 5840 free_percpu(shared_msrs); 5841} 5842 5843int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5844{ 5845 ++vcpu->stat.halt_exits; 5846 if (lapic_in_kernel(vcpu)) { 5847 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5848 return 1; 5849 } else { 5850 vcpu->run->exit_reason = KVM_EXIT_HLT; 5851 return 0; 5852 } 5853} 5854EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5855 5856int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5857{ 5858 kvm_x86_ops->skip_emulated_instruction(vcpu); 5859 return kvm_vcpu_halt(vcpu); 5860} 5861EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5862 5863/* 5864 * kvm_pv_kick_cpu_op: Kick a vcpu. 5865 * 5866 * @apicid - apicid of vcpu to be kicked. 5867 */ 5868static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5869{ 5870 struct kvm_lapic_irq lapic_irq; 5871 5872 lapic_irq.shorthand = 0; 5873 lapic_irq.dest_mode = 0; 5874 lapic_irq.dest_id = apicid; 5875 lapic_irq.msi_redir_hint = false; 5876 5877 lapic_irq.delivery_mode = APIC_DM_REMRD; 5878 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5879} 5880 5881int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5882{ 5883 unsigned long nr, a0, a1, a2, a3, ret; 5884 int op_64_bit, r = 1; 5885 5886 kvm_x86_ops->skip_emulated_instruction(vcpu); 5887 5888 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5889 return kvm_hv_hypercall(vcpu); 5890 5891 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5892 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5893 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5894 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5895 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5896 5897 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5898 5899 op_64_bit = is_64_bit_mode(vcpu); 5900 if (!op_64_bit) { 5901 nr &= 0xFFFFFFFF; 5902 a0 &= 0xFFFFFFFF; 5903 a1 &= 0xFFFFFFFF; 5904 a2 &= 0xFFFFFFFF; 5905 a3 &= 0xFFFFFFFF; 5906 } 5907 5908 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5909 ret = -KVM_EPERM; 5910 goto out; 5911 } 5912 5913 switch (nr) { 5914 case KVM_HC_VAPIC_POLL_IRQ: 5915 ret = 0; 5916 break; 5917 case KVM_HC_KICK_CPU: 5918 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5919 ret = 0; 5920 break; 5921 default: 5922 ret = -KVM_ENOSYS; 5923 break; 5924 } 5925out: 5926 if (!op_64_bit) 5927 ret = (u32)ret; 5928 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5929 ++vcpu->stat.hypercalls; 5930 return r; 5931} 5932EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5933 5934static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5935{ 5936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5937 char instruction[3]; 5938 unsigned long rip = kvm_rip_read(vcpu); 5939 5940 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5941 5942 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 5943} 5944 5945static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 5946{ 5947 return vcpu->run->request_interrupt_window && 5948 likely(!pic_in_kernel(vcpu->kvm)); 5949} 5950 5951static void post_kvm_run_save(struct kvm_vcpu *vcpu) 5952{ 5953 struct kvm_run *kvm_run = vcpu->run; 5954 5955 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 5956 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 5957 kvm_run->cr8 = kvm_get_cr8(vcpu); 5958 kvm_run->apic_base = kvm_get_apic_base(vcpu); 5959 kvm_run->ready_for_interrupt_injection = 5960 pic_in_kernel(vcpu->kvm) || 5961 kvm_vcpu_ready_for_interrupt_injection(vcpu); 5962} 5963 5964static void update_cr8_intercept(struct kvm_vcpu *vcpu) 5965{ 5966 int max_irr, tpr; 5967 5968 if (!kvm_x86_ops->update_cr8_intercept) 5969 return; 5970 5971 if (!vcpu->arch.apic) 5972 return; 5973 5974 if (!vcpu->arch.apic->vapic_addr) 5975 max_irr = kvm_lapic_find_highest_irr(vcpu); 5976 else 5977 max_irr = -1; 5978 5979 if (max_irr != -1) 5980 max_irr >>= 4; 5981 5982 tpr = kvm_lapic_get_cr8(vcpu); 5983 5984 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 5985} 5986 5987static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 5988{ 5989 int r; 5990 5991 /* try to reinject previous events if any */ 5992 if (vcpu->arch.exception.pending) { 5993 trace_kvm_inj_exception(vcpu->arch.exception.nr, 5994 vcpu->arch.exception.has_error_code, 5995 vcpu->arch.exception.error_code); 5996 5997 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 5998 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 5999 X86_EFLAGS_RF); 6000 6001 if (vcpu->arch.exception.nr == DB_VECTOR && 6002 (vcpu->arch.dr7 & DR7_GD)) { 6003 vcpu->arch.dr7 &= ~DR7_GD; 6004 kvm_update_dr7(vcpu); 6005 } 6006 6007 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6008 vcpu->arch.exception.has_error_code, 6009 vcpu->arch.exception.error_code, 6010 vcpu->arch.exception.reinject); 6011 return 0; 6012 } 6013 6014 if (vcpu->arch.nmi_injected) { 6015 kvm_x86_ops->set_nmi(vcpu); 6016 return 0; 6017 } 6018 6019 if (vcpu->arch.interrupt.pending) { 6020 kvm_x86_ops->set_irq(vcpu); 6021 return 0; 6022 } 6023 6024 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6025 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6026 if (r != 0) 6027 return r; 6028 } 6029 6030 /* try to inject new event if pending */ 6031 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6032 --vcpu->arch.nmi_pending; 6033 vcpu->arch.nmi_injected = true; 6034 kvm_x86_ops->set_nmi(vcpu); 6035 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6036 /* 6037 * Because interrupts can be injected asynchronously, we are 6038 * calling check_nested_events again here to avoid a race condition. 6039 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6040 * proposal and current concerns. Perhaps we should be setting 6041 * KVM_REQ_EVENT only on certain events and not unconditionally? 6042 */ 6043 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6044 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6045 if (r != 0) 6046 return r; 6047 } 6048 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6049 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6050 false); 6051 kvm_x86_ops->set_irq(vcpu); 6052 } 6053 } 6054 return 0; 6055} 6056 6057static void process_nmi(struct kvm_vcpu *vcpu) 6058{ 6059 unsigned limit = 2; 6060 6061 /* 6062 * x86 is limited to one NMI running, and one NMI pending after it. 6063 * If an NMI is already in progress, limit further NMIs to just one. 6064 * Otherwise, allow two (and we'll inject the first one immediately). 6065 */ 6066 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6067 limit = 1; 6068 6069 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6070 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6071 kvm_make_request(KVM_REQ_EVENT, vcpu); 6072} 6073 6074#define put_smstate(type, buf, offset, val) \ 6075 *(type *)((buf) + (offset) - 0x7e00) = val 6076 6077static u32 process_smi_get_segment_flags(struct kvm_segment *seg) 6078{ 6079 u32 flags = 0; 6080 flags |= seg->g << 23; 6081 flags |= seg->db << 22; 6082 flags |= seg->l << 21; 6083 flags |= seg->avl << 20; 6084 flags |= seg->present << 15; 6085 flags |= seg->dpl << 13; 6086 flags |= seg->s << 12; 6087 flags |= seg->type << 8; 6088 return flags; 6089} 6090 6091static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6092{ 6093 struct kvm_segment seg; 6094 int offset; 6095 6096 kvm_get_segment(vcpu, &seg, n); 6097 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6098 6099 if (n < 3) 6100 offset = 0x7f84 + n * 12; 6101 else 6102 offset = 0x7f2c + (n - 3) * 12; 6103 6104 put_smstate(u32, buf, offset + 8, seg.base); 6105 put_smstate(u32, buf, offset + 4, seg.limit); 6106 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); 6107} 6108 6109#ifdef CONFIG_X86_64 6110static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6111{ 6112 struct kvm_segment seg; 6113 int offset; 6114 u16 flags; 6115 6116 kvm_get_segment(vcpu, &seg, n); 6117 offset = 0x7e00 + n * 16; 6118 6119 flags = process_smi_get_segment_flags(&seg) >> 8; 6120 put_smstate(u16, buf, offset, seg.selector); 6121 put_smstate(u16, buf, offset + 2, flags); 6122 put_smstate(u32, buf, offset + 4, seg.limit); 6123 put_smstate(u64, buf, offset + 8, seg.base); 6124} 6125#endif 6126 6127static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6128{ 6129 struct desc_ptr dt; 6130 struct kvm_segment seg; 6131 unsigned long val; 6132 int i; 6133 6134 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6135 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6136 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6137 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6138 6139 for (i = 0; i < 8; i++) 6140 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6141 6142 kvm_get_dr(vcpu, 6, &val); 6143 put_smstate(u32, buf, 0x7fcc, (u32)val); 6144 kvm_get_dr(vcpu, 7, &val); 6145 put_smstate(u32, buf, 0x7fc8, (u32)val); 6146 6147 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6148 put_smstate(u32, buf, 0x7fc4, seg.selector); 6149 put_smstate(u32, buf, 0x7f64, seg.base); 6150 put_smstate(u32, buf, 0x7f60, seg.limit); 6151 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); 6152 6153 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6154 put_smstate(u32, buf, 0x7fc0, seg.selector); 6155 put_smstate(u32, buf, 0x7f80, seg.base); 6156 put_smstate(u32, buf, 0x7f7c, seg.limit); 6157 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); 6158 6159 kvm_x86_ops->get_gdt(vcpu, &dt); 6160 put_smstate(u32, buf, 0x7f74, dt.address); 6161 put_smstate(u32, buf, 0x7f70, dt.size); 6162 6163 kvm_x86_ops->get_idt(vcpu, &dt); 6164 put_smstate(u32, buf, 0x7f58, dt.address); 6165 put_smstate(u32, buf, 0x7f54, dt.size); 6166 6167 for (i = 0; i < 6; i++) 6168 process_smi_save_seg_32(vcpu, buf, i); 6169 6170 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6171 6172 /* revision id */ 6173 put_smstate(u32, buf, 0x7efc, 0x00020000); 6174 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6175} 6176 6177static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6178{ 6179#ifdef CONFIG_X86_64 6180 struct desc_ptr dt; 6181 struct kvm_segment seg; 6182 unsigned long val; 6183 int i; 6184 6185 for (i = 0; i < 16; i++) 6186 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6187 6188 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6189 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6190 6191 kvm_get_dr(vcpu, 6, &val); 6192 put_smstate(u64, buf, 0x7f68, val); 6193 kvm_get_dr(vcpu, 7, &val); 6194 put_smstate(u64, buf, 0x7f60, val); 6195 6196 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6197 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6198 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6199 6200 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6201 6202 /* revision id */ 6203 put_smstate(u32, buf, 0x7efc, 0x00020064); 6204 6205 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6206 6207 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6208 put_smstate(u16, buf, 0x7e90, seg.selector); 6209 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); 6210 put_smstate(u32, buf, 0x7e94, seg.limit); 6211 put_smstate(u64, buf, 0x7e98, seg.base); 6212 6213 kvm_x86_ops->get_idt(vcpu, &dt); 6214 put_smstate(u32, buf, 0x7e84, dt.size); 6215 put_smstate(u64, buf, 0x7e88, dt.address); 6216 6217 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6218 put_smstate(u16, buf, 0x7e70, seg.selector); 6219 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); 6220 put_smstate(u32, buf, 0x7e74, seg.limit); 6221 put_smstate(u64, buf, 0x7e78, seg.base); 6222 6223 kvm_x86_ops->get_gdt(vcpu, &dt); 6224 put_smstate(u32, buf, 0x7e64, dt.size); 6225 put_smstate(u64, buf, 0x7e68, dt.address); 6226 6227 for (i = 0; i < 6; i++) 6228 process_smi_save_seg_64(vcpu, buf, i); 6229#else 6230 WARN_ON_ONCE(1); 6231#endif 6232} 6233 6234static void process_smi(struct kvm_vcpu *vcpu) 6235{ 6236 struct kvm_segment cs, ds; 6237 struct desc_ptr dt; 6238 char buf[512]; 6239 u32 cr0; 6240 6241 if (is_smm(vcpu)) { 6242 vcpu->arch.smi_pending = true; 6243 return; 6244 } 6245 6246 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6247 vcpu->arch.hflags |= HF_SMM_MASK; 6248 memset(buf, 0, 512); 6249 if (guest_cpuid_has_longmode(vcpu)) 6250 process_smi_save_state_64(vcpu, buf); 6251 else 6252 process_smi_save_state_32(vcpu, buf); 6253 6254 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6255 6256 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6257 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6258 else 6259 kvm_x86_ops->set_nmi_mask(vcpu, true); 6260 6261 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6262 kvm_rip_write(vcpu, 0x8000); 6263 6264 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6265 kvm_x86_ops->set_cr0(vcpu, cr0); 6266 vcpu->arch.cr0 = cr0; 6267 6268 kvm_x86_ops->set_cr4(vcpu, 0); 6269 6270 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6271 dt.address = dt.size = 0; 6272 kvm_x86_ops->set_idt(vcpu, &dt); 6273 6274 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6275 6276 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6277 cs.base = vcpu->arch.smbase; 6278 6279 ds.selector = 0; 6280 ds.base = 0; 6281 6282 cs.limit = ds.limit = 0xffffffff; 6283 cs.type = ds.type = 0x3; 6284 cs.dpl = ds.dpl = 0; 6285 cs.db = ds.db = 0; 6286 cs.s = ds.s = 1; 6287 cs.l = ds.l = 0; 6288 cs.g = ds.g = 1; 6289 cs.avl = ds.avl = 0; 6290 cs.present = ds.present = 1; 6291 cs.unusable = ds.unusable = 0; 6292 cs.padding = ds.padding = 0; 6293 6294 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6295 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6296 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6297 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6298 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6299 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6300 6301 if (guest_cpuid_has_longmode(vcpu)) 6302 kvm_x86_ops->set_efer(vcpu, 0); 6303 6304 kvm_update_cpuid(vcpu); 6305 kvm_mmu_reset_context(vcpu); 6306} 6307 6308static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6309{ 6310 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6311 return; 6312 6313 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8); 6314 6315 if (irqchip_split(vcpu->kvm)) 6316 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap); 6317 else { 6318 kvm_x86_ops->sync_pir_to_irr(vcpu); 6319 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap); 6320 } 6321 kvm_x86_ops->load_eoi_exitmap(vcpu); 6322} 6323 6324static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6325{ 6326 ++vcpu->stat.tlb_flush; 6327 kvm_x86_ops->tlb_flush(vcpu); 6328} 6329 6330void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6331{ 6332 struct page *page = NULL; 6333 6334 if (!lapic_in_kernel(vcpu)) 6335 return; 6336 6337 if (!kvm_x86_ops->set_apic_access_page_addr) 6338 return; 6339 6340 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6341 if (is_error_page(page)) 6342 return; 6343 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6344 6345 /* 6346 * Do not pin apic access page in memory, the MMU notifier 6347 * will call us again if it is migrated or swapped out. 6348 */ 6349 put_page(page); 6350} 6351EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6352 6353void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6354 unsigned long address) 6355{ 6356 /* 6357 * The physical address of apic access page is stored in the VMCS. 6358 * Update it when it becomes invalid. 6359 */ 6360 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6361 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6362} 6363 6364/* 6365 * Returns 1 to let vcpu_run() continue the guest execution loop without 6366 * exiting to the userspace. Otherwise, the value will be returned to the 6367 * userspace. 6368 */ 6369static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6370{ 6371 int r; 6372 bool req_int_win = 6373 dm_request_for_irq_injection(vcpu) && 6374 kvm_cpu_accept_dm_intr(vcpu); 6375 6376 bool req_immediate_exit = false; 6377 6378 if (vcpu->requests) { 6379 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6380 kvm_mmu_unload(vcpu); 6381 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6382 __kvm_migrate_timers(vcpu); 6383 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6384 kvm_gen_update_masterclock(vcpu->kvm); 6385 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6386 kvm_gen_kvmclock_update(vcpu); 6387 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6388 r = kvm_guest_time_update(vcpu); 6389 if (unlikely(r)) 6390 goto out; 6391 } 6392 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6393 kvm_mmu_sync_roots(vcpu); 6394 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6395 kvm_vcpu_flush_tlb(vcpu); 6396 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6397 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6398 r = 0; 6399 goto out; 6400 } 6401 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6402 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6403 r = 0; 6404 goto out; 6405 } 6406 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6407 vcpu->fpu_active = 0; 6408 kvm_x86_ops->fpu_deactivate(vcpu); 6409 } 6410 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6411 /* Page is swapped out. Do synthetic halt */ 6412 vcpu->arch.apf.halted = true; 6413 r = 1; 6414 goto out; 6415 } 6416 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6417 record_steal_time(vcpu); 6418 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6419 process_smi(vcpu); 6420 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6421 process_nmi(vcpu); 6422 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6423 kvm_pmu_handle_event(vcpu); 6424 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6425 kvm_pmu_deliver_pmi(vcpu); 6426 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6427 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6428 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6429 (void *) vcpu->arch.eoi_exit_bitmap)) { 6430 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6431 vcpu->run->eoi.vector = 6432 vcpu->arch.pending_ioapic_eoi; 6433 r = 0; 6434 goto out; 6435 } 6436 } 6437 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6438 vcpu_scan_ioapic(vcpu); 6439 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6440 kvm_vcpu_reload_apic_access_page(vcpu); 6441 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6442 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6443 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6444 r = 0; 6445 goto out; 6446 } 6447 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6448 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6449 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6450 r = 0; 6451 goto out; 6452 } 6453 } 6454 6455 /* 6456 * KVM_REQ_EVENT is not set when posted interrupts are set by 6457 * VT-d hardware, so we have to update RVI unconditionally. 6458 */ 6459 if (kvm_lapic_enabled(vcpu)) { 6460 /* 6461 * Update architecture specific hints for APIC 6462 * virtual interrupt delivery. 6463 */ 6464 if (kvm_x86_ops->hwapic_irr_update) 6465 kvm_x86_ops->hwapic_irr_update(vcpu, 6466 kvm_lapic_find_highest_irr(vcpu)); 6467 } 6468 6469 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6470 kvm_apic_accept_events(vcpu); 6471 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6472 r = 1; 6473 goto out; 6474 } 6475 6476 if (inject_pending_event(vcpu, req_int_win) != 0) 6477 req_immediate_exit = true; 6478 /* enable NMI/IRQ window open exits if needed */ 6479 else { 6480 if (vcpu->arch.nmi_pending) 6481 kvm_x86_ops->enable_nmi_window(vcpu); 6482 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6483 kvm_x86_ops->enable_irq_window(vcpu); 6484 } 6485 6486 if (kvm_lapic_enabled(vcpu)) { 6487 update_cr8_intercept(vcpu); 6488 kvm_lapic_sync_to_vapic(vcpu); 6489 } 6490 } 6491 6492 r = kvm_mmu_reload(vcpu); 6493 if (unlikely(r)) { 6494 goto cancel_injection; 6495 } 6496 6497 preempt_disable(); 6498 6499 kvm_x86_ops->prepare_guest_switch(vcpu); 6500 if (vcpu->fpu_active) 6501 kvm_load_guest_fpu(vcpu); 6502 vcpu->mode = IN_GUEST_MODE; 6503 6504 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6505 6506 /* We should set ->mode before check ->requests, 6507 * see the comment in make_all_cpus_request. 6508 */ 6509 smp_mb__after_srcu_read_unlock(); 6510 6511 local_irq_disable(); 6512 6513 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6514 || need_resched() || signal_pending(current)) { 6515 vcpu->mode = OUTSIDE_GUEST_MODE; 6516 smp_wmb(); 6517 local_irq_enable(); 6518 preempt_enable(); 6519 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6520 r = 1; 6521 goto cancel_injection; 6522 } 6523 6524 kvm_load_guest_xcr0(vcpu); 6525 6526 if (req_immediate_exit) 6527 smp_send_reschedule(vcpu->cpu); 6528 6529 trace_kvm_entry(vcpu->vcpu_id); 6530 wait_lapic_expire(vcpu); 6531 __kvm_guest_enter(); 6532 6533 if (unlikely(vcpu->arch.switch_db_regs)) { 6534 set_debugreg(0, 7); 6535 set_debugreg(vcpu->arch.eff_db[0], 0); 6536 set_debugreg(vcpu->arch.eff_db[1], 1); 6537 set_debugreg(vcpu->arch.eff_db[2], 2); 6538 set_debugreg(vcpu->arch.eff_db[3], 3); 6539 set_debugreg(vcpu->arch.dr6, 6); 6540 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6541 } 6542 6543 kvm_x86_ops->run(vcpu); 6544 6545 /* 6546 * Do this here before restoring debug registers on the host. And 6547 * since we do this before handling the vmexit, a DR access vmexit 6548 * can (a) read the correct value of the debug registers, (b) set 6549 * KVM_DEBUGREG_WONT_EXIT again. 6550 */ 6551 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6552 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6553 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6554 kvm_update_dr0123(vcpu); 6555 kvm_update_dr6(vcpu); 6556 kvm_update_dr7(vcpu); 6557 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6558 } 6559 6560 /* 6561 * If the guest has used debug registers, at least dr7 6562 * will be disabled while returning to the host. 6563 * If we don't have active breakpoints in the host, we don't 6564 * care about the messed up debug address registers. But if 6565 * we have some of them active, restore the old state. 6566 */ 6567 if (hw_breakpoint_active()) 6568 hw_breakpoint_restore(); 6569 6570 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 6571 6572 vcpu->mode = OUTSIDE_GUEST_MODE; 6573 smp_wmb(); 6574 6575 kvm_put_guest_xcr0(vcpu); 6576 6577 /* Interrupt is enabled by handle_external_intr() */ 6578 kvm_x86_ops->handle_external_intr(vcpu); 6579 6580 ++vcpu->stat.exits; 6581 6582 /* 6583 * We must have an instruction between local_irq_enable() and 6584 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6585 * the interrupt shadow. The stat.exits increment will do nicely. 6586 * But we need to prevent reordering, hence this barrier(): 6587 */ 6588 barrier(); 6589 6590 kvm_guest_exit(); 6591 6592 preempt_enable(); 6593 6594 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6595 6596 /* 6597 * Profile KVM exit RIPs: 6598 */ 6599 if (unlikely(prof_on == KVM_PROFILING)) { 6600 unsigned long rip = kvm_rip_read(vcpu); 6601 profile_hit(KVM_PROFILING, (void *)rip); 6602 } 6603 6604 if (unlikely(vcpu->arch.tsc_always_catchup)) 6605 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6606 6607 if (vcpu->arch.apic_attention) 6608 kvm_lapic_sync_from_vapic(vcpu); 6609 6610 r = kvm_x86_ops->handle_exit(vcpu); 6611 return r; 6612 6613cancel_injection: 6614 kvm_x86_ops->cancel_injection(vcpu); 6615 if (unlikely(vcpu->arch.apic_attention)) 6616 kvm_lapic_sync_from_vapic(vcpu); 6617out: 6618 return r; 6619} 6620 6621static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6622{ 6623 if (!kvm_arch_vcpu_runnable(vcpu) && 6624 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 6625 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6626 kvm_vcpu_block(vcpu); 6627 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6628 6629 if (kvm_x86_ops->post_block) 6630 kvm_x86_ops->post_block(vcpu); 6631 6632 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6633 return 1; 6634 } 6635 6636 kvm_apic_accept_events(vcpu); 6637 switch(vcpu->arch.mp_state) { 6638 case KVM_MP_STATE_HALTED: 6639 vcpu->arch.pv.pv_unhalted = false; 6640 vcpu->arch.mp_state = 6641 KVM_MP_STATE_RUNNABLE; 6642 case KVM_MP_STATE_RUNNABLE: 6643 vcpu->arch.apf.halted = false; 6644 break; 6645 case KVM_MP_STATE_INIT_RECEIVED: 6646 break; 6647 default: 6648 return -EINTR; 6649 break; 6650 } 6651 return 1; 6652} 6653 6654static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6655{ 6656 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6657 !vcpu->arch.apf.halted); 6658} 6659 6660static int vcpu_run(struct kvm_vcpu *vcpu) 6661{ 6662 int r; 6663 struct kvm *kvm = vcpu->kvm; 6664 6665 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6666 6667 for (;;) { 6668 if (kvm_vcpu_running(vcpu)) { 6669 r = vcpu_enter_guest(vcpu); 6670 } else { 6671 r = vcpu_block(kvm, vcpu); 6672 } 6673 6674 if (r <= 0) 6675 break; 6676 6677 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6678 if (kvm_cpu_has_pending_timer(vcpu)) 6679 kvm_inject_pending_timer_irqs(vcpu); 6680 6681 if (dm_request_for_irq_injection(vcpu) && 6682 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 6683 r = 0; 6684 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 6685 ++vcpu->stat.request_irq_exits; 6686 break; 6687 } 6688 6689 kvm_check_async_pf_completion(vcpu); 6690 6691 if (signal_pending(current)) { 6692 r = -EINTR; 6693 vcpu->run->exit_reason = KVM_EXIT_INTR; 6694 ++vcpu->stat.signal_exits; 6695 break; 6696 } 6697 if (need_resched()) { 6698 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6699 cond_resched(); 6700 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6701 } 6702 } 6703 6704 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6705 6706 return r; 6707} 6708 6709static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6710{ 6711 int r; 6712 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6713 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6714 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6715 if (r != EMULATE_DONE) 6716 return 0; 6717 return 1; 6718} 6719 6720static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6721{ 6722 BUG_ON(!vcpu->arch.pio.count); 6723 6724 return complete_emulated_io(vcpu); 6725} 6726 6727/* 6728 * Implements the following, as a state machine: 6729 * 6730 * read: 6731 * for each fragment 6732 * for each mmio piece in the fragment 6733 * write gpa, len 6734 * exit 6735 * copy data 6736 * execute insn 6737 * 6738 * write: 6739 * for each fragment 6740 * for each mmio piece in the fragment 6741 * write gpa, len 6742 * copy data 6743 * exit 6744 */ 6745static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6746{ 6747 struct kvm_run *run = vcpu->run; 6748 struct kvm_mmio_fragment *frag; 6749 unsigned len; 6750 6751 BUG_ON(!vcpu->mmio_needed); 6752 6753 /* Complete previous fragment */ 6754 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6755 len = min(8u, frag->len); 6756 if (!vcpu->mmio_is_write) 6757 memcpy(frag->data, run->mmio.data, len); 6758 6759 if (frag->len <= 8) { 6760 /* Switch to the next fragment. */ 6761 frag++; 6762 vcpu->mmio_cur_fragment++; 6763 } else { 6764 /* Go forward to the next mmio piece. */ 6765 frag->data += len; 6766 frag->gpa += len; 6767 frag->len -= len; 6768 } 6769 6770 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6771 vcpu->mmio_needed = 0; 6772 6773 /* FIXME: return into emulator if single-stepping. */ 6774 if (vcpu->mmio_is_write) 6775 return 1; 6776 vcpu->mmio_read_completed = 1; 6777 return complete_emulated_io(vcpu); 6778 } 6779 6780 run->exit_reason = KVM_EXIT_MMIO; 6781 run->mmio.phys_addr = frag->gpa; 6782 if (vcpu->mmio_is_write) 6783 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6784 run->mmio.len = min(8u, frag->len); 6785 run->mmio.is_write = vcpu->mmio_is_write; 6786 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6787 return 0; 6788} 6789 6790 6791int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6792{ 6793 struct fpu *fpu = ¤t->thread.fpu; 6794 int r; 6795 sigset_t sigsaved; 6796 6797 fpu__activate_curr(fpu); 6798 6799 if (vcpu->sigset_active) 6800 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6801 6802 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6803 kvm_vcpu_block(vcpu); 6804 kvm_apic_accept_events(vcpu); 6805 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6806 r = -EAGAIN; 6807 goto out; 6808 } 6809 6810 /* re-sync apic's tpr */ 6811 if (!lapic_in_kernel(vcpu)) { 6812 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6813 r = -EINVAL; 6814 goto out; 6815 } 6816 } 6817 6818 if (unlikely(vcpu->arch.complete_userspace_io)) { 6819 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6820 vcpu->arch.complete_userspace_io = NULL; 6821 r = cui(vcpu); 6822 if (r <= 0) 6823 goto out; 6824 } else 6825 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6826 6827 r = vcpu_run(vcpu); 6828 6829out: 6830 post_kvm_run_save(vcpu); 6831 if (vcpu->sigset_active) 6832 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6833 6834 return r; 6835} 6836 6837int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6838{ 6839 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6840 /* 6841 * We are here if userspace calls get_regs() in the middle of 6842 * instruction emulation. Registers state needs to be copied 6843 * back from emulation context to vcpu. Userspace shouldn't do 6844 * that usually, but some bad designed PV devices (vmware 6845 * backdoor interface) need this to work 6846 */ 6847 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6848 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6849 } 6850 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6851 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6852 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6853 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6854 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6855 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6856 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6857 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6858#ifdef CONFIG_X86_64 6859 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6860 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6861 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6862 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6863 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6864 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6865 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6866 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6867#endif 6868 6869 regs->rip = kvm_rip_read(vcpu); 6870 regs->rflags = kvm_get_rflags(vcpu); 6871 6872 return 0; 6873} 6874 6875int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6876{ 6877 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6878 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6879 6880 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6881 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6882 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6883 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6884 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6885 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6886 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6887 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6888#ifdef CONFIG_X86_64 6889 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6890 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6891 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6892 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6893 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6894 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6895 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6896 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6897#endif 6898 6899 kvm_rip_write(vcpu, regs->rip); 6900 kvm_set_rflags(vcpu, regs->rflags); 6901 6902 vcpu->arch.exception.pending = false; 6903 6904 kvm_make_request(KVM_REQ_EVENT, vcpu); 6905 6906 return 0; 6907} 6908 6909void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6910{ 6911 struct kvm_segment cs; 6912 6913 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6914 *db = cs.db; 6915 *l = cs.l; 6916} 6917EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6918 6919int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6920 struct kvm_sregs *sregs) 6921{ 6922 struct desc_ptr dt; 6923 6924 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6925 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6926 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6927 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6928 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6929 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6930 6931 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6932 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6933 6934 kvm_x86_ops->get_idt(vcpu, &dt); 6935 sregs->idt.limit = dt.size; 6936 sregs->idt.base = dt.address; 6937 kvm_x86_ops->get_gdt(vcpu, &dt); 6938 sregs->gdt.limit = dt.size; 6939 sregs->gdt.base = dt.address; 6940 6941 sregs->cr0 = kvm_read_cr0(vcpu); 6942 sregs->cr2 = vcpu->arch.cr2; 6943 sregs->cr3 = kvm_read_cr3(vcpu); 6944 sregs->cr4 = kvm_read_cr4(vcpu); 6945 sregs->cr8 = kvm_get_cr8(vcpu); 6946 sregs->efer = vcpu->arch.efer; 6947 sregs->apic_base = kvm_get_apic_base(vcpu); 6948 6949 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6950 6951 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6952 set_bit(vcpu->arch.interrupt.nr, 6953 (unsigned long *)sregs->interrupt_bitmap); 6954 6955 return 0; 6956} 6957 6958int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6959 struct kvm_mp_state *mp_state) 6960{ 6961 kvm_apic_accept_events(vcpu); 6962 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6963 vcpu->arch.pv.pv_unhalted) 6964 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6965 else 6966 mp_state->mp_state = vcpu->arch.mp_state; 6967 6968 return 0; 6969} 6970 6971int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6972 struct kvm_mp_state *mp_state) 6973{ 6974 if (!kvm_vcpu_has_lapic(vcpu) && 6975 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6976 return -EINVAL; 6977 6978 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6979 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6980 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6981 } else 6982 vcpu->arch.mp_state = mp_state->mp_state; 6983 kvm_make_request(KVM_REQ_EVENT, vcpu); 6984 return 0; 6985} 6986 6987int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6988 int reason, bool has_error_code, u32 error_code) 6989{ 6990 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6991 int ret; 6992 6993 init_emulate_ctxt(vcpu); 6994 6995 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6996 has_error_code, error_code); 6997 6998 if (ret) 6999 return EMULATE_FAIL; 7000 7001 kvm_rip_write(vcpu, ctxt->eip); 7002 kvm_set_rflags(vcpu, ctxt->eflags); 7003 kvm_make_request(KVM_REQ_EVENT, vcpu); 7004 return EMULATE_DONE; 7005} 7006EXPORT_SYMBOL_GPL(kvm_task_switch); 7007 7008int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7009 struct kvm_sregs *sregs) 7010{ 7011 struct msr_data apic_base_msr; 7012 int mmu_reset_needed = 0; 7013 int pending_vec, max_bits, idx; 7014 struct desc_ptr dt; 7015 7016 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 7017 return -EINVAL; 7018 7019 dt.size = sregs->idt.limit; 7020 dt.address = sregs->idt.base; 7021 kvm_x86_ops->set_idt(vcpu, &dt); 7022 dt.size = sregs->gdt.limit; 7023 dt.address = sregs->gdt.base; 7024 kvm_x86_ops->set_gdt(vcpu, &dt); 7025 7026 vcpu->arch.cr2 = sregs->cr2; 7027 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7028 vcpu->arch.cr3 = sregs->cr3; 7029 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7030 7031 kvm_set_cr8(vcpu, sregs->cr8); 7032 7033 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7034 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7035 apic_base_msr.data = sregs->apic_base; 7036 apic_base_msr.host_initiated = true; 7037 kvm_set_apic_base(vcpu, &apic_base_msr); 7038 7039 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7040 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7041 vcpu->arch.cr0 = sregs->cr0; 7042 7043 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7044 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7045 if (sregs->cr4 & X86_CR4_OSXSAVE) 7046 kvm_update_cpuid(vcpu); 7047 7048 idx = srcu_read_lock(&vcpu->kvm->srcu); 7049 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7050 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7051 mmu_reset_needed = 1; 7052 } 7053 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7054 7055 if (mmu_reset_needed) 7056 kvm_mmu_reset_context(vcpu); 7057 7058 max_bits = KVM_NR_INTERRUPTS; 7059 pending_vec = find_first_bit( 7060 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7061 if (pending_vec < max_bits) { 7062 kvm_queue_interrupt(vcpu, pending_vec, false); 7063 pr_debug("Set back pending irq %d\n", pending_vec); 7064 } 7065 7066 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7067 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7068 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7069 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7070 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7071 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7072 7073 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7074 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7075 7076 update_cr8_intercept(vcpu); 7077 7078 /* Older userspace won't unhalt the vcpu on reset. */ 7079 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7080 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7081 !is_protmode(vcpu)) 7082 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7083 7084 kvm_make_request(KVM_REQ_EVENT, vcpu); 7085 7086 return 0; 7087} 7088 7089int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7090 struct kvm_guest_debug *dbg) 7091{ 7092 unsigned long rflags; 7093 int i, r; 7094 7095 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7096 r = -EBUSY; 7097 if (vcpu->arch.exception.pending) 7098 goto out; 7099 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7100 kvm_queue_exception(vcpu, DB_VECTOR); 7101 else 7102 kvm_queue_exception(vcpu, BP_VECTOR); 7103 } 7104 7105 /* 7106 * Read rflags as long as potentially injected trace flags are still 7107 * filtered out. 7108 */ 7109 rflags = kvm_get_rflags(vcpu); 7110 7111 vcpu->guest_debug = dbg->control; 7112 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7113 vcpu->guest_debug = 0; 7114 7115 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7116 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7117 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7118 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7119 } else { 7120 for (i = 0; i < KVM_NR_DB_REGS; i++) 7121 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7122 } 7123 kvm_update_dr7(vcpu); 7124 7125 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7126 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7127 get_segment_base(vcpu, VCPU_SREG_CS); 7128 7129 /* 7130 * Trigger an rflags update that will inject or remove the trace 7131 * flags. 7132 */ 7133 kvm_set_rflags(vcpu, rflags); 7134 7135 kvm_x86_ops->update_bp_intercept(vcpu); 7136 7137 r = 0; 7138 7139out: 7140 7141 return r; 7142} 7143 7144/* 7145 * Translate a guest virtual address to a guest physical address. 7146 */ 7147int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7148 struct kvm_translation *tr) 7149{ 7150 unsigned long vaddr = tr->linear_address; 7151 gpa_t gpa; 7152 int idx; 7153 7154 idx = srcu_read_lock(&vcpu->kvm->srcu); 7155 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7156 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7157 tr->physical_address = gpa; 7158 tr->valid = gpa != UNMAPPED_GVA; 7159 tr->writeable = 1; 7160 tr->usermode = 0; 7161 7162 return 0; 7163} 7164 7165int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7166{ 7167 struct fxregs_state *fxsave = 7168 &vcpu->arch.guest_fpu.state.fxsave; 7169 7170 memcpy(fpu->fpr, fxsave->st_space, 128); 7171 fpu->fcw = fxsave->cwd; 7172 fpu->fsw = fxsave->swd; 7173 fpu->ftwx = fxsave->twd; 7174 fpu->last_opcode = fxsave->fop; 7175 fpu->last_ip = fxsave->rip; 7176 fpu->last_dp = fxsave->rdp; 7177 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7178 7179 return 0; 7180} 7181 7182int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7183{ 7184 struct fxregs_state *fxsave = 7185 &vcpu->arch.guest_fpu.state.fxsave; 7186 7187 memcpy(fxsave->st_space, fpu->fpr, 128); 7188 fxsave->cwd = fpu->fcw; 7189 fxsave->swd = fpu->fsw; 7190 fxsave->twd = fpu->ftwx; 7191 fxsave->fop = fpu->last_opcode; 7192 fxsave->rip = fpu->last_ip; 7193 fxsave->rdp = fpu->last_dp; 7194 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7195 7196 return 0; 7197} 7198 7199static void fx_init(struct kvm_vcpu *vcpu) 7200{ 7201 fpstate_init(&vcpu->arch.guest_fpu.state); 7202 if (cpu_has_xsaves) 7203 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7204 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7205 7206 /* 7207 * Ensure guest xcr0 is valid for loading 7208 */ 7209 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7210 7211 vcpu->arch.cr0 |= X86_CR0_ET; 7212} 7213 7214void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7215{ 7216 if (vcpu->guest_fpu_loaded) 7217 return; 7218 7219 /* 7220 * Restore all possible states in the guest, 7221 * and assume host would use all available bits. 7222 * Guest xcr0 would be loaded later. 7223 */ 7224 vcpu->guest_fpu_loaded = 1; 7225 __kernel_fpu_begin(); 7226 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7227 trace_kvm_fpu(1); 7228} 7229 7230void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7231{ 7232 if (!vcpu->guest_fpu_loaded) { 7233 vcpu->fpu_counter = 0; 7234 return; 7235 } 7236 7237 vcpu->guest_fpu_loaded = 0; 7238 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7239 __kernel_fpu_end(); 7240 ++vcpu->stat.fpu_reload; 7241 /* 7242 * If using eager FPU mode, or if the guest is a frequent user 7243 * of the FPU, just leave the FPU active for next time. 7244 * Every 255 times fpu_counter rolls over to 0; a guest that uses 7245 * the FPU in bursts will revert to loading it on demand. 7246 */ 7247 if (!vcpu->arch.eager_fpu) { 7248 if (++vcpu->fpu_counter < 5) 7249 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7250 } 7251 trace_kvm_fpu(0); 7252} 7253 7254void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7255{ 7256 kvmclock_reset(vcpu); 7257 7258 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7259 kvm_x86_ops->vcpu_free(vcpu); 7260} 7261 7262struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7263 unsigned int id) 7264{ 7265 struct kvm_vcpu *vcpu; 7266 7267 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7268 printk_once(KERN_WARNING 7269 "kvm: SMP vm created on host with unstable TSC; " 7270 "guest TSC will not be reliable\n"); 7271 7272 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7273 7274 return vcpu; 7275} 7276 7277int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7278{ 7279 int r; 7280 7281 kvm_vcpu_mtrr_init(vcpu); 7282 r = vcpu_load(vcpu); 7283 if (r) 7284 return r; 7285 kvm_vcpu_reset(vcpu, false); 7286 kvm_mmu_setup(vcpu); 7287 vcpu_put(vcpu); 7288 return r; 7289} 7290 7291void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7292{ 7293 struct msr_data msr; 7294 struct kvm *kvm = vcpu->kvm; 7295 7296 if (vcpu_load(vcpu)) 7297 return; 7298 msr.data = 0x0; 7299 msr.index = MSR_IA32_TSC; 7300 msr.host_initiated = true; 7301 kvm_write_tsc(vcpu, &msr); 7302 vcpu_put(vcpu); 7303 7304 if (!kvmclock_periodic_sync) 7305 return; 7306 7307 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7308 KVMCLOCK_SYNC_PERIOD); 7309} 7310 7311void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7312{ 7313 int r; 7314 vcpu->arch.apf.msr_val = 0; 7315 7316 r = vcpu_load(vcpu); 7317 BUG_ON(r); 7318 kvm_mmu_unload(vcpu); 7319 vcpu_put(vcpu); 7320 7321 kvm_x86_ops->vcpu_free(vcpu); 7322} 7323 7324void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7325{ 7326 vcpu->arch.hflags = 0; 7327 7328 atomic_set(&vcpu->arch.nmi_queued, 0); 7329 vcpu->arch.nmi_pending = 0; 7330 vcpu->arch.nmi_injected = false; 7331 kvm_clear_interrupt_queue(vcpu); 7332 kvm_clear_exception_queue(vcpu); 7333 7334 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7335 kvm_update_dr0123(vcpu); 7336 vcpu->arch.dr6 = DR6_INIT; 7337 kvm_update_dr6(vcpu); 7338 vcpu->arch.dr7 = DR7_FIXED_1; 7339 kvm_update_dr7(vcpu); 7340 7341 vcpu->arch.cr2 = 0; 7342 7343 kvm_make_request(KVM_REQ_EVENT, vcpu); 7344 vcpu->arch.apf.msr_val = 0; 7345 vcpu->arch.st.msr_val = 0; 7346 7347 kvmclock_reset(vcpu); 7348 7349 kvm_clear_async_pf_completion_queue(vcpu); 7350 kvm_async_pf_hash_reset(vcpu); 7351 vcpu->arch.apf.halted = false; 7352 7353 if (!init_event) { 7354 kvm_pmu_reset(vcpu); 7355 vcpu->arch.smbase = 0x30000; 7356 } 7357 7358 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7359 vcpu->arch.regs_avail = ~0; 7360 vcpu->arch.regs_dirty = ~0; 7361 7362 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7363} 7364 7365void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7366{ 7367 struct kvm_segment cs; 7368 7369 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7370 cs.selector = vector << 8; 7371 cs.base = vector << 12; 7372 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7373 kvm_rip_write(vcpu, 0); 7374} 7375 7376int kvm_arch_hardware_enable(void) 7377{ 7378 struct kvm *kvm; 7379 struct kvm_vcpu *vcpu; 7380 int i; 7381 int ret; 7382 u64 local_tsc; 7383 u64 max_tsc = 0; 7384 bool stable, backwards_tsc = false; 7385 7386 kvm_shared_msr_cpu_online(); 7387 ret = kvm_x86_ops->hardware_enable(); 7388 if (ret != 0) 7389 return ret; 7390 7391 local_tsc = rdtsc(); 7392 stable = !check_tsc_unstable(); 7393 list_for_each_entry(kvm, &vm_list, vm_list) { 7394 kvm_for_each_vcpu(i, vcpu, kvm) { 7395 if (!stable && vcpu->cpu == smp_processor_id()) 7396 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7397 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7398 backwards_tsc = true; 7399 if (vcpu->arch.last_host_tsc > max_tsc) 7400 max_tsc = vcpu->arch.last_host_tsc; 7401 } 7402 } 7403 } 7404 7405 /* 7406 * Sometimes, even reliable TSCs go backwards. This happens on 7407 * platforms that reset TSC during suspend or hibernate actions, but 7408 * maintain synchronization. We must compensate. Fortunately, we can 7409 * detect that condition here, which happens early in CPU bringup, 7410 * before any KVM threads can be running. Unfortunately, we can't 7411 * bring the TSCs fully up to date with real time, as we aren't yet far 7412 * enough into CPU bringup that we know how much real time has actually 7413 * elapsed; our helper function, get_kernel_ns() will be using boot 7414 * variables that haven't been updated yet. 7415 * 7416 * So we simply find the maximum observed TSC above, then record the 7417 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7418 * the adjustment will be applied. Note that we accumulate 7419 * adjustments, in case multiple suspend cycles happen before some VCPU 7420 * gets a chance to run again. In the event that no KVM threads get a 7421 * chance to run, we will miss the entire elapsed period, as we'll have 7422 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7423 * loose cycle time. This isn't too big a deal, since the loss will be 7424 * uniform across all VCPUs (not to mention the scenario is extremely 7425 * unlikely). It is possible that a second hibernate recovery happens 7426 * much faster than a first, causing the observed TSC here to be 7427 * smaller; this would require additional padding adjustment, which is 7428 * why we set last_host_tsc to the local tsc observed here. 7429 * 7430 * N.B. - this code below runs only on platforms with reliable TSC, 7431 * as that is the only way backwards_tsc is set above. Also note 7432 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7433 * have the same delta_cyc adjustment applied if backwards_tsc 7434 * is detected. Note further, this adjustment is only done once, 7435 * as we reset last_host_tsc on all VCPUs to stop this from being 7436 * called multiple times (one for each physical CPU bringup). 7437 * 7438 * Platforms with unreliable TSCs don't have to deal with this, they 7439 * will be compensated by the logic in vcpu_load, which sets the TSC to 7440 * catchup mode. This will catchup all VCPUs to real time, but cannot 7441 * guarantee that they stay in perfect synchronization. 7442 */ 7443 if (backwards_tsc) { 7444 u64 delta_cyc = max_tsc - local_tsc; 7445 backwards_tsc_observed = true; 7446 list_for_each_entry(kvm, &vm_list, vm_list) { 7447 kvm_for_each_vcpu(i, vcpu, kvm) { 7448 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7449 vcpu->arch.last_host_tsc = local_tsc; 7450 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7451 } 7452 7453 /* 7454 * We have to disable TSC offset matching.. if you were 7455 * booting a VM while issuing an S4 host suspend.... 7456 * you may have some problem. Solving this issue is 7457 * left as an exercise to the reader. 7458 */ 7459 kvm->arch.last_tsc_nsec = 0; 7460 kvm->arch.last_tsc_write = 0; 7461 } 7462 7463 } 7464 return 0; 7465} 7466 7467void kvm_arch_hardware_disable(void) 7468{ 7469 kvm_x86_ops->hardware_disable(); 7470 drop_user_return_notifiers(); 7471} 7472 7473int kvm_arch_hardware_setup(void) 7474{ 7475 int r; 7476 7477 r = kvm_x86_ops->hardware_setup(); 7478 if (r != 0) 7479 return r; 7480 7481 if (kvm_has_tsc_control) { 7482 /* 7483 * Make sure the user can only configure tsc_khz values that 7484 * fit into a signed integer. 7485 * A min value is not calculated needed because it will always 7486 * be 1 on all machines. 7487 */ 7488 u64 max = min(0x7fffffffULL, 7489 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 7490 kvm_max_guest_tsc_khz = max; 7491 7492 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 7493 } 7494 7495 kvm_init_msr_list(); 7496 return 0; 7497} 7498 7499void kvm_arch_hardware_unsetup(void) 7500{ 7501 kvm_x86_ops->hardware_unsetup(); 7502} 7503 7504void kvm_arch_check_processor_compat(void *rtn) 7505{ 7506 kvm_x86_ops->check_processor_compatibility(rtn); 7507} 7508 7509bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7510{ 7511 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7512} 7513EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7514 7515bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7516{ 7517 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7518} 7519 7520bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7521{ 7522 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu); 7523} 7524 7525struct static_key kvm_no_apic_vcpu __read_mostly; 7526 7527int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7528{ 7529 struct page *page; 7530 struct kvm *kvm; 7531 int r; 7532 7533 BUG_ON(vcpu->kvm == NULL); 7534 kvm = vcpu->kvm; 7535 7536 vcpu->arch.pv.pv_unhalted = false; 7537 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7538 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7539 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7540 else 7541 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7542 7543 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7544 if (!page) { 7545 r = -ENOMEM; 7546 goto fail; 7547 } 7548 vcpu->arch.pio_data = page_address(page); 7549 7550 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7551 7552 r = kvm_mmu_create(vcpu); 7553 if (r < 0) 7554 goto fail_free_pio_data; 7555 7556 if (irqchip_in_kernel(kvm)) { 7557 r = kvm_create_lapic(vcpu); 7558 if (r < 0) 7559 goto fail_mmu_destroy; 7560 } else 7561 static_key_slow_inc(&kvm_no_apic_vcpu); 7562 7563 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7564 GFP_KERNEL); 7565 if (!vcpu->arch.mce_banks) { 7566 r = -ENOMEM; 7567 goto fail_free_lapic; 7568 } 7569 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7570 7571 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7572 r = -ENOMEM; 7573 goto fail_free_mce_banks; 7574 } 7575 7576 fx_init(vcpu); 7577 7578 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7579 vcpu->arch.pv_time_enabled = false; 7580 7581 vcpu->arch.guest_supported_xcr0 = 0; 7582 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7583 7584 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7585 7586 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7587 7588 kvm_async_pf_hash_reset(vcpu); 7589 kvm_pmu_init(vcpu); 7590 7591 vcpu->arch.pending_external_vector = -1; 7592 7593 return 0; 7594 7595fail_free_mce_banks: 7596 kfree(vcpu->arch.mce_banks); 7597fail_free_lapic: 7598 kvm_free_lapic(vcpu); 7599fail_mmu_destroy: 7600 kvm_mmu_destroy(vcpu); 7601fail_free_pio_data: 7602 free_page((unsigned long)vcpu->arch.pio_data); 7603fail: 7604 return r; 7605} 7606 7607void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7608{ 7609 int idx; 7610 7611 kvm_pmu_destroy(vcpu); 7612 kfree(vcpu->arch.mce_banks); 7613 kvm_free_lapic(vcpu); 7614 idx = srcu_read_lock(&vcpu->kvm->srcu); 7615 kvm_mmu_destroy(vcpu); 7616 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7617 free_page((unsigned long)vcpu->arch.pio_data); 7618 if (!lapic_in_kernel(vcpu)) 7619 static_key_slow_dec(&kvm_no_apic_vcpu); 7620} 7621 7622void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7623{ 7624 kvm_x86_ops->sched_in(vcpu, cpu); 7625} 7626 7627int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7628{ 7629 if (type) 7630 return -EINVAL; 7631 7632 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7633 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7634 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7635 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7636 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7637 7638 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7639 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7640 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7641 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7642 &kvm->arch.irq_sources_bitmap); 7643 7644 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7645 mutex_init(&kvm->arch.apic_map_lock); 7646 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7647 7648 pvclock_update_vm_gtod_copy(kvm); 7649 7650 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7651 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7652 7653 return 0; 7654} 7655 7656static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7657{ 7658 int r; 7659 r = vcpu_load(vcpu); 7660 BUG_ON(r); 7661 kvm_mmu_unload(vcpu); 7662 vcpu_put(vcpu); 7663} 7664 7665static void kvm_free_vcpus(struct kvm *kvm) 7666{ 7667 unsigned int i; 7668 struct kvm_vcpu *vcpu; 7669 7670 /* 7671 * Unpin any mmu pages first. 7672 */ 7673 kvm_for_each_vcpu(i, vcpu, kvm) { 7674 kvm_clear_async_pf_completion_queue(vcpu); 7675 kvm_unload_vcpu_mmu(vcpu); 7676 } 7677 kvm_for_each_vcpu(i, vcpu, kvm) 7678 kvm_arch_vcpu_free(vcpu); 7679 7680 mutex_lock(&kvm->lock); 7681 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7682 kvm->vcpus[i] = NULL; 7683 7684 atomic_set(&kvm->online_vcpus, 0); 7685 mutex_unlock(&kvm->lock); 7686} 7687 7688void kvm_arch_sync_events(struct kvm *kvm) 7689{ 7690 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7691 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7692 kvm_free_all_assigned_devices(kvm); 7693 kvm_free_pit(kvm); 7694} 7695 7696int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7697{ 7698 int i, r; 7699 unsigned long hva; 7700 struct kvm_memslots *slots = kvm_memslots(kvm); 7701 struct kvm_memory_slot *slot, old; 7702 7703 /* Called with kvm->slots_lock held. */ 7704 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7705 return -EINVAL; 7706 7707 slot = id_to_memslot(slots, id); 7708 if (size) { 7709 if (WARN_ON(slot->npages)) 7710 return -EEXIST; 7711 7712 /* 7713 * MAP_SHARED to prevent internal slot pages from being moved 7714 * by fork()/COW. 7715 */ 7716 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7717 MAP_SHARED | MAP_ANONYMOUS, 0); 7718 if (IS_ERR((void *)hva)) 7719 return PTR_ERR((void *)hva); 7720 } else { 7721 if (!slot->npages) 7722 return 0; 7723 7724 hva = 0; 7725 } 7726 7727 old = *slot; 7728 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 7729 struct kvm_userspace_memory_region m; 7730 7731 m.slot = id | (i << 16); 7732 m.flags = 0; 7733 m.guest_phys_addr = gpa; 7734 m.userspace_addr = hva; 7735 m.memory_size = size; 7736 r = __kvm_set_memory_region(kvm, &m); 7737 if (r < 0) 7738 return r; 7739 } 7740 7741 if (!size) { 7742 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 7743 WARN_ON(r < 0); 7744 } 7745 7746 return 0; 7747} 7748EXPORT_SYMBOL_GPL(__x86_set_memory_region); 7749 7750int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7751{ 7752 int r; 7753 7754 mutex_lock(&kvm->slots_lock); 7755 r = __x86_set_memory_region(kvm, id, gpa, size); 7756 mutex_unlock(&kvm->slots_lock); 7757 7758 return r; 7759} 7760EXPORT_SYMBOL_GPL(x86_set_memory_region); 7761 7762void kvm_arch_destroy_vm(struct kvm *kvm) 7763{ 7764 if (current->mm == kvm->mm) { 7765 /* 7766 * Free memory regions allocated on behalf of userspace, 7767 * unless the the memory map has changed due to process exit 7768 * or fd copying. 7769 */ 7770 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 7771 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 7772 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 7773 } 7774 kvm_iommu_unmap_guest(kvm); 7775 kfree(kvm->arch.vpic); 7776 kfree(kvm->arch.vioapic); 7777 kvm_free_vcpus(kvm); 7778 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7779} 7780 7781void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7782 struct kvm_memory_slot *dont) 7783{ 7784 int i; 7785 7786 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7787 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7788 kvfree(free->arch.rmap[i]); 7789 free->arch.rmap[i] = NULL; 7790 } 7791 if (i == 0) 7792 continue; 7793 7794 if (!dont || free->arch.lpage_info[i - 1] != 7795 dont->arch.lpage_info[i - 1]) { 7796 kvfree(free->arch.lpage_info[i - 1]); 7797 free->arch.lpage_info[i - 1] = NULL; 7798 } 7799 } 7800} 7801 7802int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7803 unsigned long npages) 7804{ 7805 int i; 7806 7807 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7808 unsigned long ugfn; 7809 int lpages; 7810 int level = i + 1; 7811 7812 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7813 slot->base_gfn, level) + 1; 7814 7815 slot->arch.rmap[i] = 7816 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7817 if (!slot->arch.rmap[i]) 7818 goto out_free; 7819 if (i == 0) 7820 continue; 7821 7822 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7823 sizeof(*slot->arch.lpage_info[i - 1])); 7824 if (!slot->arch.lpage_info[i - 1]) 7825 goto out_free; 7826 7827 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7828 slot->arch.lpage_info[i - 1][0].write_count = 1; 7829 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7830 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7831 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7832 /* 7833 * If the gfn and userspace address are not aligned wrt each 7834 * other, or if explicitly asked to, disable large page 7835 * support for this slot 7836 */ 7837 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7838 !kvm_largepages_enabled()) { 7839 unsigned long j; 7840 7841 for (j = 0; j < lpages; ++j) 7842 slot->arch.lpage_info[i - 1][j].write_count = 1; 7843 } 7844 } 7845 7846 return 0; 7847 7848out_free: 7849 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7850 kvfree(slot->arch.rmap[i]); 7851 slot->arch.rmap[i] = NULL; 7852 if (i == 0) 7853 continue; 7854 7855 kvfree(slot->arch.lpage_info[i - 1]); 7856 slot->arch.lpage_info[i - 1] = NULL; 7857 } 7858 return -ENOMEM; 7859} 7860 7861void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 7862{ 7863 /* 7864 * memslots->generation has been incremented. 7865 * mmio generation may have reached its maximum value. 7866 */ 7867 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 7868} 7869 7870int kvm_arch_prepare_memory_region(struct kvm *kvm, 7871 struct kvm_memory_slot *memslot, 7872 const struct kvm_userspace_memory_region *mem, 7873 enum kvm_mr_change change) 7874{ 7875 return 0; 7876} 7877 7878static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7879 struct kvm_memory_slot *new) 7880{ 7881 /* Still write protect RO slot */ 7882 if (new->flags & KVM_MEM_READONLY) { 7883 kvm_mmu_slot_remove_write_access(kvm, new); 7884 return; 7885 } 7886 7887 /* 7888 * Call kvm_x86_ops dirty logging hooks when they are valid. 7889 * 7890 * kvm_x86_ops->slot_disable_log_dirty is called when: 7891 * 7892 * - KVM_MR_CREATE with dirty logging is disabled 7893 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7894 * 7895 * The reason is, in case of PML, we need to set D-bit for any slots 7896 * with dirty logging disabled in order to eliminate unnecessary GPA 7897 * logging in PML buffer (and potential PML buffer full VMEXT). This 7898 * guarantees leaving PML enabled during guest's lifetime won't have 7899 * any additonal overhead from PML when guest is running with dirty 7900 * logging disabled for memory slots. 7901 * 7902 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7903 * to dirty logging mode. 7904 * 7905 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7906 * 7907 * In case of write protect: 7908 * 7909 * Write protect all pages for dirty logging. 7910 * 7911 * All the sptes including the large sptes which point to this 7912 * slot are set to readonly. We can not create any new large 7913 * spte on this slot until the end of the logging. 7914 * 7915 * See the comments in fast_page_fault(). 7916 */ 7917 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7918 if (kvm_x86_ops->slot_enable_log_dirty) 7919 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7920 else 7921 kvm_mmu_slot_remove_write_access(kvm, new); 7922 } else { 7923 if (kvm_x86_ops->slot_disable_log_dirty) 7924 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 7925 } 7926} 7927 7928void kvm_arch_commit_memory_region(struct kvm *kvm, 7929 const struct kvm_userspace_memory_region *mem, 7930 const struct kvm_memory_slot *old, 7931 const struct kvm_memory_slot *new, 7932 enum kvm_mr_change change) 7933{ 7934 int nr_mmu_pages = 0; 7935 7936 if (!kvm->arch.n_requested_mmu_pages) 7937 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7938 7939 if (nr_mmu_pages) 7940 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7941 7942 /* 7943 * Dirty logging tracks sptes in 4k granularity, meaning that large 7944 * sptes have to be split. If live migration is successful, the guest 7945 * in the source machine will be destroyed and large sptes will be 7946 * created in the destination. However, if the guest continues to run 7947 * in the source machine (for example if live migration fails), small 7948 * sptes will remain around and cause bad performance. 7949 * 7950 * Scan sptes if dirty logging has been stopped, dropping those 7951 * which can be collapsed into a single large-page spte. Later 7952 * page faults will create the large-page sptes. 7953 */ 7954 if ((change != KVM_MR_DELETE) && 7955 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 7956 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7957 kvm_mmu_zap_collapsible_sptes(kvm, new); 7958 7959 /* 7960 * Set up write protection and/or dirty logging for the new slot. 7961 * 7962 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 7963 * been zapped so no dirty logging staff is needed for old slot. For 7964 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 7965 * new and it's also covered when dealing with the new slot. 7966 * 7967 * FIXME: const-ify all uses of struct kvm_memory_slot. 7968 */ 7969 if (change != KVM_MR_DELETE) 7970 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 7971} 7972 7973void kvm_arch_flush_shadow_all(struct kvm *kvm) 7974{ 7975 kvm_mmu_invalidate_zap_all_pages(kvm); 7976} 7977 7978void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7979 struct kvm_memory_slot *slot) 7980{ 7981 kvm_mmu_invalidate_zap_all_pages(kvm); 7982} 7983 7984static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 7985{ 7986 if (!list_empty_careful(&vcpu->async_pf.done)) 7987 return true; 7988 7989 if (kvm_apic_has_events(vcpu)) 7990 return true; 7991 7992 if (vcpu->arch.pv.pv_unhalted) 7993 return true; 7994 7995 if (atomic_read(&vcpu->arch.nmi_queued)) 7996 return true; 7997 7998 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 7999 return true; 8000 8001 if (kvm_arch_interrupt_allowed(vcpu) && 8002 kvm_cpu_has_interrupt(vcpu)) 8003 return true; 8004 8005 return false; 8006} 8007 8008int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8009{ 8010 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8011 kvm_x86_ops->check_nested_events(vcpu, false); 8012 8013 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8014} 8015 8016int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8017{ 8018 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8019} 8020 8021int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8022{ 8023 return kvm_x86_ops->interrupt_allowed(vcpu); 8024} 8025 8026unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8027{ 8028 if (is_64_bit_mode(vcpu)) 8029 return kvm_rip_read(vcpu); 8030 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8031 kvm_rip_read(vcpu)); 8032} 8033EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8034 8035bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8036{ 8037 return kvm_get_linear_rip(vcpu) == linear_rip; 8038} 8039EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8040 8041unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8042{ 8043 unsigned long rflags; 8044 8045 rflags = kvm_x86_ops->get_rflags(vcpu); 8046 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8047 rflags &= ~X86_EFLAGS_TF; 8048 return rflags; 8049} 8050EXPORT_SYMBOL_GPL(kvm_get_rflags); 8051 8052static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8053{ 8054 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8055 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8056 rflags |= X86_EFLAGS_TF; 8057 kvm_x86_ops->set_rflags(vcpu, rflags); 8058} 8059 8060void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8061{ 8062 __kvm_set_rflags(vcpu, rflags); 8063 kvm_make_request(KVM_REQ_EVENT, vcpu); 8064} 8065EXPORT_SYMBOL_GPL(kvm_set_rflags); 8066 8067void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8068{ 8069 int r; 8070 8071 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8072 work->wakeup_all) 8073 return; 8074 8075 r = kvm_mmu_reload(vcpu); 8076 if (unlikely(r)) 8077 return; 8078 8079 if (!vcpu->arch.mmu.direct_map && 8080 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8081 return; 8082 8083 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8084} 8085 8086static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8087{ 8088 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8089} 8090 8091static inline u32 kvm_async_pf_next_probe(u32 key) 8092{ 8093 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8094} 8095 8096static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8097{ 8098 u32 key = kvm_async_pf_hash_fn(gfn); 8099 8100 while (vcpu->arch.apf.gfns[key] != ~0) 8101 key = kvm_async_pf_next_probe(key); 8102 8103 vcpu->arch.apf.gfns[key] = gfn; 8104} 8105 8106static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8107{ 8108 int i; 8109 u32 key = kvm_async_pf_hash_fn(gfn); 8110 8111 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8112 (vcpu->arch.apf.gfns[key] != gfn && 8113 vcpu->arch.apf.gfns[key] != ~0); i++) 8114 key = kvm_async_pf_next_probe(key); 8115 8116 return key; 8117} 8118 8119bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8120{ 8121 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8122} 8123 8124static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8125{ 8126 u32 i, j, k; 8127 8128 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8129 while (true) { 8130 vcpu->arch.apf.gfns[i] = ~0; 8131 do { 8132 j = kvm_async_pf_next_probe(j); 8133 if (vcpu->arch.apf.gfns[j] == ~0) 8134 return; 8135 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8136 /* 8137 * k lies cyclically in ]i,j] 8138 * | i.k.j | 8139 * |....j i.k.| or |.k..j i...| 8140 */ 8141 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8142 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8143 i = j; 8144 } 8145} 8146 8147static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8148{ 8149 8150 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8151 sizeof(val)); 8152} 8153 8154void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8155 struct kvm_async_pf *work) 8156{ 8157 struct x86_exception fault; 8158 8159 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8160 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8161 8162 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8163 (vcpu->arch.apf.send_user_only && 8164 kvm_x86_ops->get_cpl(vcpu) == 0)) 8165 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8166 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8167 fault.vector = PF_VECTOR; 8168 fault.error_code_valid = true; 8169 fault.error_code = 0; 8170 fault.nested_page_fault = false; 8171 fault.address = work->arch.token; 8172 kvm_inject_page_fault(vcpu, &fault); 8173 } 8174} 8175 8176void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8177 struct kvm_async_pf *work) 8178{ 8179 struct x86_exception fault; 8180 8181 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8182 if (work->wakeup_all) 8183 work->arch.token = ~0; /* broadcast wakeup */ 8184 else 8185 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8186 8187 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 8188 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8189 fault.vector = PF_VECTOR; 8190 fault.error_code_valid = true; 8191 fault.error_code = 0; 8192 fault.nested_page_fault = false; 8193 fault.address = work->arch.token; 8194 kvm_inject_page_fault(vcpu, &fault); 8195 } 8196 vcpu->arch.apf.halted = false; 8197 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8198} 8199 8200bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8201{ 8202 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8203 return true; 8204 else 8205 return !kvm_event_needs_reinjection(vcpu) && 8206 kvm_x86_ops->interrupt_allowed(vcpu); 8207} 8208 8209void kvm_arch_start_assignment(struct kvm *kvm) 8210{ 8211 atomic_inc(&kvm->arch.assigned_device_count); 8212} 8213EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8214 8215void kvm_arch_end_assignment(struct kvm *kvm) 8216{ 8217 atomic_dec(&kvm->arch.assigned_device_count); 8218} 8219EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8220 8221bool kvm_arch_has_assigned_device(struct kvm *kvm) 8222{ 8223 return atomic_read(&kvm->arch.assigned_device_count); 8224} 8225EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8226 8227void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8228{ 8229 atomic_inc(&kvm->arch.noncoherent_dma_count); 8230} 8231EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8232 8233void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8234{ 8235 atomic_dec(&kvm->arch.noncoherent_dma_count); 8236} 8237EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8238 8239bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8240{ 8241 return atomic_read(&kvm->arch.noncoherent_dma_count); 8242} 8243EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8244 8245int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8246 struct irq_bypass_producer *prod) 8247{ 8248 struct kvm_kernel_irqfd *irqfd = 8249 container_of(cons, struct kvm_kernel_irqfd, consumer); 8250 8251 if (kvm_x86_ops->update_pi_irte) { 8252 irqfd->producer = prod; 8253 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8254 prod->irq, irqfd->gsi, 1); 8255 } 8256 8257 return -EINVAL; 8258} 8259 8260void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8261 struct irq_bypass_producer *prod) 8262{ 8263 int ret; 8264 struct kvm_kernel_irqfd *irqfd = 8265 container_of(cons, struct kvm_kernel_irqfd, consumer); 8266 8267 if (!kvm_x86_ops->update_pi_irte) { 8268 WARN_ON(irqfd->producer != NULL); 8269 return; 8270 } 8271 8272 WARN_ON(irqfd->producer != prod); 8273 irqfd->producer = NULL; 8274 8275 /* 8276 * When producer of consumer is unregistered, we change back to 8277 * remapped mode, so we can re-use the current implementation 8278 * when the irq is masked/disabed or the consumer side (KVM 8279 * int this case doesn't want to receive the interrupts. 8280 */ 8281 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8282 if (ret) 8283 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8284 " fails: %d\n", irqfd->consumer.token, ret); 8285} 8286 8287int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8288 uint32_t guest_irq, bool set) 8289{ 8290 if (!kvm_x86_ops->update_pi_irte) 8291 return -EINVAL; 8292 8293 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8294} 8295 8296EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8297EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8298EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8299EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8300EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8301EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8302EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8303EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8304EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8305EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8306EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8307EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8308EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8309EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8310EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8311EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8312EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8313