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Searched refs:WP (Results 1 – 33 of 33) sorted by relevance

/linux-4.4.14/Documentation/devicetree/bindings/mmc/
Dmmc.txt22 - wp-inverted: when present, polarity on the WP line is inverted. See the note
23 below for the case, when a GPIO is used for the WP line
24 - disable-wp: When set no physical WP line is present. This property should
27 logic it is sufficient to not specify wp-gpios property in the absence of a WP
52 *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
59 CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs,
63 in the latter case. We choose to use the XOR logic for GPIO CD and WP lines.
/linux-4.4.14/arch/arm/boot/dts/
Dimx6sx-sabreauto.dts93 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
136 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
Dkirkwood-sheevaplug.dts22 /* No CD or WP GPIOs */
Dimx6qdl-rex.dtsi286 /* WP */
301 /* WP */
Dkirkwood-rd88f6281.dtsi62 /* No WP GPIO */
Dkirkwood-dreamplug.dts76 /* No CD or WP GPIOs */
Dkirkwood-mplcec4.dts113 /* No WP GPIO */
Dkirkwood-topkick.dts105 /* No CD or WP GPIOs */
Dat91sam9263ek.dts78 AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */
Dimx6dl-riotboard.dts509 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
522 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
Dimx6sx-sdb.dtsi515 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
558 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
Dimx27-phytec-phycore-rdk.dts170 MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
Dat91sam9m10g45ek.dts141 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
Darmada-370-mirabox.dts151 * No CD or WP GPIOs: SDIO interface used for
Dimx6qdl-aristainetos.dtsi233 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
Ddove-sbc-a510.dts57 * 1.0 MMC WP
Darmada-370-rd.dts133 /* No CD or WP GPIOs */
Darmada-xp-db.dts205 /* No CD or WP GPIOs */
Darmada-370-db.dts146 /* No CD or WP GPIOs */
Dimx7d-sdb.dts417 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
Dimx51-babbage.dts472 MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
Dimx6qdl-sabrelite.dtsi501 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
Dimx6qdl-aristainetos2.dtsi450 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
/linux-4.4.14/drivers/mtd/nand/
Dnuc900_nand.c41 #define WP (0x01 << 24) macro
233 val |= WP; in nuc900_nand_enable()
/linux-4.4.14/Documentation/devicetree/bindings/mtd/
Dbrcm,brcmnand.txt49 (WP) control bit. It is always available on >=
51 earlier versions of this core that include WP
/linux-4.4.14/arch/powerpc/boot/dts/
Dac14xx.dts171 wp-inverted; /* WP active high */
Dmpc8610_hpcd.dts214 &sdcsr_pio 1 0>; /* WP */
/linux-4.4.14/drivers/input/mouse/
Dsynaptics_usb.c535 { USB_DEVICE_SYNAPTICS(WP, SYNUSB_TOUCHPAD) },
/linux-4.4.14/arch/frv/mm/
Dtlb-miss.S175 # - IAMPR1 has no WP bit, and we mustn't lose WP information
/linux-4.4.14/arch/x86/kernel/
Dhead_32.S447 movl $0x50022,%ecx # set AM, WP, NE and MP
/linux-4.4.14/arch/x86/mm/
Dpat.c165 case PAT_WP: cache = CM(WP); cache_mode = "WP "; break; in pat_get_cache_mode()
/linux-4.4.14/Documentation/virtual/kvm/
Dmmu.txt365 CR4.SMAP && !CR0.WP into shadow page's role to avoid this case. Note,
/linux-4.4.14/drivers/pinctrl/sh-pfc/
Dpfc-sh7757.c1435 GPIO_FN(WP),