/linux-4.4.14/drivers/scsi/ |
H A D | mac_scsi.c | 38 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro 144 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); mac_scsi_reset_boot() 152 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); mac_scsi_reset_boot() 246 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && macscsi_pread() 247 !(NCR5380_read(STATUS_REG) & SR_REQ)) macscsi_pread() 250 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && macscsi_pread() 251 (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) { macscsi_pread() 340 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && macscsi_pwrite() 341 (!(NCR5380_read(STATUS_REG) & SR_REQ) || macscsi_pwrite() 342 (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))) macscsi_pwrite() 345 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)) { macscsi_pwrite()
|
H A D | dtc.h | 48 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro 51 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
|
H A D | g_NCR5380.h | 52 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro 77 #define NCR5380_read(reg) readb(iomem + NCR53C400_mem_base + (reg)) macro
|
H A D | g_NCR5380.c | 534 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { NCR5380_pread() 537 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { NCR5380_pread() 541 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY); NCR5380_pread() 547 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); NCR5380_pread() 558 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) NCR5380_pread() 567 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); NCR5380_pread() 577 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) NCR5380_pread() 585 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) NCR5380_pread() 588 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) NCR5380_pread() 592 NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_pread() 619 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { NCR5380_pwrite() 624 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { NCR5380_pwrite() 627 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) NCR5380_pwrite() 642 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) NCR5380_pwrite() 660 THEY NEVER DO ! while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG); NCR5380_pwrite() 668 while (!(i = NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) NCR5380_pwrite() 676 if (!((i = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_END_DMA_TRANSFER)) NCR5380_pwrite() 682 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) { NCR5380_pwrite() 686 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) NCR5380_pwrite()
|
H A D | dtc.c | 338 NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_pread() 348 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) NCR5380_pread() 359 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) NCR5380_pread() 363 NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_pread() 389 NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_pwrite() 400 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) NCR5380_pwrite() 408 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) NCR5380_pwrite() 412 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) NCR5380_pwrite()
|
H A D | atari_NCR5380.c | 193 * NCR5380_read(register) - read from the specified register 517 data = NCR5380_read(CURRENT_SCSI_DATA_REG); NCR5380_print() 518 status = NCR5380_read(STATUS_REG); NCR5380_print() 519 mr = NCR5380_read(MODE_REG); NCR5380_print() 520 icr = NCR5380_read(INITIATOR_COMMAND_REG); NCR5380_print() 521 basr = NCR5380_read(BUS_AND_STATUS_REG); NCR5380_print() 565 status = NCR5380_read(STATUS_REG); NCR5380_print_phase() 1124 if ((NCR5380_read(BUS_AND_STATUS_REG) & NCR5380_dma_complete() 1127 saved_data = NCR5380_read(INPUT_DATA_REG); NCR5380_dma_complete() 1135 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), NCR5380_dma_complete() 1136 NCR5380_read(STATUS_REG)); NCR5380_dma_complete() 1146 if ((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | BASR_ACK)) == NCR5380_dma_complete() 1149 NCR5380_read(BUS_AND_STATUS_REG)); NCR5380_dma_complete() 1156 (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_dma_complete() 1171 if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) { NCR5380_dma_complete() 1208 basr = NCR5380_read(BUS_AND_STATUS_REG); NCR5380_intr() 1213 if ((NCR5380_read(STATUS_REG) & (SR_SEL|SR_IO)) == (SR_SEL|SR_IO)) { NCR5380_intr() 1217 (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1220 (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1221 } else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) { NCR5380_intr() 1223 (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1237 if ((NCR5380_read(MODE_REG) & MR_DMA_MODE) && NCR5380_intr() 1251 HOSTNO, basr, NCR5380_read(MODE_REG), NCR5380_intr() 1252 NCR5380_read(STATUS_REG)); NCR5380_intr() 1253 (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1263 NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG)); NCR5380_intr() 1264 (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1347 while (!(NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_PROGRESS) && NCR5380_select() 1358 while (!(NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_PROGRESS) && NCR5380_select() 1379 if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) || NCR5380_select() 1380 (NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) || NCR5380_select() 1381 (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) || NCR5380_select() 1395 if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) || NCR5380_select() 1506 !(NCR5380_read(STATUS_REG) & (SR_BSY | SR_IO))) NCR5380_select() 1509 if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) { NCR5380_select() 1518 while (time_before(jiffies, timeout) && !(NCR5380_read(STATUS_REG) & SR_BSY)) NCR5380_select() 1532 if (!(NCR5380_read(STATUS_REG) & SR_BSY)) { NCR5380_select() 1571 while (!(NCR5380_read(STATUS_REG) & SR_REQ)) NCR5380_select() 1655 while (!((tmp = NCR5380_read(STATUS_REG)) & SR_REQ)) NCR5380_transfer_pio() 1671 *d = NCR5380_read(CURRENT_SCSI_DATA_REG); NCR5380_transfer_pio() 1700 while (NCR5380_read(STATUS_REG) & SR_REQ) NCR5380_transfer_pio() 1728 tmp = NCR5380_read(STATUS_REG); NCR5380_transfer_pio() 1771 while (!((tmp = NCR5380_read(STATUS_REG)) & SR_REQ)) do_abort() 1779 while (NCR5380_read(STATUS_REG) & SR_REQ) do_abort() 1849 NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_transfer_dma() 1852 (NCR5380_read(MODE_REG) | MR_DMA_MODE | MR_ENABLE_EOP_INTR)); NCR5380_transfer_dma() 1856 NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_transfer_dma() 1859 (NCR5380_read(MODE_REG) | MR_DMA_MODE | MR_ENABLE_EOP_INTR)); NCR5380_transfer_dma() 1875 if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) { NCR5380_transfer_dma() 1963 tmp = NCR5380_read(STATUS_REG); NCR5380_information_transfer() 2004 while (NCR5380_read(STATUS_REG) & SR_REQ) NCR5380_information_transfer() 2247 while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) NCR5380_information_transfer() 2307 while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) NCR5380_information_transfer() 2493 target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask); NCR5380_reselect() 2508 while (NCR5380_read(STATUS_REG) & SR_SEL) NCR5380_reselect() 2516 while (!(NCR5380_read(STATUS_REG) & SR_REQ)) NCR5380_reselect() 2524 msg[0] = NCR5380_read(CURRENT_SCSI_DATA_REG); NCR5380_reselect() 2685 NCR5380_read(BUS_AND_STATUS_REG), NCR5380_abort() 2686 NCR5380_read(STATUS_REG)); NCR5380_abort() 2884 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG))); NCR5380_bus_reset() 2895 (void)NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_bus_reset()
|
H A D | NCR5380.c | 239 * NCR5380_read(register) - read from the specified register 325 r = NCR5380_read(reg); NCR5380_poll_politely() 334 r = NCR5380_read(reg); NCR5380_poll_politely() 413 data = NCR5380_read(CURRENT_SCSI_DATA_REG); NCR5380_print() 414 status = NCR5380_read(STATUS_REG); NCR5380_print() 415 mr = NCR5380_read(MODE_REG); NCR5380_print() 416 icr = NCR5380_read(INITIATOR_COMMAND_REG); NCR5380_print() 417 basr = NCR5380_read(BUS_AND_STATUS_REG); NCR5380_print() 455 status = NCR5380_read(STATUS_REG); NCR5380_print_phase() 864 for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) { NCR5380_init() 1118 basr = NCR5380_read(BUS_AND_STATUS_REG); NCR5380_intr() 1122 if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) { NCR5380_intr() 1126 (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1129 (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1130 } else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) { NCR5380_intr() 1132 (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1141 if ((NCR5380_read(MODE_REG) & MR_DMA) && ((basr & BASR_END_DMA_TRANSFER) || !(basr & BASR_PHASE_MATCH))) { NCR5380_intr() 1152 (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1161 dprintk(NDEBUG_INTR, "scsi : unknown interrupt, BASR 0x%X, MR 0x%X, SR 0x%x\n", basr, NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG)); NCR5380_intr() 1162 (void) NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_intr() 1265 if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) || (NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) || (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) { NCR5380_select() 1277 (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) { NCR5380_select() 1364 value = NCR5380_read(STATUS_REG) & (SR_BSY | SR_IO); NCR5380_select() 1376 if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) { NCR5380_select() 1393 if (!(NCR5380_read(STATUS_REG) & SR_BSY)) { NCR5380_select() 1532 while (!((tmp = NCR5380_read(STATUS_REG)) & SR_REQ) && !break_allowed); NCR5380_transfer_pio() 1551 *d = NCR5380_read(CURRENT_SCSI_DATA_REG); NCR5380_transfer_pio() 1604 tmp = NCR5380_read(STATUS_REG); NCR5380_transfer_pio() 1630 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); do_reset() 1737 if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) { NCR5380_transfer_dma() 1776 dprintk(NDEBUG_DMA, "scsi%d : mode reg = 0x%X\n", instance->host_no, NCR5380_read(MODE_REG)); NCR5380_transfer_dma() 1796 tmp = NCR5380_read(BUS_AND_STATUS_REG); NCR5380_transfer_dma() 1838 if (((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | BASR_ACK)) == (BASR_PHASE_MATCH | BASR_ACK))) { NCR5380_transfer_dma() 1839 saved_data = NCR5380_read(INPUT_DATA_REGISTER); NCR5380_transfer_dma() 1845 while (((tmp = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_ACK) || (NCR5380_read(STATUS_REG) & SR_REQ)) { NCR5380_transfer_dma() 1853 dprintk(NDEBUG_DMA, "scsi%d : polled DMA transfer complete, basr 0x%X, sr 0x%X\n", instance->host_no, tmp, NCR5380_read(STATUS_REG)); NCR5380_transfer_dma() 1862 *phase = NCR5380_read(STATUS_REG) & PHASE_MASK; NCR5380_transfer_dma() 1920 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)); NCR5380_transfer_dma() 1922 while (NCR5380_read(STATUS_REG) & SR_REQ); NCR5380_transfer_dma() 1923 d[c - 1] = NCR5380_read(INPUT_DATA_REG); NCR5380_transfer_dma() 1940 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)); NCR5380_transfer_dma() 1947 if (NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT) { NCR5380_transfer_dma() 1954 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)); NCR5380_transfer_dma() 1965 if (NCR5380_read(BUS_AND_STATUS_REG) & BASR_IRQ) { NCR5380_transfer_dma() 1967 NCR5380_read(RESET_PARITY_INTERRUPT_REG); NCR5380_transfer_dma() 1974 *phase = NCR5380_read(STATUS_REG) & PHASE_MASK; NCR5380_transfer_dma() 2020 tmp = NCR5380_read(STATUS_REG); 2032 while (NCR5380_read(STATUS_REG) & SR_REQ); 2216 while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) 2252 while ((NCR5380_read(STATUS_REG) & SR_BSY) && !hostdata->connected) 2429 target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask); NCR5380_reselect() 2596 dprintk(NDEBUG_ABORT, " basr 0x%X, sr 0x%X\n", NCR5380_read(BUS_AND_STATUS_REG), NCR5380_read(STATUS_REG)); NCR5380_abort()
|
H A D | t128.h | 96 #define NCR5380_read(reg) readb(T128_address(reg)) macro 99 #define NCR5380_read(reg) \ macro
|
H A D | pas16.h | 124 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro 127 #define NCR5380_read(reg) \ macro
|
H A D | dmx3191d.c | 39 #define NCR5380_read(reg) inb(port + reg) macro
|
H A D | pas16.c | 208 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); init_board() 285 if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */ pas16_hw_detect() 288 if( NCR5380_read( MODE_REG ) != 0x00 ) pas16_hw_detect()
|
H A D | sun3_scsi.c | 50 #define NCR5380_read(reg) sun3scsi_read(reg) macro 164 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); sun3_scsi_reset_boot() 174 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); sun3_scsi_reset_boot()
|
H A D | atari_scsi.c | 96 #define NCR5380_read(reg) atari_scsi_reg_read(reg) macro 533 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG))); atari_scsi_reset_boot() 541 NCR5380_read(RESET_PARITY_INTERRUPT_REG); atari_scsi_reset_boot() 752 * methods are quite different. The calling macros NCR5380_read and
|
/linux-4.4.14/drivers/scsi/arm/ |
H A D | oak.c | 26 #define NCR5380_read(reg) readb(_base + ((reg) << 2)) macro
|
H A D | cumana_1.c | 25 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro
|