534 		if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) {  in NCR5380_pread()
537 		if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) {  in NCR5380_pread()
541 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY);  in NCR5380_pread()
547 				dst[start + i] = NCR5380_read(C400_HOST_BUFFER);  in NCR5380_pread()
558 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)  in NCR5380_pread()
567 				dst[start + i] = NCR5380_read(C400_HOST_BUFFER);  in NCR5380_pread()
577 	if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ))  in NCR5380_pread()
585 	while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG)  in NCR5380_pread()
588 	if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER))  in NCR5380_pread()
592 	NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_pread()
619 		if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) {  in NCR5380_pwrite()
624 		if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) {  in NCR5380_pwrite()
627 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)  in NCR5380_pwrite()
642 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)  in NCR5380_pwrite()
660 	THEY NEVER DO ! while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG);  in NCR5380_pwrite()
668 	while (!(i = NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ))  in NCR5380_pwrite()
676 		if (!((i = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_END_DMA_TRANSFER))  in NCR5380_pwrite()
682 	if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) {  in NCR5380_pwrite()
686 	while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT))  in NCR5380_pwrite()