Searched refs:IS_HASWELL (Results 1 - 24 of 24) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_fbc.c300 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { gen7_fbc_enable()
531 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) intel_fbc_find_crtc()
813 if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { intel_fbc_hw_tracking_covers_screen()
947 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && __intel_fbc_update()
1099 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) for_each_pipe()
H A Di915_drv.c463 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { intel_virt_detect_pch()
519 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); intel_detect_pch()
524 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); intel_detect_pch()
846 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) i915_drm_resume_early()
1580 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) intel_runtime_resume()
1624 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) intel_suspend_complete()
H A Di915_cmd_parser.c699 if (IS_HASWELL(ring->dev)) { i915_cmd_parser_init_ring()
711 if (IS_HASWELL(ring->dev)) { i915_cmd_parser_init_ring()
727 if (IS_HASWELL(ring->dev)) { i915_cmd_parser_init_ring()
738 if (IS_HASWELL(ring->dev)) { i915_cmd_parser_init_ring()
H A Di915_vgpu.c69 if (!IS_HASWELL(dev)) i915_check_vgpu()
H A Dintel_sprite.c536 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ivb_update_plane()
541 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ivb_update_plane()
568 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { ivb_update_plane()
592 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ivb_update_plane()
H A Dintel_uncore.c336 if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || intel_uncore_ellc_detect()
1132 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { intel_uncore_fw_domains_init()
1135 if (IS_HASWELL(dev)) intel_uncore_fw_domains_init()
1225 if (IS_HASWELL(dev)) { intel_uncore_init()
H A Dintel_audio.c569 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { intel_init_audio()
648 !IS_HASWELL(dev_priv)) i915_audio_component_sync_audio_rate()
H A Dintel_psr.c304 if (IS_HASWELL(dev) && dig_port->port != PORT_A) { intel_psr_match_conditions()
314 if (IS_HASWELL(dev) && intel_psr_match_conditions()
321 if (IS_HASWELL(dev) && intel_psr_match_conditions()
H A Di915_drv.h2471 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) macro
2476 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2487 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2489 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2545 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2583 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2588 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2591 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2602 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2631 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
H A Dintel_pm.c2122 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { intel_read_wm_latency()
2172 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ilk_wm_max_level()
2338 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2472 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ilk_wm_lp_latency()
2696 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { ilk_write_wm_values()
3880 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ilk_pipe_wm_get_hw_state()
4086 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ilk_wm_get_hw_state()
4435 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) gen6_set_rps()
4694 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { gen6_init_rps_frequencies()
4723 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) gen6_init_rps_frequencies()
4978 if (!IS_HASWELL(dev)) { gen6_enable_rps()
5087 } else if (IS_HASWELL(dev)) { __gen6_update_ring_freq()
7089 else if (IS_HASWELL(dev)) intel_init_pm()
H A Dintel_dp_mst.c93 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
H A Di915_gem_context.c121 if (IS_HASWELL(dev)) get_context_size()
536 if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) mi_set_context()
H A Dintel_display.c2848 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ironlake_update_primary_plane()
2877 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) ironlake_update_primary_plane()
2890 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { ironlake_update_primary_plane()
2910 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { ironlake_update_primary_plane()
4570 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) ironlake_pfit_enable()
4662 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && intel_crtc_load_lut()
5056 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5384 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) intel_compute_max_dotclk()
6510 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { ironlake_check_fdi_lanes()
6620 if (IS_HASWELL(dev_priv->dev)) pipe_config_supports_ips()
7752 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && intel_set_pipe_timings()
8728 if (IS_HASWELL(dev) && intel_crtc->config->dither) haswell_set_pipeconf()
9229 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { ironlake_get_initial_plane_config()
9358 if (IS_HASWELL(dev)) assert_can_disable_lcpll()
9380 if (IS_HASWELL(dev)) hsw_read_dcomp()
9390 if (IS_HASWELL(dev)) { hsw_write_dcomp()
9914 if (IS_HASWELL(dev)) haswell_get_pipe_config()
11501 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { intel_crtc_page_flip()
12560 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || intel_pipe_config_compare()
12601 if (IS_HASWELL(dev)) intel_pipe_config_compare()
13092 if (IS_HASWELL(dev)) intel_modeset_checks()
14572 else if (IS_HASWELL(dev)) intel_init_display()
14628 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { intel_init_display()
15693 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) intel_display_capture_error_state()
15713 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) for_each_pipe()
15767 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) intel_display_print_error_state()
15784 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) for_each_pipe()
H A Di915_gem_gtt.c1759 if (IS_HASWELL(dev)) { gen7_ppgtt_enable()
2070 } else if (IS_HASWELL(dev)) { gen6_ppgtt_init()
3099 if (IS_HASWELL(dev) && dev_priv->ellc_size) i915_gem_gtt_init()
3101 else if (IS_HASWELL(dev)) i915_gem_gtt_init()
H A Di915_sysfs.c294 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) gt_act_freq_mhz_show()
H A Di915_debugfs.c1178 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) i915_frequency_info()
1198 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) i915_frequency_info()
3854 if (IS_HASWELL(dev) && pipe == PIPE_A) ivb_pipe_crc_ctl_reg()
3966 else if (IS_HASWELL(dev) && pipe == PIPE_A) pipe_crc_set_source()
H A Dintel_dp.c1074 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E) intel_dp_aux_init()
1195 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || intel_dp_source_supports_hbr2()
1534 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) intel_dp_compute_config()
3098 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { intel_dp_pre_emphasis_max()
6008 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) intel_dp_init_connector()
H A Dintel_ddi.c481 } else if (IS_HASWELL(dev)) { intel_prepare_ddi_buffers()
1895 if (IS_HASWELL(dev) && intel_ddi_enable_transcoder_func()
H A Dintel_hdmi.c1159 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) hdmi_port_clock_limit()
H A Dintel_runtime_pm.c1858 if (IS_HASWELL(dev_priv->dev)) { intel_power_domains_init()
H A Dintel_ringbuffer.c2747 if (IS_HASWELL(dev)) intel_init_render_ring_buffer()
H A Di915_reg.h1956 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3085 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
H A Di915_gem.c4778 if (IS_HASWELL(dev)) i915_gem_init_hw()
H A Di915_irq.c387 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) gen6_sanitize_rps_pm_mask()

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