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Searched refs:I915_READ (Results 1 – 43 of 43) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Di915_suspend.c38 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
42 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); in i915_save_display()
44 dev_priv->regfile.saveLVDS = I915_READ(LVDS); in i915_save_display()
48 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()
49 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); in i915_save_display()
50 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); in i915_save_display()
51 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); in i915_save_display()
53 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); in i915_save_display()
54 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); in i915_save_display()
55 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); in i915_save_display()
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Di915_drv.c1147 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
1148 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
1149 s->arb_mode = I915_READ(ARB_MODE); in vlv_save_gunit_s0ix_state()
1150 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
1151 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
1154 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
1156 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
1157 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
1159 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
1160 s->ecochk = I915_READ(GAM_ECOCHK); in vlv_save_gunit_s0ix_state()
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Di915_gpu_error.c796 error->fence[i] = I915_READ(FENCE_REG(i)); in i915_gem_record_fences()
845 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); in gen6_record_semaphore_state()
846 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); in gen6_record_semaphore_state()
852 I915_READ(RING_SYNC_2(ring->mmio_base)); in gen6_record_semaphore_state()
865 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); in i915_record_ring_state()
866 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); in i915_record_ring_state()
874 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); in i915_record_ring_state()
875 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); in i915_record_ring_state()
876 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); in i915_record_ring_state()
877 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); in i915_record_ring_state()
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Dintel_ddi.c592 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
675 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
683 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
697 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
703 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
716 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
948 wrpll = I915_READ(reg); in hsw_ddi_calc_wrpll_link()
985 cfgcr1_val = I915_READ(cfgcr1_reg); in skl_calc_wrpll_link()
986 cfgcr2_val = I915_READ(cfgcr2_reg); in skl_calc_wrpll_link()
1065 dpll_ctl1 = I915_READ(DPLL_CTRL1); in skl_ddi_clock_get()
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Dintel_audio.c173 tmp = I915_READ(reg_eldv); in intel_eld_uptodate()
179 tmp = I915_READ(reg_elda); in intel_eld_uptodate()
184 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) in intel_eld_uptodate()
197 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_disable()
204 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
221 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_enable()
233 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
243 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
260 tmp = I915_READ(HSW_AUD_CFG(pipe)); in hsw_audio_codec_disable()
270 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); in hsw_audio_codec_disable()
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Di915_debugfs.c618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); in i915_gem_pageflip_info()
620 addr = I915_READ(DSPADDR(crtc->plane)); in i915_gem_pageflip_info()
777 I915_READ(GEN8_MASTER_IRQ)); in i915_interrupt_info()
780 I915_READ(VLV_IER)); in i915_interrupt_info()
782 I915_READ(VLV_IIR)); in i915_interrupt_info()
784 I915_READ(VLV_IIR_RW)); in i915_interrupt_info()
786 I915_READ(VLV_IMR)); in i915_interrupt_info()
790 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
793 I915_READ(PORT_HOTPLUG_EN)); in i915_interrupt_info()
795 I915_READ(VLV_DPFLIPSTAT)); in i915_interrupt_info()
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Di915_irq.c144 u32 val = I915_READ(reg); in gen5_assert_iir_is_zero()
184 val = I915_READ(PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
370 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
372 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | in gen6_enable_rps_interrupts()
411 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & in gen6_disable_rps_interrupts()
439 old_val = I915_READ(GEN8_DE_PORT_IMR); in bdw_update_port_irq()
461 uint32_t sdeimr = I915_READ(SDEIMR); in ibx_display_interrupt_update()
481 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_enable_pipestat()
508 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_disable_pipestat()
696 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()
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Dintel_crt.c79 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_hw_state()
98 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_flags()
288 save_adpa = adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
297 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in intel_ironlake_crt_detect_hotplug()
308 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
327 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
334 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in valleyview_crt_detect_hotplug()
341 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
390 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & in intel_crt_detect_hotplug()
396 stat = I915_READ(PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
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Dintel_display.c179 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; in intel_pch_rawclk()
192 clkcfg = I915_READ(CLKCFG); in intel_hrawclk()
231 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; in intel_fdi_link_freq()
1108 line1 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1110 line2 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1142 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, in intel_wait_for_pipe_off()
1164 val = I915_READ(DPLL(pipe)); in assert_pll()
1227 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1230 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1246 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
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Dintel_dsi.c59 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) in wait_for_dsi_fifo_empty()
84 u32 val = I915_READ(reg); in read_data()
125 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) in intel_dsi_host_transfer()
136 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { in intel_dsi_host_transfer()
145 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) in intel_dsi_host_transfer()
229 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
235 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) in dpi_send_cmd()
298 val = I915_READ(BXT_MIPI_PORT_CTRL(port)); in bxt_dsi_device_ready()
303 val = I915_READ(MIPI_DEVICE_READY(port)); in bxt_dsi_device_ready()
310 val = I915_READ(MIPI_DEVICE_READY(port)); in bxt_dsi_device_ready()
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Dintel_psr.c69 val = I915_READ(VLV_PSRSTAT(pipe)) & in vlv_is_psr_active_on_pipe()
116 val = I915_READ(VLV_VSCSDP(pipe)); in vlv_psr_setup_vsc()
197 val = I915_READ(aux_ctl_reg); in hsw_psr_enable_sink()
246 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
315 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & in intel_psr_match_conditions()
343 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); in intel_psr_activate()
446 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & in vlv_psr_disable()
450 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); in vlv_psr_disable()
470 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); in hsw_psr_disable()
473 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & in hsw_psr_disable()
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Dintel_sideband.c54 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { in vlv_sideband_rw()
65 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { in vlv_sideband_rw()
72 *val = I915_READ(VLV_IOSF_DATA); in vlv_sideband_rw()
218 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_read()
232 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_read()
238 return I915_READ(SBI_DATA); in intel_sbi_read()
248 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_write()
263 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_write()
Dintel_pm.c60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
76 tmp = I915_READ(CLKCFG); in i915_pineview_get_mem_freq()
106 tmp = I915_READ(CSHRDDR3CTL); in i915_pineview_get_mem_freq()
294 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; in intel_set_memory_cxsr()
345 dsparb = I915_READ(DSPARB); in vlv_get_fifo_size()
346 dsparb2 = I915_READ(DSPARB2); in vlv_get_fifo_size()
351 dsparb = I915_READ(DSPARB); in vlv_get_fifo_size()
352 dsparb2 = I915_READ(DSPARB2); in vlv_get_fifo_size()
357 dsparb2 = I915_READ(DSPARB2); in vlv_get_fifo_size()
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Dintel_runtime_pm.c95 return I915_READ(HSW_PWR_WELL_DRIVER) == in hsw_power_well_enabled()
261 tmp = I915_READ(HSW_PWR_WELL_DRIVER); in hsw_set_power_well()
272 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & in hsw_set_power_well()
387 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), in assert_can_enable_dc9()
389 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, in assert_can_enable_dc9()
391 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); in assert_can_enable_dc9()
406 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), in assert_can_disable_dc9()
408 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, in assert_can_disable_dc9()
428 val = I915_READ(DC_STATE_EN); in bxt_enable_dc9()
442 val = I915_READ(DC_STATE_EN); in bxt_disable_dc9()
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Dintel_panel.c486 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
494 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
504 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
525 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in _vlv_get_backlight()
542 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); in bxt_get_backlight()
578 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
588 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
616 tmp = I915_READ(BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
630 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
743 tmp = I915_READ(BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
Dintel_dsi_pll.c303 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_disable_dsi_pll()
311 if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) in bxt_disable_dsi_pll()
401 dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & in bxt_get_dsi_pclk()
428 temp = I915_READ(MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
445 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
452 pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & in bxt_dsi_program_clocks()
499 val = I915_READ(BXT_DSI_PLL_CTL); in bxt_configure_dsi_pll()
528 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_enable_dsi_pll()
547 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_enable_dsi_pll()
552 if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { in bxt_enable_dsi_pll()
[all …]
Dintel_lvds.c83 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_hw_state()
105 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_config()
119 tmp = I915_READ(PFIT_CONTROL); in intel_lvds_get_config()
150 temp = I915_READ(lvds_encoder->reg); in intel_pre_enable_lvds()
223 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
225 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
227 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) in intel_enable_lvds()
248 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
249 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) in intel_disable_lvds()
252 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
[all …]
Dintel_dvo.c122 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
138 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
155 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
175 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
179 I915_READ(dvo_reg); in intel_disable_dvo()
188 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
195 I915_READ(dvo_reg); in intel_enable_dvo()
274 dvo_val = I915_READ(dvo_reg) & in intel_dvo_pre_enable()
388 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_current_mode()
488 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
Di915_vgpu.c191 mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); in intel_vgt_balloon()
192 mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); in intel_vgt_balloon()
193 unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); in intel_vgt_balloon()
194 unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); in intel_vgt_balloon()
Dintel_ringbuffer.h34 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
37 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
40 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
43 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
46 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
49 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
Dintel_fifo_underrun.c108 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_check_fifo_underruns()
127 u32 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_set_fifo_underrun_reporting()
169 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivybridge_set_fifo_underrun_reporting()
222 if (old && I915_READ(SERR_INT) & in cpt_set_fifo_underrun_reporting()
Dintel_hdmi.c55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
141 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
176 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_infoframe_enabled()
197 u32 val = I915_READ(reg); in ibx_write_infoframe()
233 u32 val = I915_READ(reg); in ibx_infoframe_enabled()
255 u32 val = I915_READ(reg); in cpt_write_infoframe()
293 u32 val = I915_READ(reg); in cpt_infoframe_enabled()
312 u32 val = I915_READ(reg); in vlv_write_infoframe()
348 u32 val = I915_READ(reg); in vlv_infoframe_enabled()
373 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
[all …]
Dintel_fbc.c69 fbc_ctl = I915_READ(FBC_CONTROL); in i8xx_fbc_disable()
77 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { in i8xx_fbc_disable()
122 fbc_ctl = I915_READ(FBC_CONTROL); in i8xx_fbc_enable()
137 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_enabled()
171 dpfc_ctl = I915_READ(DPFC_CONTROL); in g4x_fbc_disable()
182 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_enabled()
246 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); in ilk_fbc_disable()
257 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; in ilk_fbc_enabled()
298 I915_READ(ILK_DISPLAY_CHICKEN1) | in gen7_fbc_enable()
303 I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | in gen7_fbc_enable()
Dintel_overlay.c282 tmp = I915_READ(DOVSTA); in intel_overlay_continue()
422 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { in intel_overlay_release_old_vid()
899 u32 pfit_control = I915_READ(PFIT_CONTROL); in update_pfit_vscale_ratio()
907 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; in update_pfit_vscale_ratio()
910 ratio = I915_READ(PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
912 ratio = I915_READ(PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1072 pfit_control = I915_READ(PFIT_CONTROL); in intel_panel_fitter_pipe()
1310 attrs->gamma0 = I915_READ(OGAMC0); in intel_overlay_attrs()
1311 attrs->gamma1 = I915_READ(OGAMC1); in intel_overlay_attrs()
1312 attrs->gamma2 = I915_READ(OGAMC2); in intel_overlay_attrs()
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Dintel_dp.c312 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
323 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
333 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
463 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
590 pp_div = I915_READ(pp_div_reg); in edp_notify_handler()
615 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
629 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
644 I915_READ(_pp_stat_reg(intel_dp)), in intel_dp_check_edp()
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Di915_dma.c558 fuse = I915_READ(CHV_FUSE_GT); in cherryview_sseu_info_init()
604 fuse2 = I915_READ(GEN8_FUSE2); in gen9_sseu_info_init()
628 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); in gen9_sseu_info_init()
682 fuse2 = I915_READ(GEN8_FUSE2); in broadwell_sseu_info_init()
686 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; in broadwell_sseu_info_init()
687 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | in broadwell_sseu_info_init()
688 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << in broadwell_sseu_info_init()
690 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | in broadwell_sseu_info_init()
691 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << in broadwell_sseu_info_init()
796 u32 fuse_strap = I915_READ(FUSE_STRAP); in intel_device_info_runtime_init()
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Dintel_csr.c275 if (I915_READ(CSR_PROGRAM(0))) in intel_csr_load_program()
483 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), in assert_csr_loaded()
485 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); in assert_csr_loaded()
486 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); in assert_csr_loaded()
Di915_gem_stolen.c197 gtt_start = I915_READ(PGTBL_CTL); in i915_stolen_to_physical()
277 uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ? in g4x_get_stolen_reserved()
300 uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); in gen6_get_stolen_reserved()
326 uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); in gen7_get_stolen_reserved()
346 uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); in gen8_get_stolen_reserved()
372 uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED); in bdw_get_stolen_reserved()
Dintel_tv.c842 u32 tmp = I915_READ(TV_CTL); in intel_tv_get_hw_state()
862 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
871 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1040 tv_ctl = I915_READ(TV_CTL); in intel_tv_pre_enable()
1148 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE); in intel_tv_pre_enable()
1199 save_tv_dac = tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
1200 save_tv_ctl = tv_ctl = I915_READ(TV_CTL); in intel_tv_detect_type()
1237 tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
1585 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) in intel_tv_init()
1600 save_tv_dac = I915_READ(TV_DAC); in intel_tv_init()
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Di915_gem_fence.c568 if (I915_READ(DISP_ARB_CTL) & in i915_gem_detect_bit_6_swizzle()
578 dimm_c0 = I915_READ(MAD_DIMM_C0); in i915_gem_detect_bit_6_swizzle()
579 dimm_c1 = I915_READ(MAD_DIMM_C1); in i915_gem_detect_bit_6_swizzle()
618 dcc = I915_READ(DCC); in i915_gem_detect_bit_6_swizzle()
646 !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { in i915_gem_detect_bit_6_swizzle()
Dintel_guc_loader.c201 u32 val = I915_READ(GUC_STATUS); in guc_ucode_response()
279 I915_READ(DMA_CTRL), status); in guc_ucode_xfer_dma()
327 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & in guc_ucode_xfer()
342 I915_READ(GEN7_MISCCPCTL))); in guc_ucode_xfer()
Dintel_ringbuffer.c464 acthd = I915_READ(RING_ACTHD(ring->mmio_base)); in intel_ring_get_active_head()
466 acthd = I915_READ(ACTHD); in intel_ring_get_active_head()
537 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, in intel_ring_setup_status_page()
802 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
803 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
914 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | in gen9_init_workarounds()
918 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in gen9_init_workarounds()
1045 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in skl_init_workarounds()
1058 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | in skl_init_workarounds()
1063 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | in skl_init_workarounds()
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Di915_guc_submission.c73 u32 val = I915_READ(SOFT_SCRATCH(0)); in host2guc_action_response()
115 I915_READ(SOFT_SCRATCH(15))); in host2guc_action()
271 I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); in guc_disable_doorbell()
273 value = I915_READ(drbreg); in guc_disable_doorbell()
Dintel_dp_mst.c204 temp = I915_READ(DP_TP_STATUS(port)); in intel_mst_pre_enable_dp()
222 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_ACT_SENT), in intel_mst_enable_dp()
254 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_dp_mst_enc_get_config()
Dintel_uncore.c1314 reg->val = I915_READ(offset); in i915_reg_read_ioctl()
1413 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1423 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1438 ret = wait_for((I915_READ(ILK_GDSR) & in ironlake_do_reset()
1445 ret = wait_for((I915_READ(ILK_GDSR) & in ironlake_do_reset()
1482 return wait_for((I915_READ(reg) & mask) == value, timeout_ms); in wait_for_register()
Di915_sysfs.c55 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) in calc_residency()
62 raw_time = I915_READ(reg) * units; in calc_residency()
291 u32 rpstat = I915_READ(GEN6_RPSTAT1); in gt_act_freq_mhz_show()
Dintel_i2c.c129 val = I915_READ(DSPCLK_GATE_D); in intel_i2c_quirk_set()
341 val = I915_READ(GMBUS3); in gmbus_xfer_read_chunk()
Dintel_sdvo.c263 cval = I915_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
265 bval = I915_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
1284 sdvox = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_pre_enable()
1343 tmp = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_get_hw_state()
1370 sdvox = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_get_config()
1456 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_disable_sdvo()
1496 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_enable_sdvo()
Di915_gem_context.c116 reg = I915_READ(CXT_SIZE); in get_context_size()
120 reg = I915_READ(GEN7_CXT_SIZE); in get_context_size()
Dintel_lrc.c511 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); in intel_lrc_irq_handler()
522 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % GEN8_CSB_ENTRIES)); in intel_lrc_irq_handler()
523 status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % GEN8_CSB_ENTRIES)); in intel_lrc_irq_handler()
1496 next_context_status_buffer_hw = (I915_READ(RING_CONTEXT_STATUS_PTR(ring)) in gen8_init_common_ring()
Di915_gem_gtt.c1755 ecobits = I915_READ(GAC_ECO_BITS); in gen7_ppgtt_enable()
1758 ecochk = I915_READ(GAM_ECOCHK); in gen7_ppgtt_enable()
1779 ecobits = I915_READ(GAC_ECO_BITS); in gen6_ppgtt_enable()
1783 gab_ctl = I915_READ(GAB_CTL); in gen6_ppgtt_enable()
1786 ecochk = I915_READ(GAM_ECOCHK); in gen6_ppgtt_enable()
2275 fault_reg = I915_READ(RING_FAULT_REG(ring)); in i915_check_and_clear_faults()
Di915_gem.c4671 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in i915_gem_init_swizzling()
4677 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); in i915_gem_init_swizzling()
4776 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); in i915_gem_init_hw()
4784 u32 temp = I915_READ(GEN7_MSG_CTL); in i915_gem_init_hw()
4788 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); in i915_gem_init_hw()
4900 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & in i915_gem_init()
5031 I915_READ(vgtif_reg(avail_rs.fence_num)); in i915_gem_load()
Di915_drv.h3424 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) macro
3440 upper = I915_READ(upper_reg); \
3443 lower = I915_READ(lower_reg); \
3444 upper = I915_READ(upper_reg); \