/linux-4.4.14/drivers/gpu/drm/gma500/ |
H A D | gtt.c | 29 * GTT resource allocator - manage page mappings in GTT space 33 * psb_gtt_mask_pte - generate GTT pte entry 35 * @type: type of memory in the GTT 37 * Set the GTT entry for the appropriate memory type. 58 * psb_gtt_entry - find the GTT entries for a gtt_range 60 * @r: our GTT range 62 * Given a gtt_range object return the GTT offset of the page table 76 * psb_gtt_insert - put an object into the GTT 78 * @r: our GTT range 80 * Take our preallocated GTT range and insert the GEM object into 81 * the GTT. This is protected via the gtt mutex which the caller 107 /* Write our page entries into the GTT itself */ psb_gtt_insert() 125 * psb_gtt_remove - remove an object from the GTT 127 * @r: our GTT range 129 * Remove a preallocated GTT range from the GTT. Overwrite all the 158 * Roll an existing pinned mapping by moving the pages through the GTT. 175 /* Not currently in the GTT - no worry we will write the mapping at psb_gtt_roll() 224 * must have been removed from the GTT as they could now be paged out 235 * psb_gtt_pin - pin pages into the GTT 238 * Pin a set of pages into the GTT. The pins are refcounted so that 241 * Non GEM backed objects treat this as a no-op as they are always GTT 273 * psb_gtt_unpin - Drop a GTT pin requirement 277 * will be removed from the GTT which will also drop the page references 280 * Non GEM backed objects treat this as a no-op as they are always GTT 315 * GTT resource allocator - allocate and manage GTT address space 319 * psb_gtt_alloc_range - allocate GTT address space 326 * to use for a GTT mapping. 342 /* The start of the GTT is the stolen pages */ psb_gtt_alloc_range() 371 * psb_gtt_free_range - release GTT address space 433 /* Enable the GTT */ psb_gtt_init() 460 dev_dbg(dev->dev, "GTT PCI BAR not initialized.\n"); psb_gtt_init() 478 /* This is a little confusing but in fact the GTT is providing psb_gtt_init() 500 dev_err(dev->dev, "GTT resume error.\n"); psb_gtt_init() 510 * Map the GTT and the stolen memory area psb_gtt_init() 532 * Insert vram stolen pages into the GTT psb_gtt_init() 537 dev_dbg(dev->dev, "Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n", psb_gtt_init() 545 * Init rest of GTT to the scratch page to avoid accidents or scribbles psb_gtt_init()
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H A D | gtt.h | 43 /* Each gtt_range describes an allocation in the GTT area */ 46 u32 offset; /* GTT offset of our object */ 53 int roll; /* Roll applied to the GTT entries */
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H A D | framebuffer.c | 106 /* GTT roll shifts in 4K pages, we need to shift the right psbfb_pan() 311 * Allocate the frame buffer. In the usual case we get a GTT range that 364 * Acceleration via the GTT requires pitch to be psbfb_create() 373 /* Allocate the fb in the GTT with stolen page backing */ psbfb_create() 393 gtt_roll = 0; /* Don't use GTT accelerated scrolling */ psbfb_create() 401 /* Allocate the framebuffer in the GTT with stolen page backing */ psbfb_create() 435 else if (gtt_roll) { /* GTT rolling seems best */ psbfb_create() 642 * Our framebuffer object is a GTT range which also contains a GEM
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H A D | gem.c | 167 * of the GTT and repacking it when we run out of space. We can put
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H A D | power.c | 114 psb_gtt_restore(dev); /* Rebuild our GTT mappings */ gma_resume_display()
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H A D | gma_display.c | 79 into the GTT */ gma_pipe_set_base() 394 /* Pin the memory into the GTT */ gma_crtc_cursor_set()
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H A D | psb_drv.h | 454 /* GTT Memory manager */ 462 u16 gmch_ctrl; /* Saved GTT setup */
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/linux-4.4.14/drivers/gpu/drm/radeon/ |
H A D | radeon_test.c | 33 /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ radeon_do_test_moves() 57 * (Total GTT - IB pool - writeback page - ring buffers) / test size radeon_do_test_moves() 93 DRM_ERROR("Failed to create GTT object %d\n", i); radeon_do_test_moves() 102 DRM_ERROR("Failed to pin GTT object %d\n", i); radeon_do_test_moves() 108 DRM_ERROR("Failed to map GTT object %d\n", i); radeon_do_test_moves() 128 DRM_ERROR("Failed GTT->VRAM copy %d\n", i); radeon_do_test_moves() 135 DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); radeon_do_test_moves() 152 DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " radeon_do_test_moves() 153 "expected 0x%p (GTT/VRAM offset " radeon_do_test_moves() 179 DRM_ERROR("Failed VRAM->GTT copy %d\n", i); radeon_do_test_moves() 186 DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); radeon_do_test_moves() 194 DRM_ERROR("Failed to map GTT object after copy %d\n", i); radeon_do_test_moves() 203 DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " radeon_do_test_moves() 204 "expected 0x%p (VRAM/GTT offset " radeon_do_test_moves() 220 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", radeon_do_test_moves()
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H A D | radeon_benchmark.c | 192 /* simple test, VRAM to GTT and GTT to VRAM */ radeon_benchmark() 204 /* GTT to VRAM, buffer size sweep, powers of 2 */ radeon_benchmark() 211 /* VRAM to GTT, buffer size sweep, powers of 2 */ radeon_benchmark() 225 /* GTT to VRAM, buffer size sweep, common modes */ radeon_benchmark() 232 /* VRAM to GTT, buffer size sweep, common modes */ radeon_benchmark()
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H A D | radeon_prime.c | 92 /* pin buffer into GTT */ radeon_gem_prime_pin()
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H A D | radeon_device.c | 548 * Note: GTT start, end, size should be initialized before calling this 595 * radeon_gtt_location - try to find GTT location 599 * Function will place try to place GTT before or after VRAM. 601 * If GTT size is bigger than space left then we ajust GTT size. 604 * FIXME: when reducing GTT size align new size on power of 2. 614 dev_warn(rdev->dev, "limiting GTT\n"); radeon_gtt_location() 620 dev_warn(rdev->dev, "limiting GTT\n"); radeon_gtt_location() 626 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", radeon_gtt_location()
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H A D | radeon_object.c | 225 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx radeon_bo_create() 232 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit radeon_bo_create() 507 * a dozen IBs to move all buffers to VRAM if they are in GTT. radeon_bo_get_threshold_for_moves()
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H A D | radeon_ttm.c | 207 * first, but only set GTT as busy placement, so this radeon_evict_flags() 208 * BO will be evicted to GTT rather than causing other radeon_evict_flags() 914 DRM_ERROR("Failed initializing GTT heap.\n"); radeon_ttm_init() 917 DRM_INFO("radeon: %uM of GTT memory ready.\n", radeon_ttm_init()
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H A D | radeon_agp.c | 248 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", radeon_agp_init()
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H A D | radeon_ib.c | 206 /* Before CIK, it's better to stick to cacheable GTT due radeon_ib_pool_init()
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H A D | radeon_gem.c | 787 placement = " GTT"; radeon_debugfs_gem_info()
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H A D | r600.c | 1362 * r600_vram_gtt_location - try to find VRAM & GTT location 1377 * This function will never fails, worst case are limiting VRAM or GTT. 1379 * Note: GTT start, end, size should be initialized before calling this 1387 /* leave room for at least 512M GTT */ r600_vram_gtt_location()
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H A D | radeon_legacy_crtc.c | 468 /* if scanout was in GTT this really wouldn't work */ radeon_crtc_do_set_base()
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H A D | rv770.c | 1605 /* leave room for at least 512M GTT */ r700_vram_gtt_location()
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H A D | si.c | 4188 /* leave room for at least 1024M GTT */ si_vram_gtt_location()
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/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_test.c | 30 /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ amdgpu_do_test_moves() 43 * (Total GTT - IB pool - writeback page - ring buffers) / test size amdgpu_do_test_moves() 87 DRM_ERROR("Failed to create GTT object %d\n", i); amdgpu_do_test_moves() 96 DRM_ERROR("Failed to pin GTT object %d\n", i); amdgpu_do_test_moves() 102 DRM_ERROR("Failed to map GTT object %d\n", i); amdgpu_do_test_moves() 117 DRM_ERROR("Failed GTT->VRAM copy %d\n", i); amdgpu_do_test_moves() 123 DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); amdgpu_do_test_moves() 140 DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " amdgpu_do_test_moves() 141 "expected 0x%p (GTT/VRAM offset " amdgpu_do_test_moves() 162 DRM_ERROR("Failed VRAM->GTT copy %d\n", i); amdgpu_do_test_moves() 168 DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); amdgpu_do_test_moves() 176 DRM_ERROR("Failed to map GTT object after copy %d\n", i); amdgpu_do_test_moves() 185 DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " amdgpu_do_test_moves() 186 "expected 0x%p (VRAM/GTT offset " amdgpu_do_test_moves() 202 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", amdgpu_do_test_moves()
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H A D | amdgpu_benchmark.c | 166 /* simple test, VRAM to GTT and GTT to VRAM */ amdgpu_benchmark() 178 /* GTT to VRAM, buffer size sweep, powers of 2 */ amdgpu_benchmark() 185 /* VRAM to GTT, buffer size sweep, powers of 2 */ amdgpu_benchmark() 199 /* GTT to VRAM, buffer size sweep, common modes */ amdgpu_benchmark() 206 /* VRAM to GTT, buffer size sweep, common modes */ amdgpu_benchmark()
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H A D | amdgpu_prime.c | 92 /* pin buffer into GTT */ amdgpu_gem_prime_pin()
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H A D | amdgpu_device.c | 576 * amdgpu_gtt_location - try to find GTT location 580 * Function will place try to place GTT before or after VRAM. 582 * If GTT size is bigger than space left then we ajust GTT size. 585 * FIXME: when reducing GTT size align new size on power of 2. 595 dev_warn(adev->dev, "limiting GTT\n"); amdgpu_gtt_location() 601 dev_warn(adev->dev, "limiting GTT\n"); amdgpu_gtt_location() 607 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", amdgpu_gtt_location()
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H A D | amdgpu_vm.c | 294 * @gtt_flags: GTT hw access flags 536 * @gtt_flags: GTT hw mapping flags 695 * @gtt_flags: flags as they are used for GTT
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H A D | amdgpu_ttm.c | 906 DRM_ERROR("Failed initializing GTT heap.\n"); amdgpu_ttm_init() 909 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", amdgpu_ttm_init()
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H A D | amdgpu_cgs.c | 96 /* pin buffer into GTT */ amdgpu_cgs_gmap_kmem()
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H A D | amdgpu_gem.c | 713 placement = " GTT"; amdgpu_debugfs_gem_info()
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H A D | amdgpu_cs.c | 326 * a dozen IBs to move all buffers to VRAM if they are in GTT. amdgpu_cs_get_threshold_for_moves()
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H A D | gmc_v7_0.c | 276 /* leave room for at least 1024M GTT */ gmc_v7_0_vram_gtt_location()
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H A D | gmc_v8_0.c | 317 /* leave room for at least 1024M GTT */ gmc_v8_0_vram_gtt_location()
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/linux-4.4.14/drivers/net/ethernet/qlogic/qed/ |
H A D | qed_init_ops.h | 104 * Initialize GTT global windows and set admin window 105 * related params of GTT/PTT to default values.
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H A D | qed_hw.h | 58 * @brief qed_gtt_init - Initialize GTT windows
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H A D | qed_dev.c | 477 /* Program GTT windows */ qed_hw_init_common()
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/linux-4.4.14/drivers/char/agp/ |
H A D | intel-gtt.c | 2 * Intel GTT (Graphics Translation Table) routines 5 * a agp driver! GTT support ended up here for purely historical reasons: The 7 * the GTT. And the drm provides a default interface for graphic devices sitting 8 * on an agp port. So it made sense to fake the GTT support as an agp port to 48 /* Chipset specific GTT setup */ 491 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ i965_gtt_total_entries() 515 /* On previous hardware, the GTT size was just what was intel_gtt_total_entries() 574 * unmapping anything from the GTT when VT-d is enabled. 758 "failed to enable the GTT: GMCH_CTRL=%x\n", intel_enable_gtt() 774 "failed to enable the GTT: PGETBL=%x [expected %x]\n", intel_enable_gtt() 852 * per-page addr for GTT */ intel_gtt_insert_sg_entries()
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H A D | intel-agp.h | 2 * Common Intel AGPGART and GTT definitions.
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/linux-4.4.14/drivers/gpu/drm/i915/ |
H A D | i915_gem_tiling.c | 116 /* Is the current GTT allocation valid for the change in tiling? */ 220 * the next fenced (either through the GTT or by the BLT unit i915_gem_set_tiling() 249 /* Force the fence to be reacquired for GTT access */ i915_gem_set_tiling()
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H A D | i915_guc_reg.h | 62 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
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H A D | i915_gem.c | 331 * remains coherent i.e. in the GTT domain, like shmem_pwrite. i915_gem_phys_pwrite() 760 * user into the GTT, uncached. 1080 /* We can only do the GTT pwrite on untiled buffers, as otherwise i915_gem_pwrite_ioctl() 1489 * safe to unbind from the GTT or access from the CPU. 1612 * through the mmap ioctl's mapping or a GTT mapping. 1774 * i915_gem_fault - fault a page into the GTT 1778 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped 1780 * the GTT (if needed), allocating and programming a fence register (again, 1785 * from the GTT and/or fence registers to make room. So performance may 1786 * suffer if the GTT working set is large or there are few fence registers 1821 /* Access to snoopable pages through the GTT is incoherent. */ i915_gem_fault() 1842 /* Now pin it into the GTT if needed */ i915_gem_fault() 1855 /* Finally, remap it using the new GTT offset */ i915_gem_fault() 1956 * object through the GTT and then lose the fence register due to 2004 * i915_gem_get_gtt_alignment - return required GTT alignment for an object 2007 * Return the required GTT alignment for an object, taking into account 2015 * Minimum alignment is 4k (GTT page size), but might be greater i915_gem_get_gtt_alignment() 2111 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing 2113 * @data: GTT mapping ioctl data 2120 * The fault handler will take care of binding the object into the GTT 2256 * wasn't in the GTT, there shouldn't be any way it could have been in i915_gem_object_get_pages_gtt() 3256 /* Wait for any direct GTT access to complete */ i915_gem_object_finish_gtt() 3415 * Finds free space in the GTT aperture and binds the object or a view of it 3600 /** Flushes the GTT write domain for the object if it's dirty. */ 3609 /* No actual flushing is required for the GTT write domain. Writes i915_gem_object_flush_gtt_write_domain() 3614 * the GTT land before any writes to the device, such as updates to i915_gem_object_flush_gtt_write_domain() 3652 * Moves a single object to the GTT read, and possibly write domain. 3687 * GTT domain upon first access. i915_gem_object_set_to_gtt_domain() 3723 * across all GTT and the contents of the backing storage will be coherent, 3782 /* Access to snoopable pages through the GTT is i915_gem_object_set_cache_level() 3786 * then double check if the GTT mapping is still i915_gem_object_set_cache_level() 3791 /* As we no longer need a fence for GTT access, i915_gem_object_set_cache_level() 3803 * so no GTT access or the architecture is fully i915_gem_object_set_cache_level() 3804 * coherent. In such cases, existing GTT mmaps i915_gem_object_set_cache_level()
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H A D | i915_gem_stolen.c | 187 /* make sure we don't clobber the GTT if it's within stolen memory */ i915_stolen_to_physical() 222 DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n", i915_stolen_to_physical() 675 /* To simplify the initialisation sequence between KMS and GTT, i915_gem_object_create_stolen_for_preallocated() 677 * setting up the GTT space. The actual reservation will occur i915_gem_object_create_stolen_for_preallocated() 685 DRM_DEBUG_KMS("failed to allocate stolen GTT space\n"); i915_gem_object_create_stolen_for_preallocated()
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H A D | i915_gem_gtt.h | 216 * How many users have pinned this object in GTT space. The following 300 * are ready to unbind, but are still in the GTT. 305 * as merely being GTT-bound shouldn't prevent its being 340 * portion of the GTT which can be mapped by the CPU and remain both coherent
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H A D | i915_gem_fence.c | 33 * wrap a given range of the global GTT. Each platform has only a fairly limited 36 * Fences are used to detile GTT memory mappings. They're also connected to the 55 * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed. 280 * if the kernel wants to do untiled GTT access. 352 * When mapping objects through the GTT, userspace wants to be able to write
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H A D | i915_gem_userptr.c | 396 * attempt to reap the vma, and if we were holding a GTT mmap i915_gem_userptr_init__mm_struct() 541 * a GTT mmapping (possible with a MAP_FIXED) - then when we have __i915_gem_userptr_set_active() 685 * the vma between us binding this page into the GTT and completion i915_gem_userptr_get_pages() 806 * space (e.g. it must not be a GTT mmapping of another object). 807 * 3. We only allow a bo as large as we could in theory map into the GTT, 808 * that is we limit the size to the total size of the GTT.
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H A D | i915_gem_gtt.c | 35 * DOC: Global GTT views 39 * Historically objects could exists (be bound) in global GTT space only as 2005 * size. We allocate at the top of the GTT to avoid fragmentation. gen6_ppgtt_allocate_page_directories() 2104 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", gen6_ppgtt_init() 2228 * unmapping anything from the GTT when VT-d is enabled. 2386 * within the global GTT as well as accessible by the GPU through the GMADR 2685 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", i915_gem_setup_global_gtt() 2853 * On BXT writes larger than 64 bit to the GTT pagetable range will be ggtt_probe_common() 2857 * readback check when writing GTT PTE entries. ggtt_probe_common() 2930 * - CPU GTT (GMADR->GGTT->no snoop->memory) chv_setup_private_ppat() 3121 /* GMADR is the PCI mmio aperture into the global GTT. */ i915_gem_gtt_init() 3125 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); i915_gem_gtt_init() 3152 /* First fill our portion of the GTT with scratch pages */ i915_gem_restore_gtt_mappings()
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H A D | i915_dma.c | 919 /* Before gen4, the registers and the GTT are behind different BARs. i915_driver_load() 920 * However, from gen4 onwards, the registers and the GTT are shared i915_driver_load() 922 * clobbering the GTT which we want ioremap_wc instead. Fortunately, i915_driver_load() 1243 * Additionally, in the non-mode setting case, we'll tear down the GTT
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H A D | intel_guc_loader.c | 222 * transfer between GTT locations. This functionality is left out of the API 312 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ guc_ucode_xfer()
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H A D | i915_gem_execbuffer.c | 735 /* Attempt to pin all of the buffers into the GTT. i915_gem_execbuffer_reserve() 738 * 1a. Unbind all objects that do not match the GTT constraints for i915_gem_execbuffer_reserve() 1315 * very low in the GTT. Ensure this doesn't happen. eb_get_batch() 1465 /* Move the objects en-masse into the GTT, evicting if necessary. */ i915_gem_do_execbuffer()
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H A D | i915_drv.h | 1260 /** Memory allocator for GTT stolen memory */ 1262 /** Protects the usage of the GTT stolen memory allocator. This is 1270 * List of objects which are not bound to the GTT (thus 1276 /** Usable portion of the GTT for GEM */ 1279 /** PPGTT used for aliasing the PPGTT with the GTT */ 1997 * of pages before to binding them into the GTT, and put_pages() is 2003 * pages to a different memory domain within the GTT). put_pages() 2064 * to the GTT 2070 * as needed when mapped into the GTT.
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H A D | i915_trace.h | 377 __entry->gtt ? "GTT" : "CPU",
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H A D | intel_fbdev.c | 163 /* Flush everything out, we'll be doing GTT only from now on */ intelfb_alloc()
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H A D | intel_runtime_pm.c | 2075 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2097 * code to ensure the GTT or GT is on).
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H A D | i915_gem_context.c | 279 * default context also requires GTT space which may not i915_gem_create_context()
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H A D | i915_gpu_error.c | 760 * the hang if we could strip the GTT offset information from it.
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H A D | i915_guc_submission.c | 672 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ gem_allocate_guc_obj()
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H A D | intel_fbc.c | 961 * cannot be unpinned (and have its GTT offset and fence revoked) __intel_fbc_update()
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H A D | intel_overlay.c | 1418 DRM_ERROR("failed to move overlay register bo into the GTT\n"); intel_setup_overlay()
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H A D | i915_drv.c | 925 * Everything depends on having the GTT running, so we need to start i915_reset()
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H A D | intel_pm.c | 6635 * GTT cache may not work with big pages, so if those 6636 * are ever enabled GTT cache may need to be disabled. 6917 * GTT cache may not work with big pages, so if those cherryview_init_clock_gating() 6918 * are ever enabled GTT cache may need to be disabled. cherryview_init_clock_gating()
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H A D | i915_debugfs.c | 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", i915_gem_stolen_list_info() 557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", i915_gem_gtt_info()
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H A D | intel_ringbuffer.c | 1975 * GTT. To generalise, it appears that all !llc init_status_page()
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H A D | i915_reg.h | 1789 /* Isoch request wait on GTT enable (Display A/B/C streams).
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/linux-4.4.14/drivers/gpu/drm/nouveau/ |
H A D | nouveau_prime.c | 95 /* pin buffer into GTT */ nouveau_gem_prime_pin()
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/linux-4.4.14/include/drm/ |
H A D | i915_drm.h | 48 #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
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/linux-4.4.14/include/uapi/drm/ |
H A D | i915_drm.h | 433 * Beginning offset in the GTT to be managed by the DRM memory 438 * Ending offset in the GTT to be managed by the DRM memory 612 /** GTT domain - aperture and scanout */ 618 * User's handle for a buffer to be bound into the GTT for this 668 * User's handle for a buffer to be bound into the GTT for this 795 /** Returned GTT offset of the buffer. */
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H A D | amdgpu_drm.h | 74 /* Flag that USWC attributes should be used for GTT */ 468 /* the used GTT size */ 472 /* Query information about VRAM and GTT domains */
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H A D | radeon_drm.h | 1001 #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
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/linux-4.4.14/drivers/video/fbdev/i810/ |
H A D | i810_regs.h | 84 #define GTT 0x10000 macro
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/linux-4.4.14/drivers/gpu/drm/virtio/ |
H A D | virtgpu_ttm.c | 451 DRM_ERROR("Failed initializing GTT heap.\n"); virtio_gpu_ttm_init()
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/linux-4.4.14/include/linux/qed/ |
H A D | common_hsi.h | 233 /* PTT and GTT */
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/linux-4.4.14/drivers/net/wireless/ath/ath9k/ |
H A D | main.c | 425 "GTT: Skipping interrupts\n"); ath9k_tasklet() 461 * successfully after a GTT interrupt, the GTT counter ath9k_tasklet() 704 * Enable GTT interrupts only for AR9003/AR9004 chips ath9k_start()
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H A D | debug.c | 556 PR_IS("GTT", gtt); read_file_interrupt()
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/linux-4.4.14/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_device.c | 260 /* Initialize GTT sa with 512 byte chunk size */ kgd2kfd_device_init()
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H A D | kfd_device_queue_manager.c | 514 * HPD buffer on GTT is allocated by amdkfd, no need to waste init_pipelines() 515 * space in GTT for pipelines we don't initialize init_pipelines()
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H A D | kfd_priv.h | 587 /* GTT Sub-Allocator */
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/linux-4.4.14/drivers/gpu/drm/ |
H A D | drm_gem.c | 802 * the object will be trapped, to perform migration, GTT binding, surface 855 * contain the fake offset we created when the GTT map ioctl was called on
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/linux-4.4.14/drivers/video/fbdev/intelfb/ |
H A D | intelfbhw.c | 218 /* Stolen memory size is reduced by the GTT and the popup. intelfbhw_get_memory() 219 GTT is 1K per MB of aperture size, and popup is 4K. */ intelfbhw_get_memory()
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/linux-4.4.14/drivers/iommu/ |
H A D | intel-iommu.c | 5166 pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); quirk_calpella_no_shadow_gtt()
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