1/* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27#include <linux/list_sort.h> 28#include <drm/drmP.h> 29#include <drm/amdgpu_drm.h> 30#include "amdgpu.h" 31#include "amdgpu_trace.h" 32 33#define AMDGPU_CS_MAX_PRIORITY 32u 34#define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1) 35 36/* This is based on the bucket sort with O(n) time complexity. 37 * An item with priority "i" is added to bucket[i]. The lists are then 38 * concatenated in descending order. 39 */ 40struct amdgpu_cs_buckets { 41 struct list_head bucket[AMDGPU_CS_NUM_BUCKETS]; 42}; 43 44static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b) 45{ 46 unsigned i; 47 48 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) 49 INIT_LIST_HEAD(&b->bucket[i]); 50} 51 52static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b, 53 struct list_head *item, unsigned priority) 54{ 55 /* Since buffers which appear sooner in the relocation list are 56 * likely to be used more often than buffers which appear later 57 * in the list, the sort mustn't change the ordering of buffers 58 * with the same priority, i.e. it must be stable. 59 */ 60 list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]); 61} 62 63static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b, 64 struct list_head *out_list) 65{ 66 unsigned i; 67 68 /* Connect the sorted buckets in the output list. */ 69 for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) { 70 list_splice(&b->bucket[i], out_list); 71 } 72} 73 74int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 75 u32 ip_instance, u32 ring, 76 struct amdgpu_ring **out_ring) 77{ 78 /* Right now all IPs have only one instance - multiple rings. */ 79 if (ip_instance != 0) { 80 DRM_ERROR("invalid ip instance: %d\n", ip_instance); 81 return -EINVAL; 82 } 83 84 switch (ip_type) { 85 default: 86 DRM_ERROR("unknown ip type: %d\n", ip_type); 87 return -EINVAL; 88 case AMDGPU_HW_IP_GFX: 89 if (ring < adev->gfx.num_gfx_rings) { 90 *out_ring = &adev->gfx.gfx_ring[ring]; 91 } else { 92 DRM_ERROR("only %d gfx rings are supported now\n", 93 adev->gfx.num_gfx_rings); 94 return -EINVAL; 95 } 96 break; 97 case AMDGPU_HW_IP_COMPUTE: 98 if (ring < adev->gfx.num_compute_rings) { 99 *out_ring = &adev->gfx.compute_ring[ring]; 100 } else { 101 DRM_ERROR("only %d compute rings are supported now\n", 102 adev->gfx.num_compute_rings); 103 return -EINVAL; 104 } 105 break; 106 case AMDGPU_HW_IP_DMA: 107 if (ring < adev->sdma.num_instances) { 108 *out_ring = &adev->sdma.instance[ring].ring; 109 } else { 110 DRM_ERROR("only %d SDMA rings are supported\n", 111 adev->sdma.num_instances); 112 return -EINVAL; 113 } 114 break; 115 case AMDGPU_HW_IP_UVD: 116 *out_ring = &adev->uvd.ring; 117 break; 118 case AMDGPU_HW_IP_VCE: 119 if (ring < 2){ 120 *out_ring = &adev->vce.ring[ring]; 121 } else { 122 DRM_ERROR("only two VCE rings are supported\n"); 123 return -EINVAL; 124 } 125 break; 126 } 127 return 0; 128} 129 130static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 131 struct drm_amdgpu_cs_chunk_fence *fence_data) 132{ 133 struct drm_gem_object *gobj; 134 uint32_t handle; 135 136 handle = fence_data->handle; 137 gobj = drm_gem_object_lookup(p->adev->ddev, p->filp, 138 fence_data->handle); 139 if (gobj == NULL) 140 return -EINVAL; 141 142 p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); 143 p->uf.offset = fence_data->offset; 144 145 if (amdgpu_ttm_tt_has_userptr(p->uf.bo->tbo.ttm)) { 146 drm_gem_object_unreference_unlocked(gobj); 147 return -EINVAL; 148 } 149 150 p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo); 151 p->uf_entry.prefered_domains = AMDGPU_GEM_DOMAIN_GTT; 152 p->uf_entry.allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 153 p->uf_entry.priority = 0; 154 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; 155 p->uf_entry.tv.shared = true; 156 157 drm_gem_object_unreference_unlocked(gobj); 158 return 0; 159} 160 161int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 162{ 163 union drm_amdgpu_cs *cs = data; 164 uint64_t *chunk_array_user; 165 uint64_t *chunk_array; 166 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 167 unsigned size; 168 int i; 169 int ret; 170 171 if (cs->in.num_chunks == 0) 172 return 0; 173 174 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); 175 if (!chunk_array) 176 return -ENOMEM; 177 178 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); 179 if (!p->ctx) { 180 ret = -EINVAL; 181 goto free_chunk; 182 } 183 184 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); 185 186 /* get chunks */ 187 INIT_LIST_HEAD(&p->validated); 188 chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); 189 if (copy_from_user(chunk_array, chunk_array_user, 190 sizeof(uint64_t)*cs->in.num_chunks)) { 191 ret = -EFAULT; 192 goto put_bo_list; 193 } 194 195 p->nchunks = cs->in.num_chunks; 196 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), 197 GFP_KERNEL); 198 if (!p->chunks) { 199 ret = -ENOMEM; 200 goto put_bo_list; 201 } 202 203 for (i = 0; i < p->nchunks; i++) { 204 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; 205 struct drm_amdgpu_cs_chunk user_chunk; 206 uint32_t __user *cdata; 207 208 chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; 209 if (copy_from_user(&user_chunk, chunk_ptr, 210 sizeof(struct drm_amdgpu_cs_chunk))) { 211 ret = -EFAULT; 212 i--; 213 goto free_partial_kdata; 214 } 215 p->chunks[i].chunk_id = user_chunk.chunk_id; 216 p->chunks[i].length_dw = user_chunk.length_dw; 217 218 size = p->chunks[i].length_dw; 219 cdata = (void __user *)(unsigned long)user_chunk.chunk_data; 220 p->chunks[i].user_ptr = cdata; 221 222 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); 223 if (p->chunks[i].kdata == NULL) { 224 ret = -ENOMEM; 225 i--; 226 goto free_partial_kdata; 227 } 228 size *= sizeof(uint32_t); 229 if (copy_from_user(p->chunks[i].kdata, cdata, size)) { 230 ret = -EFAULT; 231 goto free_partial_kdata; 232 } 233 234 switch (p->chunks[i].chunk_id) { 235 case AMDGPU_CHUNK_ID_IB: 236 p->num_ibs++; 237 break; 238 239 case AMDGPU_CHUNK_ID_FENCE: 240 size = sizeof(struct drm_amdgpu_cs_chunk_fence); 241 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { 242 ret = -EINVAL; 243 goto free_partial_kdata; 244 } 245 246 ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata); 247 if (ret) 248 goto free_partial_kdata; 249 250 break; 251 252 case AMDGPU_CHUNK_ID_DEPENDENCIES: 253 break; 254 255 default: 256 ret = -EINVAL; 257 goto free_partial_kdata; 258 } 259 } 260 261 262 p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); 263 if (!p->ibs) { 264 ret = -ENOMEM; 265 goto free_all_kdata; 266 } 267 268 kfree(chunk_array); 269 return 0; 270 271free_all_kdata: 272 i = p->nchunks - 1; 273free_partial_kdata: 274 for (; i >= 0; i--) 275 drm_free_large(p->chunks[i].kdata); 276 kfree(p->chunks); 277put_bo_list: 278 if (p->bo_list) 279 amdgpu_bo_list_put(p->bo_list); 280 amdgpu_ctx_put(p->ctx); 281free_chunk: 282 kfree(chunk_array); 283 284 return ret; 285} 286 287/* Returns how many bytes TTM can move per IB. 288 */ 289static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) 290{ 291 u64 real_vram_size = adev->mc.real_vram_size; 292 u64 vram_usage = atomic64_read(&adev->vram_usage); 293 294 /* This function is based on the current VRAM usage. 295 * 296 * - If all of VRAM is free, allow relocating the number of bytes that 297 * is equal to 1/4 of the size of VRAM for this IB. 298 299 * - If more than one half of VRAM is occupied, only allow relocating 300 * 1 MB of data for this IB. 301 * 302 * - From 0 to one half of used VRAM, the threshold decreases 303 * linearly. 304 * __________________ 305 * 1/4 of -|\ | 306 * VRAM | \ | 307 * | \ | 308 * | \ | 309 * | \ | 310 * | \ | 311 * | \ | 312 * | \________|1 MB 313 * |----------------| 314 * VRAM 0 % 100 % 315 * used used 316 * 317 * Note: It's a threshold, not a limit. The threshold must be crossed 318 * for buffer relocations to stop, so any buffer of an arbitrary size 319 * can be moved as long as the threshold isn't crossed before 320 * the relocation takes place. We don't want to disable buffer 321 * relocations completely. 322 * 323 * The idea is that buffers should be placed in VRAM at creation time 324 * and TTM should only do a minimum number of relocations during 325 * command submission. In practice, you need to submit at least 326 * a dozen IBs to move all buffers to VRAM if they are in GTT. 327 * 328 * Also, things can get pretty crazy under memory pressure and actual 329 * VRAM usage can change a lot, so playing safe even at 50% does 330 * consistently increase performance. 331 */ 332 333 u64 half_vram = real_vram_size >> 1; 334 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 335 u64 bytes_moved_threshold = half_free_vram >> 1; 336 return max(bytes_moved_threshold, 1024*1024ull); 337} 338 339int amdgpu_cs_list_validate(struct amdgpu_device *adev, 340 struct amdgpu_vm *vm, 341 struct list_head *validated) 342{ 343 struct amdgpu_bo_list_entry *lobj; 344 struct amdgpu_bo *bo; 345 u64 bytes_moved = 0, initial_bytes_moved; 346 u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev); 347 int r; 348 349 list_for_each_entry(lobj, validated, tv.head) { 350 bo = lobj->robj; 351 if (!bo->pin_count) { 352 u32 domain = lobj->prefered_domains; 353 u32 current_domain = 354 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 355 356 /* Check if this buffer will be moved and don't move it 357 * if we have moved too many buffers for this IB already. 358 * 359 * Note that this allows moving at least one buffer of 360 * any size, because it doesn't take the current "bo" 361 * into account. We don't want to disallow buffer moves 362 * completely. 363 */ 364 if ((lobj->allowed_domains & current_domain) != 0 && 365 (domain & current_domain) == 0 && /* will be moved */ 366 bytes_moved > bytes_moved_threshold) { 367 /* don't move it */ 368 domain = current_domain; 369 } 370 371 retry: 372 amdgpu_ttm_placement_from_domain(bo, domain); 373 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); 374 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 375 bytes_moved += atomic64_read(&adev->num_bytes_moved) - 376 initial_bytes_moved; 377 378 if (unlikely(r)) { 379 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) { 380 domain = lobj->allowed_domains; 381 goto retry; 382 } 383 return r; 384 } 385 } 386 lobj->bo_va = amdgpu_vm_bo_find(vm, bo); 387 } 388 return 0; 389} 390 391static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) 392{ 393 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 394 struct amdgpu_cs_buckets buckets; 395 struct list_head duplicates; 396 bool need_mmap_lock = false; 397 int i, r; 398 399 if (p->bo_list) { 400 need_mmap_lock = p->bo_list->has_userptr; 401 amdgpu_cs_buckets_init(&buckets); 402 for (i = 0; i < p->bo_list->num_entries; i++) 403 amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, 404 p->bo_list->array[i].priority); 405 406 amdgpu_cs_buckets_get_list(&buckets, &p->validated); 407 } 408 409 p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm, 410 &p->validated); 411 412 if (p->uf.bo) 413 list_add(&p->uf_entry.tv.head, &p->validated); 414 415 if (need_mmap_lock) 416 down_read(¤t->mm->mmap_sem); 417 418 INIT_LIST_HEAD(&duplicates); 419 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); 420 if (unlikely(r != 0)) 421 goto error_reserve; 422 423 r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated); 424 if (r) 425 goto error_validate; 426 427 r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates); 428 429error_validate: 430 if (r) 431 ttm_eu_backoff_reservation(&p->ticket, &p->validated); 432 433error_reserve: 434 if (need_mmap_lock) 435 up_read(¤t->mm->mmap_sem); 436 437 return r; 438} 439 440static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) 441{ 442 struct amdgpu_bo_list_entry *e; 443 int r; 444 445 list_for_each_entry(e, &p->validated, tv.head) { 446 struct reservation_object *resv = e->robj->tbo.resv; 447 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); 448 449 if (r) 450 return r; 451 } 452 return 0; 453} 454 455static int cmp_size_smaller_first(void *priv, struct list_head *a, 456 struct list_head *b) 457{ 458 struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); 459 struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); 460 461 /* Sort A before B if A is smaller. */ 462 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 463} 464 465/** 466 * cs_parser_fini() - clean parser states 467 * @parser: parser structure holding parsing context. 468 * @error: error number 469 * 470 * If error is set than unvalidate buffer, otherwise just free memory 471 * used by parsing context. 472 **/ 473static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) 474{ 475 unsigned i; 476 477 if (!error) { 478 /* Sort the buffer list from the smallest to largest buffer, 479 * which affects the order of buffers in the LRU list. 480 * This assures that the smallest buffers are added first 481 * to the LRU list, so they are likely to be later evicted 482 * first, instead of large buffers whose eviction is more 483 * expensive. 484 * 485 * This slightly lowers the number of bytes moved by TTM 486 * per frame under memory pressure. 487 */ 488 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 489 490 ttm_eu_fence_buffer_objects(&parser->ticket, 491 &parser->validated, 492 parser->fence); 493 } else if (backoff) { 494 ttm_eu_backoff_reservation(&parser->ticket, 495 &parser->validated); 496 } 497 fence_put(parser->fence); 498 499 if (parser->ctx) 500 amdgpu_ctx_put(parser->ctx); 501 if (parser->bo_list) 502 amdgpu_bo_list_put(parser->bo_list); 503 504 drm_free_large(parser->vm_bos); 505 for (i = 0; i < parser->nchunks; i++) 506 drm_free_large(parser->chunks[i].kdata); 507 kfree(parser->chunks); 508 if (parser->ibs) 509 for (i = 0; i < parser->num_ibs; i++) 510 amdgpu_ib_free(parser->adev, &parser->ibs[i]); 511 kfree(parser->ibs); 512 amdgpu_bo_unref(&parser->uf.bo); 513 amdgpu_bo_unref(&parser->uf_entry.robj); 514} 515 516static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, 517 struct amdgpu_vm *vm) 518{ 519 struct amdgpu_device *adev = p->adev; 520 struct amdgpu_bo_va *bo_va; 521 struct amdgpu_bo *bo; 522 int i, r; 523 524 r = amdgpu_vm_update_page_directory(adev, vm); 525 if (r) 526 return r; 527 528 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence); 529 if (r) 530 return r; 531 532 r = amdgpu_vm_clear_freed(adev, vm); 533 if (r) 534 return r; 535 536 if (p->bo_list) { 537 for (i = 0; i < p->bo_list->num_entries; i++) { 538 struct fence *f; 539 540 /* ignore duplicates */ 541 bo = p->bo_list->array[i].robj; 542 if (!bo) 543 continue; 544 545 bo_va = p->bo_list->array[i].bo_va; 546 if (bo_va == NULL) 547 continue; 548 549 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); 550 if (r) 551 return r; 552 553 f = bo_va->last_pt_update; 554 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f); 555 if (r) 556 return r; 557 } 558 559 } 560 561 r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); 562 563 if (amdgpu_vm_debug && p->bo_list) { 564 /* Invalidate all BOs to test for userspace bugs */ 565 for (i = 0; i < p->bo_list->num_entries; i++) { 566 /* ignore duplicates */ 567 bo = p->bo_list->array[i].robj; 568 if (!bo) 569 continue; 570 571 amdgpu_vm_bo_invalidate(adev, bo); 572 } 573 } 574 575 return r; 576} 577 578static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, 579 struct amdgpu_cs_parser *parser) 580{ 581 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 582 struct amdgpu_vm *vm = &fpriv->vm; 583 struct amdgpu_ring *ring; 584 int i, r; 585 586 if (parser->num_ibs == 0) 587 return 0; 588 589 /* Only for UVD/VCE VM emulation */ 590 for (i = 0; i < parser->num_ibs; i++) { 591 ring = parser->ibs[i].ring; 592 if (ring->funcs->parse_cs) { 593 r = amdgpu_ring_parse_cs(ring, parser, i); 594 if (r) 595 return r; 596 } 597 } 598 599 r = amdgpu_bo_vm_update_pte(parser, vm); 600 if (!r) 601 amdgpu_cs_sync_rings(parser); 602 603 return r; 604} 605 606static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) 607{ 608 if (r == -EDEADLK) { 609 r = amdgpu_gpu_reset(adev); 610 if (!r) 611 r = -EAGAIN; 612 } 613 return r; 614} 615 616static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 617 struct amdgpu_cs_parser *parser) 618{ 619 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 620 struct amdgpu_vm *vm = &fpriv->vm; 621 int i, j; 622 int r; 623 624 for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { 625 struct amdgpu_cs_chunk *chunk; 626 struct amdgpu_ib *ib; 627 struct drm_amdgpu_cs_chunk_ib *chunk_ib; 628 struct amdgpu_ring *ring; 629 630 chunk = &parser->chunks[i]; 631 ib = &parser->ibs[j]; 632 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; 633 634 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) 635 continue; 636 637 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, 638 chunk_ib->ip_instance, chunk_ib->ring, 639 &ring); 640 if (r) 641 return r; 642 643 if (ring->funcs->parse_cs) { 644 struct amdgpu_bo_va_mapping *m; 645 struct amdgpu_bo *aobj = NULL; 646 uint64_t offset; 647 uint8_t *kptr; 648 649 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, 650 &aobj); 651 if (!aobj) { 652 DRM_ERROR("IB va_start is invalid\n"); 653 return -EINVAL; 654 } 655 656 if ((chunk_ib->va_start + chunk_ib->ib_bytes) > 657 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { 658 DRM_ERROR("IB va_start+ib_bytes is invalid\n"); 659 return -EINVAL; 660 } 661 662 /* the IB should be reserved at this point */ 663 r = amdgpu_bo_kmap(aobj, (void **)&kptr); 664 if (r) { 665 return r; 666 } 667 668 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; 669 kptr += chunk_ib->va_start - offset; 670 671 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); 672 if (r) { 673 DRM_ERROR("Failed to get ib !\n"); 674 return r; 675 } 676 677 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); 678 amdgpu_bo_kunmap(aobj); 679 } else { 680 r = amdgpu_ib_get(ring, vm, 0, ib); 681 if (r) { 682 DRM_ERROR("Failed to get ib !\n"); 683 return r; 684 } 685 686 ib->gpu_addr = chunk_ib->va_start; 687 } 688 689 ib->length_dw = chunk_ib->ib_bytes / 4; 690 ib->flags = chunk_ib->flags; 691 ib->ctx = parser->ctx; 692 j++; 693 } 694 695 if (!parser->num_ibs) 696 return 0; 697 698 /* add GDS resources to first IB */ 699 if (parser->bo_list) { 700 struct amdgpu_bo *gds = parser->bo_list->gds_obj; 701 struct amdgpu_bo *gws = parser->bo_list->gws_obj; 702 struct amdgpu_bo *oa = parser->bo_list->oa_obj; 703 struct amdgpu_ib *ib = &parser->ibs[0]; 704 705 if (gds) { 706 ib->gds_base = amdgpu_bo_gpu_offset(gds); 707 ib->gds_size = amdgpu_bo_size(gds); 708 } 709 if (gws) { 710 ib->gws_base = amdgpu_bo_gpu_offset(gws); 711 ib->gws_size = amdgpu_bo_size(gws); 712 } 713 if (oa) { 714 ib->oa_base = amdgpu_bo_gpu_offset(oa); 715 ib->oa_size = amdgpu_bo_size(oa); 716 } 717 } 718 /* wrap the last IB with user fence */ 719 if (parser->uf.bo) { 720 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; 721 722 /* UVD & VCE fw doesn't support user fences */ 723 if (ib->ring->type == AMDGPU_RING_TYPE_UVD || 724 ib->ring->type == AMDGPU_RING_TYPE_VCE) 725 return -EINVAL; 726 727 ib->user = &parser->uf; 728 } 729 730 return 0; 731} 732 733static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 734 struct amdgpu_cs_parser *p) 735{ 736 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 737 struct amdgpu_ib *ib; 738 int i, j, r; 739 740 if (!p->num_ibs) 741 return 0; 742 743 /* Add dependencies to first IB */ 744 ib = &p->ibs[0]; 745 for (i = 0; i < p->nchunks; ++i) { 746 struct drm_amdgpu_cs_chunk_dep *deps; 747 struct amdgpu_cs_chunk *chunk; 748 unsigned num_deps; 749 750 chunk = &p->chunks[i]; 751 752 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) 753 continue; 754 755 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; 756 num_deps = chunk->length_dw * 4 / 757 sizeof(struct drm_amdgpu_cs_chunk_dep); 758 759 for (j = 0; j < num_deps; ++j) { 760 struct amdgpu_ring *ring; 761 struct amdgpu_ctx *ctx; 762 struct fence *fence; 763 764 r = amdgpu_cs_get_ring(adev, deps[j].ip_type, 765 deps[j].ip_instance, 766 deps[j].ring, &ring); 767 if (r) 768 return r; 769 770 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); 771 if (ctx == NULL) 772 return -EINVAL; 773 774 fence = amdgpu_ctx_get_fence(ctx, ring, 775 deps[j].handle); 776 if (IS_ERR(fence)) { 777 r = PTR_ERR(fence); 778 amdgpu_ctx_put(ctx); 779 return r; 780 781 } else if (fence) { 782 r = amdgpu_sync_fence(adev, &ib->sync, fence); 783 fence_put(fence); 784 amdgpu_ctx_put(ctx); 785 if (r) 786 return r; 787 } 788 } 789 } 790 791 return 0; 792} 793 794static int amdgpu_cs_free_job(struct amdgpu_job *job) 795{ 796 int i; 797 if (job->ibs) 798 for (i = 0; i < job->num_ibs; i++) 799 amdgpu_ib_free(job->adev, &job->ibs[i]); 800 kfree(job->ibs); 801 if (job->uf.bo) 802 amdgpu_bo_unref(&job->uf.bo); 803 return 0; 804} 805 806int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 807{ 808 struct amdgpu_device *adev = dev->dev_private; 809 union drm_amdgpu_cs *cs = data; 810 struct amdgpu_cs_parser parser = {}; 811 bool reserved_buffers = false; 812 int i, r; 813 814 if (!adev->accel_working) 815 return -EBUSY; 816 817 parser.adev = adev; 818 parser.filp = filp; 819 820 r = amdgpu_cs_parser_init(&parser, data); 821 if (r) { 822 DRM_ERROR("Failed to initialize parser !\n"); 823 amdgpu_cs_parser_fini(&parser, r, false); 824 r = amdgpu_cs_handle_lockup(adev, r); 825 return r; 826 } 827 r = amdgpu_cs_parser_relocs(&parser); 828 if (r == -ENOMEM) 829 DRM_ERROR("Not enough memory for command submission!\n"); 830 else if (r && r != -ERESTARTSYS) 831 DRM_ERROR("Failed to process the buffer list %d!\n", r); 832 else if (!r) { 833 reserved_buffers = true; 834 r = amdgpu_cs_ib_fill(adev, &parser); 835 } 836 837 if (!r) { 838 r = amdgpu_cs_dependencies(adev, &parser); 839 if (r) 840 DRM_ERROR("Failed in the dependencies handling %d!\n", r); 841 } 842 843 if (r) 844 goto out; 845 846 for (i = 0; i < parser.num_ibs; i++) 847 trace_amdgpu_cs(&parser, i); 848 849 r = amdgpu_cs_ib_vm_chunk(adev, &parser); 850 if (r) 851 goto out; 852 853 if (amdgpu_enable_scheduler && parser.num_ibs) { 854 struct amdgpu_ring * ring = parser.ibs->ring; 855 struct amd_sched_fence *fence; 856 struct amdgpu_job *job; 857 858 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); 859 if (!job) { 860 r = -ENOMEM; 861 goto out; 862 } 863 864 job->base.sched = &ring->sched; 865 job->base.s_entity = &parser.ctx->rings[ring->idx].entity; 866 job->adev = parser.adev; 867 job->owner = parser.filp; 868 job->free_job = amdgpu_cs_free_job; 869 870 job->ibs = parser.ibs; 871 job->num_ibs = parser.num_ibs; 872 parser.ibs = NULL; 873 parser.num_ibs = 0; 874 875 if (job->ibs[job->num_ibs - 1].user) { 876 job->uf = parser.uf; 877 job->ibs[job->num_ibs - 1].user = &job->uf; 878 parser.uf.bo = NULL; 879 } 880 881 fence = amd_sched_fence_create(job->base.s_entity, 882 parser.filp); 883 if (!fence) { 884 r = -ENOMEM; 885 amdgpu_cs_free_job(job); 886 kfree(job); 887 goto out; 888 } 889 job->base.s_fence = fence; 890 parser.fence = fence_get(&fence->base); 891 892 cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring, 893 &fence->base); 894 job->ibs[job->num_ibs - 1].sequence = cs->out.handle; 895 896 trace_amdgpu_cs_ioctl(job); 897 amd_sched_entity_push_job(&job->base); 898 899 } else { 900 struct amdgpu_fence *fence; 901 902 r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs, 903 parser.filp); 904 fence = parser.ibs[parser.num_ibs - 1].fence; 905 parser.fence = fence_get(&fence->base); 906 cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence; 907 } 908 909out: 910 amdgpu_cs_parser_fini(&parser, r, reserved_buffers); 911 r = amdgpu_cs_handle_lockup(adev, r); 912 return r; 913} 914 915/** 916 * amdgpu_cs_wait_ioctl - wait for a command submission to finish 917 * 918 * @dev: drm device 919 * @data: data from userspace 920 * @filp: file private 921 * 922 * Wait for the command submission identified by handle to finish. 923 */ 924int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, 925 struct drm_file *filp) 926{ 927 union drm_amdgpu_wait_cs *wait = data; 928 struct amdgpu_device *adev = dev->dev_private; 929 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); 930 struct amdgpu_ring *ring = NULL; 931 struct amdgpu_ctx *ctx; 932 struct fence *fence; 933 long r; 934 935 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, 936 wait->in.ring, &ring); 937 if (r) 938 return r; 939 940 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); 941 if (ctx == NULL) 942 return -EINVAL; 943 944 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); 945 if (IS_ERR(fence)) 946 r = PTR_ERR(fence); 947 else if (fence) { 948 r = fence_wait_timeout(fence, true, timeout); 949 fence_put(fence); 950 } else 951 r = 1; 952 953 amdgpu_ctx_put(ctx); 954 if (r < 0) 955 return r; 956 957 memset(wait, 0, sizeof(*wait)); 958 wait->out.status = (r == 0); 959 960 return 0; 961} 962 963/** 964 * amdgpu_cs_find_bo_va - find bo_va for VM address 965 * 966 * @parser: command submission parser context 967 * @addr: VM address 968 * @bo: resulting BO of the mapping found 969 * 970 * Search the buffer objects in the command submission context for a certain 971 * virtual memory address. Returns allocation structure when found, NULL 972 * otherwise. 973 */ 974struct amdgpu_bo_va_mapping * 975amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 976 uint64_t addr, struct amdgpu_bo **bo) 977{ 978 struct amdgpu_bo_list_entry *reloc; 979 struct amdgpu_bo_va_mapping *mapping; 980 981 addr /= AMDGPU_GPU_PAGE_SIZE; 982 983 list_for_each_entry(reloc, &parser->validated, tv.head) { 984 if (!reloc->bo_va) 985 continue; 986 987 list_for_each_entry(mapping, &reloc->bo_va->valids, list) { 988 if (mapping->it.start > addr || 989 addr > mapping->it.last) 990 continue; 991 992 *bo = reloc->bo_va->bo; 993 return mapping; 994 } 995 996 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) { 997 if (mapping->it.start > addr || 998 addr > mapping->it.last) 999 continue; 1000 1001 *bo = reloc->bo_va->bo; 1002 return mapping; 1003 } 1004 } 1005 1006 return NULL; 1007} 1008