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/linux-4.4.14/Documentation/devicetree/bindings/dma/
Ddma.txt1 * Generic DMA Controller and DMA request bindings
3 Generic binding to provide a way for a driver using DMA Engine to retrieve the
4 DMA request or channel information that goes from a hardware device to a DMA
8 * DMA controller
11 - #dma-cells: Must be at least 1. Used to provide DMA controller
12 specific information. See DMA client binding below for
16 - dma-channels: Number of DMA channels supported by the controller.
17 - dma-requests: Number of DMA request signals supported by the
34 * DMA router
36 DMA routers are transparent IP blocks used to route DMA request lines from
[all …]
Dfsl-imx-dma.txt1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
16 - #dma-channels : Number of DMA channels supported. Should be 16.
17 - #dma-requests : Number of DMA requests supported.
30 * DMA client
[all …]
Dti-dma-crossbar.txt1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to to match with the DMA controller's dma-cells
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
19 When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
20 the DMA event number as crossbar ID (input to the DMA crossbar).
23 dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC
[all …]
Dmpc512x-dma.txt1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
29 DMA clients must use the format described in dma/dma.txt file.
Dshdma.txt3 Sh-/r-mobile and r-car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
22 * DMA controller
73 * DMA client
[all …]
Dmmp-dma.txt1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - #dma-channels: Number of DMA channels supported by the controller (defaults
24 * while DMA controller may not able to distinguish the irq channel
39 * Dmaengine driver (DMA controller) distinguish irq channel via
50 Marvell Two Channel DMA Controller used specifically for audio
55 - reg: Should contain DMA registers location and length.
56 - interrupts: Either contain all of the per-channel DMA interrupts
Dapm-xgene-dma.txt1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
6 Required properties for DMA interfaces:
11 1st - DMA control and status register address space.
15 - interrupts: DMA has 5 interrupts sources. 1st interrupt is
16 DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
17 are completion interrupts for each DMA channels.
Dbrcm,bcm2835-dma.txt1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
44 DMA clients connected to the BCM2835 DMA controller must use the format
Datmel-dma.txt1 * Atmel Direct Memory Access Controller (DMA)
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt.
19 DMA clients connected to the Atmel DMA controller must use the format
24 1. A phandle pointing to the DMA controller.
27 3. Parameters for the at91 DMA configuration register which are device
Djz4780-dma.txt1 * Ingenic JZ4780 DMA Controller
6 - reg: Should contain the DMA controller registers location and length.
7 - interrupts: Should contain the interrupt specifier of the DMA controller.
11 DMA clients (see below).
37 DMA clients must use the format described in dma.txt, giving a phandle to the
38 DMA controller plus the following 2 integer cells:
40 1. Request type: The DMA request type for transfers to/from the device on
45 should be reserved on the DMA controller using the ingenic,reserved-channels
Dadi,axi-dmac.txt1 Analog Device AXI-DMAC DMA controller
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
21 - adi,length-width: Width of the DMA transfer length register.
32 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
34 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
38 specifier refers to the DMA channel index.
Dtegra20-apbdma.txt1 * NVIDIA Tegra APB DMA controller
5 - reg: Should contain DMA registers location and length. This shuld include
7 - interrupts: Should contain all of the per-channel DMA interrupts.
14 - #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
15 client nodes' dmas properties. The specifier represents the DMA request
17 documentation of the APB DMA channel control register REQ_SEL field.
Dfsl-mxs-dma.txt1 * Freescale MXS DMA
6 - interrupts : Should contain the interrupt numbers of DMA channels.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
49 DMA clients connected to the MXS DMA controller must use the format
Dlpc1850-dmamux.txt1 NXP LPC18xx/43xx DMA MUX (DMA request router)
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
Dsnps-dma.txt1 * Synopsys Designware DMA Controller
8 - dma-requests: Number of DMA request lines supported, up to 16
24 general purpose DMA channel allocator. False if not passed.
44 DMA clients connected to the Designware DMA controller must use the format
48 1. A phandle pointing to the DMA controller
49 2. The DMA request line number
Drenesas,rcar-dmac.txt1 * Renesas R-Car DMA Controller Device Tree bindings
3 Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
8 Each DMA client is connected to one dedicated port of the DMAC, identified by
9 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
11 number of clients to be served, channels must be shared between multiple DMA
12 clients. The association of DMA clients to DMAC channels is fully dynamic and
32 connected to the DMA client
33 - dma-channels: number of DMA channels
Dste-dma40.txt1 * DMA40 DMA Controller
37 1. A phandle pointing to the DMA controller
40 3. The DMA request line number (only when 'use fixed channel' is set)
54 Use DMA request line number when set
113 51: memcpy TX (to be used by the DMA driver for memcpy operations)
118 56: memcpy (to be used by the DMA driver for memcpy operations)
119 57: memcpy (to be used by the DMA driver for memcpy operations)
120 58: memcpy (to be used by the DMA driver for memcpy operations)
121 59: memcpy (to be used by the DMA driver for memcpy operations)
122 60: memcpy (to be used by the DMA driver for memcpy operations)
Dste-coh901318.txt1 ST-Ericsson COH 901 318 DMA Controller
3 This is a DMA controller which has begun as a fork of the
9 - interrupts: the single DMA IRQ
12 - dma-channels: the number of DMA channels handled
Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
6 - interrupts: Must contain all the per-channel DMA interrupts.
12 node which contains the DMA request to channel mapping registers.
17 - The first cell is the peripheral's DMA request line.
18 - The second cell is a bitmap specifying to which channels the DMA request
23 - dma-channels: Number of supported DMA channels, up to 32. If not specified
Dsun4i-dma.txt1 Allwinner A10 DMA Controller
3 This driver follows the generic DMA bindings defined in dma.txt.
25 DMA clients connected to the Allwinner A10 DMA controller must use the
30 1. A phandle pointing to the DMA controller.
Dsun6i-dma.txt1 Allwinner A31 DMA Controller
3 This driver follows the generic DMA bindings defined in dma.txt.
30 DMA clients connected to the A31 DMA controller must use the format
35 1. A phandle pointing to the DMA controller.
Datmel-xdma.txt8 - reg: Should contain DMA registers location and length.
9 - interrupts: Should contain DMA interrupt.
29 * DMA clients
30 DMA clients connected to the Atmel XDMA controller must use the format
33 1. A phandle pointing to the DMA controller.
Darm-pl330.txt1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
31 mem-to-dev) should specify the DMA channel numbers and dma channel names
Dmoxa,moxart-dma.txt1 MOXA ART DMA Controller
25 DMA clients connected to the MOXA ART DMA controller must use the format
30 1. A phandle pointing to the DMA controller.
Darm-pl08x.txt1 * ARM PrimeCells PL080 and PL081 and derivatives DMA controller
14 - #dma-cells: must be <2>. First cell should contain the DMA request,
19 - dma-channels: contains the total number of DMA channels supported by the DMAC
20 - dma-requests: contains the total number of DMA requests supported by the DMAC
28 - dmas: List of DMA controller phandle, request channel and AHB master id
Dti-edma.txt4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
13 - #dma-cells: Should be set to <2>. The first number is the DMA request
92 /* DMA channel 36 executed on eDMA TC0 - low priority queue */
106 /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
119 Clients should use a single channel number per DMA request.
135 - dma-channels: Specify total DMA channels per CC
Dqcom_adm.txt1 QCOM ADM DMA Controller
5 - reg: Address range for DMA registers
38 DMA clients must use the format descripted in the dma.txt file, using a three
42 1. phandle pointing to the DMA controller
Dnbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
48 * DMA client
Dqcom_bam_dma.txt1 QCOM BAM DMA controller
8 - reg: Address range for DMA registers
29 DMA clients must use the format described in the dma.txt file, using a two cell
Drenesas,usb-dmac.txt1 * Renesas USB DMA Controller Device Tree bindings
12 port connected to the DMA client.
13 - dma-channels: number of DMA channels
Dfsl-edma.txt5 specific DMA request source can only be multiplexed by any channel of certain
58 * DMA clients
59 DMA client drivers that uses the DMA function must use the format described
Dzxdma.txt1 * ZTE ZX296702 DMA controller
5 - reg: Should contain DMA registers location and length.
Dfsl-imx-sdma.txt17 The first cell specifies the DMA request/event ID. See details below
22 The second cell of dma phandle specifies the peripheral type of DMA transfer.
71 DMA clients connected to the i.MX SDMA controller must use the format
Dk3dma.txt1 * Hisilicon K3 DMA controller
7 - reg: Should contain DMA registers location and length.
Dsirfsoc-dma.txt1 * CSR SiRFSoC DMA controller
8 - reg: Should contain DMA registers location and length.
/linux-4.4.14/Documentation/video4linux/
Dpxa_camera.txt8 This is due to DMA constraints, which transfers only planes of 8 byte
20 capture. The new buffers are "appended" at the tail of the DMA chain, and
38 | | DMA: stop | | DMA: stop | |
45 | | DMA hotlink missed | | Capture running | |
48 | | DMA: stop | / | DMA: run | | |
50 | ^ /DMA still | | channels |
51 | | capture list / running | DMA Irq End | not |
58 | DMA: run | | DMA: run | |
67 | DMA: run | | DMA: stop |
76 - "DMA: stop" means all 3 DMA channels are stopped
[all …]
Dcafe_ccic21 - alloc_bufs_at_load: Normally, the driver will not allocate any DMA
27 - dma_buf_size: The size of DMA buffers to allocate. Note that this
32 - n_dma_bufs: The controller can cycle through either two or three DMA
Dvideobuf26 scatter/gather DMA operations.
30 buffers are just as hard to use for DMA operations, but they can be
31 useful in situations where DMA is not available but virtually-contiguous
35 buffer can be unreliable on fragmented systems, but simpler DMA
289 same is normally true of contiguous-DMA drivers as well; videobuf will
293 play tricks by allocating DMA space at system boot time; videobuf does not
296 As of 2.6.31, contiguous-DMA drivers can work with a user-supplied buffer,
327 DMA; that ensures that the videobuf layer will not try to do anything with
336 For contiguous DMA drivers, the function to use is:
340 The contiguous DMA API goes out of its way to hide the kernel-space address
[all …]
/linux-4.4.14/drivers/dma/
DKconfig2 # DMA engine configuration
6 bool "DMA Engine support"
9 DMA engines can do asynchronous data transfers without
13 DMA Device drivers supported by the configured arch, it may
17 bool "DMA Engine debugging"
21 say N here. This enables DMA engine core and driver debugging.
24 bool "DMA Engine verbose debugging"
29 the DMA engine core and drivers.
34 comment "DMA Devices"
66 which can provide DMA engine support
[all …]
/linux-4.4.14/Documentation/dmaengine/
Dclient.txt1 DMA Engine API Guide
6 NOTE: For DMA Engine usage in async_tx please see:
10 Below is a guide to device driver writers on how to use the Slave-DMA API of the
11 DMA Engine. This is applicable only for slave DMA usage only.
13 The slave DMA usage consists of following steps:
14 1. Allocate a DMA slave channel
20 1. Allocate a DMA slave channel
22 Channel allocation is slightly different in the slave DMA context,
23 client drivers typically need a channel from a particular DMA
36 DMA channel.
[all …]
D00-INDEX4 -the DMA Engine API Guide.
8 - the DMA controller API.
Dprovider.txt7 Most of the Slave DMA controllers have the same general principles of
10 They have a given number of channels to use for the DMA transfers, and
19 DMA-eligible devices to the controller itself. Whenever the device
20 will want to start a transfer, it will assert a DMA request (DRQ) by
23 A very simple DMA controller would only take into account a single
34 is why most if not all of the DMA controllers can adjust this, using a
37 Moreover, some DMA controllers, whenever the RAM is used as a source
45 Our theoretical DMA controller would then only be able to do transfers
53 quite simple DMA controller that doesn't support it, and we'll have to
54 implement it in software, or we have a more advanced DMA controller,
[all …]
Dpxa_dma.txt1 PXA/MMP - DMA Slave controller
8 is queued even on a running DMA channel.
26 a check of the DMA channel reports a "stopped channel", the transfer should
41 channel" linked to the requestor line, and the physical DMA channel is
79 If while new_link was created the DMA channel stopped, it is _not_
89 this specific case if the DMA is already running in aligned mode.
100 DMA chain.
Ddmatest.txt1 DMA Test Guide
6 This small document introduces how to test DMA drivers using dmatest module.
11 Device Drivers -> DMA Engine support -> DMA Test client
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/
Ddma.txt1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
18 - DMA channel nodes:
21 - reg : DMA channel specific registers
22 - cell-index : DMA channel index starts at 0.
[all …]
Dmpc512x_lpbfifo.txt8 - dmas: should contain the DMA specifier for SCLPC as described at
/linux-4.4.14/Documentation/
DDMA-ISA-LPC.txt1 DMA with ISA and LPC devices
6 This document describes how to do DMA transfers using the old ISA DMA
8 uses the same DMA system so it will be around for quite some time.
13 To do ISA style DMA you need to include two headers:
18 The first is the generic DMA API used to convert virtual addresses to
19 bus addresses (see Documentation/DMA-API.txt for details).
21 The second contains the routines specific to ISA DMA transfers. Since
29 The ISA DMA controller has some very strict requirements on which
33 (You usually need a special buffer for DMA transfers instead of
36 The DMA-able address space is the lowest 16 MB of _physical_ memory.
[all …]
DDMA-API-HOWTO.txt1 Dynamic DMA mapping Guide
8 This is a guide to device driver writers on how to use the DMA API
10 DMA-API.txt.
12 CPU and DMA addresses
14 There are several kinds of addresses involved in the DMA API, and it's
29 registers at an MMIO address, or if it performs DMA to read or write system
35 From a device's point of view, DMA uses the bus address space, but it may
38 so devices only need to use 32-bit DMA addresses.
73 If the device supports DMA, the driver sets up a buffer using kmalloc() or
77 cannot because DMA doesn't go through the CPU virtual memory system.
[all …]
DIntel-IOMMU.txt12 DMAR - DMA remapping
13 DRHD - DMA Remapping Hardware Unit Definition
21 ACPI enumerates and lists the different DMA engines in the platform, and
22 device scope relationships between PCI devices and which DMA engine controls
30 reserved in the e820 map. When we turn on DMA translation, DMA to those
39 that needs to perform DMA. Once DMA is completed and mapping is no longer
49 Different DMA engines may support different number of domains.
70 When errors are reported, the DMA engine signals via an interrupt. The fault
96 PCI-DMA: Using DMAR IOMMU
101 DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
[all …]
DDMA-attributes.txt1 DMA attributes
4 This document describes the semantics of the DMA attributes that are
10 DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA. DMA
12 all pending DMA writes to complete, and thus provides a mechanism to
13 strictly order DMA from a device across all intervening busses and
17 the way from the DMA device to memory.
20 useful, suppose that a device does a DMA write to indicate that data is
21 ready and available in memory. The DMA of the "completion indication"
22 could race with data DMA. Mapping the memory used for completion
98 By default DMA-mapping subsystem is allowed to assemble the buffer
DDMA-API.txt1 Dynamic DMA mapping using the generic device
6 This document describes the DMA API. For a more gentle introduction
7 of the API (and actual examples), see Documentation/DMA-API-HOWTO.txt.
21 A dma_addr_t can hold any valid DMA address for the platform. It can be
22 given to a device to use as a DMA source or target. A CPU cannot reference
24 address space and the DMA address space.
26 Part Ia - Using large DMA-coherent buffers
45 same width as the bus and given to the device as the DMA address base of
78 Part Ib - Using small DMA-coherent buffers
83 Many drivers need lots of small DMA-coherent memory regions for DMA
[all …]
Ddebugging-via-ohci1394.txt2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
10 bus master which uses DMA to offload data transfers from the CPU and has
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
44 DMA by default, which is more secure but not suitable for remote debugging.
45 Pass the remote_dma=1 parameter to the driver to get unfiltered physical DMA.
81 disable all physical DMA on each bus reset.
108 required for physical DMA above 4 GB (but not utilized by Linux yet).
123 3) Test physical DMA using firescope:
152 (Kernel hacking: Provide code for enabling DMA over FireWire early on boot)
Dvfio.txt3 Many modern system now provide DMA and interrupt remapping facilities
38 and DMA. Without going into the details of each of these, DMA is
201 /* Allocate some space and setup a DMA mapping */
299 2) The hardware supports so called DMA windows - the PCI address range
300 within which DMA transfer is allowed, any attempt to access address space
304 to map/unmap pages for DMA, and it normally maps 1..32 pages per call and
321 of the DMA window on the PCI bus.
325 the DMA window is and adjust rlimit before doing any real job.
349 /* Allocate some space and setup a DMA mapping */
357 /* Check here is .iova/.size are within DMA window from spapr_iommu_info */
[all …]
Dvme_api.txt84 specific window or DMA channel (which may be used by a different driver) this
103 when it is used. For DMA controllers, the request function requires the
233 DMA channels
236 The VME DMA transfer provides the ability to run link-list DMA transfers. The
237 API introduces the concept of DMA lists. Each DMA list is a link-list which can
238 be passed to a DMA controller. Multiple lists can be created, extended,
245 The following functions are provided to create and destroy DMA lists. Execution
266 are not checked until an entry is added to a DMA list, the request
267 for a DMA channel purely checks the directions in which the
Dxillybus.txt61 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
102 up the DMA buffers and character devices accordingly. As a result, a single
135 * Being bandwidth efficient under load (using DMA) but also handle small
191 the kernel. Since the DMA mapping and synchronization functions, which are bus
195 which execute the DMA-related operations on the bus.
220 * bufsize: Each DMA buffer's size. Always a power of two.
249 the host is done through DMA. In particular, the Interrupt Service Routine
269 sides, the implementation relies on a set of DMA buffers which is allocated
272 FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the
281 stops momentarily before a DMA buffer is filled, the intuitive expectation is
[all …]
Dparport.txt82 command-line will make parport use any IRQ lines or DMA channels that
148 dma Parallel port's DMA channel, or -1 if none is being
162 DMA DMA is available and will be used.
238 o interrupt-driven, protocol in hardware using DMA
261 the DMA channel, and try with:
264 io=0x378 irq=7 dma=3 (for DMA)
D00-INDEX24 DMA-API.txt
25 - DMA API, pci_ API & extensions for non-consistent memory machines.
26 DMA-API-HOWTO.txt
27 - Dynamic DMA mapping Guide
28 DMA-ISA-LPC.txt
29 - How to do DMA with ISA (and LPC) devices.
30 DMA-attributes.txt
31 - listing of the various possible attributes a DMA region can have
163 - the DMA Buffer Sharing API Guide
/linux-4.4.14/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-dma.txt1 Keystone Navigator DMA Controller
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
34 into DMA and the DMA uses it as the physical addresses to reach queue
36 they are relevant only from DMA perspective. The QMSS may not choose to
[all …]
Dkeystone-navigator-qmss.txt7 Packet DMA.
47 transmit DMA queues.
85 navigator packet DMA descriptors. The memory for
95 - dma-coherent : Present if DMA operations are coherent.
/linux-4.4.14/arch/cris/
DKconfig295 bool "Enable DMA on synchronous serial port 0."
298 A synchronous serial port can run in manual or DMA mode.
299 Selecting this option will make it run in DMA mode.
308 bool "Enable DMA on synchronous serial port 1."
311 A synchronous serial port can run in manual or DMA mode.
312 Selecting this option will make it run in DMA mode.
346 prompt "Ser0 DMA out channel"
352 bool "Ser0 uses no DMA for output"
354 Do not use DMA for ser0 output.
361 If you do not enable DMA, an interrupt for each character will be
[all …]
/linux-4.4.14/drivers/dma/sh/
DKconfig2 # DMA engine configuration for sh
10 # DMA Engine Helpers
14 bool "Renesas SuperH DMA Engine support"
21 Enable support for the Renesas SuperH DMA controllers.
24 # DMA Controllers
31 Enable support for the Renesas SuperH DMA controllers.
43 tristate "Renesas R-Car Gen2 DMA Controller"
47 This driver supports the general purpose DMA controller found in the
54 Enable support for the Renesas R-Car series DMA controllers.
57 tristate "Renesas USB-DMA Controller"
[all …]
/linux-4.4.14/Documentation/usb/
Ddma.txt2 over how DMA may be used to perform I/O operations. The APIs are detailed
8 The big picture is that USB drivers can continue to ignore most DMA issues,
9 though they still must provide DMA-ready buffers (see
10 Documentation/DMA-API-HOWTO.txt). That's how they've worked through
13 OR: they can now be DMA-aware.
15 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
22 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
26 - There's a new "generic DMA API", parts of which are usable by USB device
38 IOMMU to manage the DMA mappings. It can cost MUCH more to set up and
58 not using a streaming DMA mapping, so it's good for small transfers on
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/4xx/
Dppc440spe-adma.txt1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
5 for DMA engines and Memory Queue Module node. The latter is used
9 DMA devices.
28 ii) The DMA node
33 - cell-index : 1 cell, hardware index of the DMA engine
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
/linux-4.4.14/arch/blackfin/mach-bf548/
DKconfig32 bool "DMA has priority over core for ext. accesses"
46 prompt "UART2 DMA channel selection"
50 UART2 DMA channel selection
58 bool "UART2 DMA RX -> DMA18 TX -> DMA19"
60 UART2 DMA channel assignment
63 use SPORT2 default DMA channel
66 bool "UART2 DMA RX -> DMA13 TX -> DMA14"
68 UART2 DMA channel assignment
71 use EPPI1 EPPI2 default DMA channel
75 prompt "UART3 DMA channel selection"
[all …]
/linux-4.4.14/Documentation/sound/oss/
Dultrasound11 dma DMA channel for the Sound Blaster
12 dma16 2nd DMA channel, only needed for full duplex operation
15 no_wave_dma Set to disable DMA usage for wavetable (see note)
22 DSP to use DMA for playback and downloading samples. This is the same
23 as the old behaviour. If set to 1, no DMA is needed for downloading samples,
29 just one 8 bit DMA channel. Recording will not work with one DMA
DESS18688 * The ESS1868 does not allow use of a 16-bit DMA, thus DMA 0, 1, 2, and 3
20 For configuring the sound card's I/O addresses, IRQ and DMA, here is a
27 (DMA 0 (CHANNEL 1))
40 the MPU-401 MIDI port is located at 0x0330. IRQ is IRQ 5, DMA is channel 1.
DVIBRA1611 to setup because the kernel reported a lot of DMA errors and wouldn't
35 (CONFLICT (IO FATAL)(IRQ FATAL)(DMA FATAL)(MEM FATAL)) # or WARNING
39 (DMA 0 (CHANNEL 1))
40 (DMA 1 (CHANNEL 3))
DREADME.modules76 Persistent DMA Buffers:
78 The sound modules normally allocate DMA buffers during open() and
80 DMA buffers for ISA cards on machines with more than 16MB RAM. This is
81 because ISA DMA buffers must exist below the 16MB boundary and it is quite
84 problem is to allocate the DMA buffers during module load and deallocate
90 To make the sound driver use persistent DMA buffers we need to pass the
100 the sound modules loaded and the DMA buffers allocated when they are not
DCMI833085 (CONFLICT (IO FATAL)(IRQ FATAL)(DMA FATAL)(MEM FATAL)) # or WARNING
95 (DMA 0 (CHANNEL 0))
122 (DMA 0 (CHANNEL 1))
123 (DMA 1 (CHANNEL 5))
DPAS1670 interrupt and DMA channel), because you will be asked for it.
87 Persistent DMA buffers
89 Linux can often have problems allocating DMA buffers for ISA sound
91 DMA buffers must exist below the 16MB boundary and it is quite
94 here the DMA buffers (64Kb) will be allocated at boot time and kept
97 then you can get the persistent DMA buffer functionality by passing
DREADME.OSS144 good default configuration to use. Please try to use same I/O, DMA and IRQ
159 - "Device or resource busy". Probably the IRQ (or DMA) channel
162 - "I/O error". Almost certainly (99%) it's an IRQ or DMA conflict.
288 - You get the famous "DMA timed out" messages. Usually all SB clones have
289 software selectable IRQ and DMA settings. If the (power on default) values
292 few other reasons to the DMA timeout message but using the SB mode seems
338 soft configuring their I/O, IRQ, DMA and shared memory resources.
359 work now. "Proper" means that I/O, IRQ and DMA settings are the same as in
375 support for PnP cards. There are bugs in setting DMA channels in earlier
644 configure the driver use I/O, IRQ and DMA settings
[all …]
DPSS20 mss_dma The DMA channel used by the Microsoft Sound System.
21 This can be 0, 1, or 3. DMA 0 is not available on older
DSoundblaster12 dma 8-bit DMA channel for the Sound Blaster (0,1,3)
13 dma16 16-bit DMA channel for SB16 and equivalent cards (5,6,7)
DIntroduction68 are available, for example IRQ, address, DMA.
244 uses more precious interrupts and DMA channels and sometimes
299 write down what addresses, IRQ, and DMA channels
301 can use these addresses, IRQs, and DMA channels.
307 IRQ or DMA port that another device is using?
321 or DMA conflict. Move the card to another IRQ or DMA
350 8) If the system reports insufficient DMA memory then you may want to
357 You may also set persistent DMA when building a 2.4.x kernel.
/linux-4.4.14/arch/sh/drivers/dma/
DKconfig1 menu "DMA support"
5 bool "SuperH on-chip DMA controller (DMAC) support"
20 bool "SuperH DMA API support"
23 SH_DMA_API always enabled DMA API of used SuperH.
24 If you want to use DMA ENGINE, you must not enable this.
48 Say Y if you want to use Audio/USB DMA on your SH7760 board.
54 Selecting this will enable support for the PVR2 DMA controller.
64 tristate "G2 Bus DMA support"
68 This enables support for the DMA controller for the Dreamcast's
/linux-4.4.14/Documentation/video4linux/cx2341x/
Dfw-dma.txt1 This page describes the structures and procedures used by the cx2341x DMA
7 The cx2341x PCI interface is busmaster capable. This means it has a DMA
23 Mailbox #10 is reserved for DMA transfer information.
30 This section describes, in general, the order of events when handling DMA
37 - The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
38 - The card raises the DMA Complete interrupt.
39 - The driver checks the DMA status register for any errors.
42 NOTE! It is possible that the Encoder and DMA Complete interrupts get raised
65 addresses are the physical memory location of the target DMA buffer.
86 DMA Transfer Status
[all …]
Dfw-memory.txt43 DMA Registers 0x000-0xff:
47 0x04 - DMA status:
49 0x08 - pci DMA pointer for read link list
50 0x0c - pci DMA pointer for write link list
51 0x10 - read/write DMA enable:
55 0x1c - always 0x20 or 32, smaller values slow down DMA transactions
62 if changed to 0xffffffff DMA write interrupts break.
72 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
127 27 Encoder DMA complete
130 20 Decoder DMA complete
[all …]
Dfw-decoder-api.txt106 Set DMA transfer block size. Counterpart to API 0xC9
108 DMA transfer block size in bytes. A different size may be specified
109 when issuing the DMA transfer command.
131 Status of the last DMA transfer
134 Bit 2 set means DMA error
137 DMA type: 0=MPEG, 1=OSD, 2=YUV
144 Setup DMA from host operation. Counterpart to API 0xCC
150 DMA type (0=MPEG, 1=OSD, 2=YUV)
Dfw-encoder-api.txt264 the PCI bus (DMA), and 1 when the data is streamed to another chip
476 Set DMA transfer block size
478 DMA transfer block size in bytes or frames. When unit is bytes,
488 Returns information on the previous DMA transfer in conjunction with
502 Returns information on the previous DMA transfer in conjunction with
508 2 DMA read error
509 3 DMA write error
512 DMA type
523 Setup DMA to host operation
529 DMA type (0=MPEG)
/linux-4.4.14/drivers/dma/dw/
DKconfig2 # DMA engine configuration for dw
13 tristate "Synopsys DesignWare AHB DMA platform driver"
18 Support the Synopsys DesignWare AHB DMA controller. This
22 tristate "Synopsys DesignWare AHB DMA PCI driver"
26 Support the Synopsys DesignWare AHB DMA controller on the
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Domap-spi.txt14 - dmas: List of DMA specifiers with the controller specific format
15 as described in the generic DMA client binding. A tx and rx
17 - dma-names: List of DMA request names. These strings correspond
18 1:1 with the DMA specifiers listed in dmas. The string naming
24 [hwmod populated DMA resources]
34 [generic DMA request binding]
Dmxs-spi.txt7 - dmas: DMA specifier, consisting of a phandle to DMA controller node
8 and SSP DMA channel ID.
Dsh-msiof.txt16 by both the CPU and the DMA engine.
19 DMA engine.
29 - dmas : Must contain a list of two references to DMA
32 - dma-names : Must contain a list of two DMA names, "tx" and "rx".
Dfsl-imx-cspi.txt20 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
22 - dma-names: DMA request names should include "tx" and "rx" if present.
Dspi-rockchip.txt24 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
26 - dma-names: DMA request names should include "tx" and "rx" if present.
Dspi-rspi.txt36 - dmas : Must contain a list of two references to DMA specifiers,
38 - dma-names : Must contain a list of two DMA names, "tx" and "rx".
Dspi-meson.txt6 NOR memories, without DMA support and a 64-byte unified transmit /
/linux-4.4.14/Documentation/devicetree/bindings/dma/xilinx/
Dxilinx_dma.txt1 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
9 - reg: Should contain DMA registers location and length.
12 DMA channel (see child node properties below).
21 - interrupts: Should contain per channel DMA interrupts.
49 * DMA client
52 - dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
55 - dma-names: a list of DMA channel names, one per "dmas" entry
Dxilinx_vdma.txt13 DMA channel (see child node properties below).
59 * DMA client
62 - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
65 - dma-names: a list of DMA channel names, one per "dmas" entry
/linux-4.4.14/Documentation/sound/alsa/soc/
Dplatform.txt4 An ASoC platform driver class can be divided into audio DMA drivers, SoC DAI
8 Audio DMA
11 The platform DMA driver optionally supports the following ALSA operations:-
23 The platform driver exports its DMA functionality via struct
49 Please refer to the ALSA driver documentation for details of audio DMA.
52 An example DMA driver is soc/pxa/pxa2xx-pcm.c
76 3) DMA IO to/from DSP buffers (if applicable)
/linux-4.4.14/drivers/usb/musb/
DKconfig127 comment "MUSB DMA mode"
130 bool 'Disable DMA (always use PIO)'
133 DMA controllers are ignored.
135 Do not choose this unless DMA support for your SOC or board
136 is unavailable (or unstable). When DMA is enabled at compile time,
146 Enable DMA transfers on UX500 platforms.
152 Enable DMA transfers using Mentor's engine.
158 Enable DMA transfers when TI CPPI DMA is available.
170 Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
/linux-4.4.14/Documentation/devicetree/bindings/mips/cavium/
Ddma-engine.txt1 * DMA Engine.
3 The Octeon DMA Engine transfers between the Boot Bus and main memory.
4 The DMA Engine will be referred to by phandle by any device that is
12 - reg: The base address of the DMA Engine's register bank.
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Dsirf-audio-port.txt6 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
7 - dma-names: Identifier string for each DMA request line in the dmas property.
10 One of the DMA channels will be responsible for transmission (should be
Dfsl,ssi.txt23 - fsl,playback-dma: Phandle to a node for the DMA channel to use for
26 - fsl,capture-dma: Phandle to a node for the DMA channel to use for
53 - fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to
74 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
75 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
76 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
77 playback and DMA channel 3 for capture. The developer can choose which
78 DMA controller to use, but the channels themselves are hard-wired. The
81 The device tree nodes for the DMA channels that are referenced by
85 "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
Dbrcm,bcm2835-i2s.txt8 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
9 - dma-names: Identifier string for each DMA request line in the dmas property.
12 One of the DMA channels will be responsible for transmission (should be
Dsirf-usp.txt6 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
7 - dma-names: Identifier string for each DMA request line in the dmas property.
10 One of the DMA channels will be responsible for transmission (should be
Dmxs-saif.txt7 - dmas: DMA specifier, consisting of a phandle to DMA controller node
8 and SAIF DMA channel ID.
Dingenic,jz4740-i2s.txt8 - dmas: DMA controller phandle and DMA request line for I2S Tx and Rx channels
Dsun4i-codec.txt8 - dmas: DMA channels for tx and rx dma. See the DMA client binding,
Ddavinci-mcasp-audio.txt22 - dmas: two element list of DMA controller phandles and DMA request line
24 - dma-names: identifier string for each DMA request line in the dmas property.
Dsamsung-i2s.txt23 - dmas: list of DMA controller phandle and DMA request line ordered pairs.
24 - dma-names: identifier string for each DMA request line in the dmas property.
58 - samsung,idma-addr: Internal DMA register base address of the audio
Drockchip-spdif.txt15 - dmas: DMA specifiers for tx dma. See the DMA client binding,
Drockchip-i2s.txt15 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
Dst,sti-asoc-card.txt29 - dma: CPU_DAI DMA controller phandle and DMA request line, listed in the same
32 - dma-names: identifier string for each DMA request line in the dmas property.
/linux-4.4.14/Documentation/rapidio/
Dtsi721.txt10 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
23 III. DMA Engine Support
25 Tsi721 mport driver supports DMA data transfers between local system memory and
27 mode API defined by common Linux kernel DMA Engine framework.
29 Depending on system requirements RapidIO DMA operations can be included/excluded
31 out of eight available BDMA channels to support DMA data transfers.
35 this driver will accept DMA-specific module parameter:
41 1.1.0 - DMA operations re-worked to support data scatter/gather lists larger
/linux-4.4.14/Documentation/devicetree/bindings/crypto/
Datmel-crypto.txt11 - dmas: List of two DMA specifiers as described in
13 - dma-names: Contains one identifier string for each DMA specifier
33 - dmas: List of two DMA specifiers as described in
35 - dma-names: Contains one identifier string for each DMA specifier
56 - dmas: One DMA specifiers as described in
58 - dma-names: Contains one identifier string for each DMA specifier
Domap-sham.txt15 - dmas: DMA specifiers for the rx dma. See the DMA client binding,
17 - dma-names: DMA request name. Should be "rx" if a dma is present.
Domap-aes.txt17 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
19 - dma-names: DMA request names should include "tx" and "rx" if present.
Domap-des.txt14 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
17 - dma-names: DMA request names should include "tx" and "rx" if present
Dqcom-qce.txt11 - dmas : DMA specifiers for tx and rx dma channels. For more see
13 - dma-names : DMA request names should be "rx" and "tx"
Dimg-hash.txt9 - reg : Offset and length of the register set for the module, and the DMA port
11 - dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
/linux-4.4.14/drivers/net/wireless/b43legacy/
DKconfig74 bool "DMA + PIO"
78 Include both, Direct Memory Access (DMA) and Programmed I/O (PIO)
81 default DMA is used, otherwise PIO is used.
86 bool "DMA (Direct Memory Access) only"
89 Only include Direct Memory Access (DMA).
97 This reduces the size of the driver module, by omitting the DMA code.
98 Please note that PIO transfers are slow (compared to DMA).
102 You should use PIO only if DMA does not work for you.
/linux-4.4.14/Documentation/devicetree/bindings/serial/
Datmel-usart.txt15 - atmel,use-dma-rx: use of PDC or DMA for receiving data
16 - atmel,use-dma-tx: use of PDC or DMA for transmitting data
21 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
22 memory peripheral interface and USART DMA channel ID, FIFO configuration.
50 - use DMA:
Dfsl-mxs-auart.txt8 - dmas: DMA specifier, consisting of a phandle to DMA controller node
9 and AUART DMA channel ID.
16 it also means you enable the DMA support for this UART.
Domap_serial.txt19 - dmas : DMA specifier, consisting of a phandle to the DMA controller
20 node and a DMA channel number.
Dqcom,msm-uartdm.txt30 used with TX DMA channel. Required when using DMA for transmission
33 used with RX DMA channel. Required when using DMA for reception
Dnxp,lpc1850-uart.txt11 - dmas : Two or more DMA channel specifiers following the
/linux-4.4.14/Documentation/spi/
Dpxa2xx8 - SSP PIO and SSP DMA data transfers.
32 The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should
33 be used. This caused the driver to acquire two DMA channels: rx_channel and
34 tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
35 See the "PXA2xx Developer Manual" section "DMA Controller".
56 .enable_dma = 1, /* Enables NSSP DMA */
109 The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
111 the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
205 DMA and PIO I/O Support
207 The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/mmc/
Ddavinci_mmc.txt16 - dmas: List of DMA specifiers with the controller specific format
17 as described in the generic DMA client binding. A tx and rx
19 - dma-names: RX and TX DMA request names. These strings correspond
20 1:1 with the DMA specifiers listed in dmas.
Dti-omap-hsmmc.txt25 dmas: List of DMA specifiers with the controller specific format
26 as described in the generic DMA client binding. A tx and rx
28 dma-names: List of DMA request names. These strings correspond
29 1:1 with the DMA specifiers listed in dmas. The string naming is
30 to be "rx" and "tx" for RX and TX DMA requests, respectively.
34 [hwmod populated DMA resources]
46 [generic DMA request binding]
Dmxs-mmc.txt13 - dmas: DMA specifier, consisting of a phandle to DMA controller node
14 and SSP DMA channel ID.
Drenesas,mmcif.txt18 - dmas: reference to the DMA channels, one per channel name listed in the
20 - dma-names: must contain "tx" for the transmit DMA channel and "rx" for the
21 receive DMA channel.
Dfsl-imx-mmc.txt9 - dmas: One DMA phandle with arguments as defined by the devicetree bindings
10 of the used DMA controller.
Dsynopsys-dw-mshc.txt78 * dmas: List of DMA specifiers with the controller specific format as described
79 in the generic DMA client binding. Refer to dma.txt for details.
81 * dma-names: request names for generic DMA client binding. Must be "rx-tx".
104 [board specific internal DMA resources]
119 [board specific generic DMA request binding]
Dmoxa,moxart-mmc.txt16 - dmas : Should contain two DMA channels, line request number must be 5 for
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt45 22 xor0 XOR DMA 0
46 23 xor1 XOR DMA 0
113 22 xor0 XOR DMA 0
116 28 xor1 XOR DMA 1
137 22 pdma Peripheral DMA
138 23 xor0 XOR DMA 0
139 24 xor1 XOR DMA 1
153 8 xor0 XOR DMA 0
157 16 xor1 XOR DMA 1
/linux-4.4.14/drivers/iommu/
DKconfig12 remap DMA requests and/or remap interrupts from other devices on the
51 # IOMMU-agnostic DMA-mapping layer
100 remapping of DMA memory accesses from devices. With an AMD IOMMU you
101 can isolate the DMA memory of different devices and protect the
132 bool "Support for Intel IOMMU using DMA Remapping Devices"
138 DMA remapping (DMAR) devices support enables independent address
139 translations for Direct Memory Access (DMA) from devices.
140 These DMA remapping devices are reported via ACPI tables
141 and include PCI device scope covered by these DMA
151 to access DMA resources through process address space by
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/i2c/
Di2c-mxs.txt9 - dmas: DMA specifier, consisting of a phandle to DMA controller node
10 and I2C DMA channel ID.
Di2c-sh_mobile.txt23 - dmas : Must contain a list of two references to DMA
26 - dma-names : Must contain a list of two DMA names, "tx" and "rx".
/linux-4.4.14/Documentation/devicetree/bindings/misc/
Datmel-ssc.txt15 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
16 the memory interface and SSC DMA channel ID (for tx and rx).
38 - DMA transfer:
/linux-4.4.14/Documentation/PCI/
Dpci.txt47 Set the DMA mask size (for both coherent and streaming DMA)
52 Enable DMA/processing engines
58 Stop all DMA activity
59 Release DMA buffers (both streaming and coherent)
117 Intended to stop any idling DMA operations.
243 Set the DMA mask size (for both coherent and streaming DMA)
248 Enable DMA/processing engines.
277 pci_set_master() will enable DMA by setting the bus master bit
280 disable DMA by clearing the bus master bit.
320 3.3 Set the DMA mask size
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/net/
Damd-xgbe.txt16 interrupt for each DMA channel supported by the device should be specified.
19 - DMA clock for the amd-xgbe device (used for calculating the
20 correct Rx interrupt watchdog timer value on a DMA channel
24 - "dma_clk" for the DMA clock
33 a unique interrupt for each DMA channel - this requires an additional
34 interrupt be configured for each DMA channel
Dsamsung-sxgbe.txt10 trasmit DMA interrupts, receive DMA interrupts and lpi interrupt.
20 This is an integer and represents allowable DMA bursts when fixed burst.
Dsnps,dwc-qos-ethernet.txt26 - snps,txpbl: DMA Programmable burst length for the TX DMA
27 - snps,rxpbl: DMA Programmable burst length for the RX DMA
Dstmmac.txt21 - snps,fixed-burst Program the DMA to use the fixed burst mode
22 - snps,mixed-burst Program the DMA to use the mixed burst mode
23 - snps,force_thresh_dma_mode Force DMA to use the threshold mode for
25 - snps,force_sf_dma_mode Force DMA to use the Store and Forward
Dlpc-eth.txt11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
/linux-4.4.14/Documentation/devicetree/bindings/iommu/
Diommu.txt13 Example: 32-bit DMA to 64-bit physical addresses
18 * Provide system protection against "rogue" DMA by forcing all accesses to go
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
59 the DMA window for the given device. The length of the DMA window is given
162 Multiple-master IOMMU with configurable DMA window:
169 * address of the DMA window. The length of the DMA
172 * The DMA window is the range addressable by the
179 /* master ID 42, 4 GiB DMA window starting at 0 */
/linux-4.4.14/Documentation/devicetree/bindings/mtd/
Dflctl-nand.txt10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
14 The DMA fields are not used yet in the driver but are listed here for
Dgpmi-nand.txt12 - dmas: DMA specifier, consisting of a phandle to DMA controller node
13 and GPMI DMA channel ID.
Dbrcm,brcmnand.txt6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
31 (optional) Flash DMA register range (if present)
36 - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
Ddenali-nand.txt8 - dm-mask : DMA bit mask
/linux-4.4.14/Documentation/networking/
Dltpc.txt12 line, and DMA channel of the card, this does not always work. For
22 where the parameters (in order) are the port address, IRQ, and DMA
81 DMA -- choose DMA 1 or 3, and set both corresponding switches.
83 SW4 DMA 3
84 SW5 DMA 1
85 SW6 DMA 3
86 SW7 DMA 1
Dstmmac.txt31 dma_rxsize: DMA rx ring size;
32 dma_txsize: DMA tx ring size;
33 buf_sz: DMA buffer size;
49 the descriptors in the ring and informs the DMA engine that there is a packet
64 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
68 The driver is able to mitigate the number of its DMA interrupts
77 4.5) DMA descriptors
81 STMMAC supports DMA descriptor to operate both in dual buffer (RING)
151 o dma_cfg: internal DMA parameters
153 be transferred in one DMA transaction.
[all …]
Daltera_tse.txt6 using the SGDMA and MSGDMA soft DMA IP components. The driver uses the
26 probe function then installs the appropriate set of DMA routines to
33 developer wishes to support their own soft DMA logic and driver support. Any
40 Scatter-gather DMA is not supported by the SGDMA or MSGDMA at this time.
41 Scatter-gather DMA will be added to a future maintenance update to this
67 transmit descriptor by calling the underlying DMA transmit routine (SGDMA or
69 interrupt is driven by the transmit DMA logic. The driver handles the transmit
74 The driver will post receive buffers to the receive DMA logic during driver
76 underlying DMA logic (MSGDMA is able queue receive buffers, SGDMA is not able
78 received, the DMA logic generates an interrupt. The driver handles a receive
[all …]
Dcs89x0.txt38 4.3 Compiling the driver to support Rx DMA
222 * use_dma=1 - Enable DMA
224 Rx DMA only)
225 * dmasize=# (16 or 64) - DMA size 16K or 64K. Default value is set to 16.
269 * DMA Burst = enabled
298 i) Cirrus recommend that the cs89x0 use the ISA DMA channels 5, 6 or
299 7. You will probably find that other DMA channels will not work.
301 j) The cs89x0 supports DMA for receiving only. DMA mode is
303 with large ping packets consumes 82% of its CPU capacity in non-DMA
304 mode. With DMA this is reduced to 45%.
[all …]
/linux-4.4.14/Documentation/mmc/
Dmmc-async-req.txt6 pre-fetch makes the cache overhead relatively significant. If the DMA
8 transfer, the DMA preparation overhead would not affect the MMC performance.
25 platform. In power save mode, when clocks run on a lower frequency, the DMA
50 In the DMA case pre_req() may do dma_map_sg() and prepare the DMA
71 * Begin to prepare DMA while cmd is being processed by MMC.
/linux-4.4.14/Documentation/sound/alsa/
Dtimestamping.txt62 The DMA time is measured using counters - typically the least reliable
63 of all measurements due to the bursty natured of DMA transfers.
80 timestamp will report the DMA time based on the hw_pointer value.
85 streams and to the DMA time (hw_ptr) in all other cases.
143 1. DMA timestamp, no compensation for DMA+analog delay
152 2. DMA timestamp, compensation for DMA+analog delay
160 3. link timestamp, compensation for DMA+analog delay
169 Example 1 shows that the timestamp at the DMA level is close to 1ms
172 DMA-link delay in example 2 helps remove the hardware buffering abut
183 Example 3: DMA timestamp, no compensation for delay, delta of ~5ms
[all …]
DALSA-Configuration.txt170 dma1 - DMA # for AD1848 chip (0,1,3)
312 dma1 - DMA # for WSS playback (0,1,3)
313 dma2 - DMA # for WSS capture (0,1), -1 = disabled (default)
334 Whatever IRQ and DMA channels you pick, be sure to reserve them for
346 dma1 - DMA # for WSS playback (0,1,3)
347 dma2 - DMA # for WSS capture (0,1), -1 = disabled (default)
368 Whatever IRQ and DMA channels you pick, be sure to reserve them for
428 wssdma - first DMA # for CMI8330 chip (WSS)
431 sbdma8 - 8bit DMA # for CMI8330 chip (SB16)
432 sbdma16 - 16bit DMA # for CMI8330 chip (SB16)
[all …]
/linux-4.4.14/sound/soc/au1x/
DKconfig9 Controllers in AC97 and I2S mode, and the Descriptor-Based DMA
22 ## Au1000/1500/1100 DMA + AC97C/I2SC
29 old DMA controller as found on the Au1000/Au1500/Au1100 chips.
/linux-4.4.14/Documentation/arm/
DNetwinder41 0xe800 - 0xe80f ide0/ide1 BM DMA
66 DMA usage
69 DMA type Description
/linux-4.4.14/Documentation/scsi/
Ddtc3x80.txt12 The DTC3x80 does not support DMA but it does have Pseudo-DMA which is
17 internal DMA, between SCSI bus and an on-chip 128-byte buffer. Double
32 the driver polls for data-ready in the pseudo-DMA transfer routine.
Dg_NCR5380.txt21 The NCR53c400 does not support DMA but it does have Pseudo-DMA which is
49 ncr_dma=xx the DMA
58 (255 should be specified for no or DMA interrupt, 254 to autoprobe for an
/linux-4.4.14/arch/blackfin/kernel/
Ddebug-mmrs.c236 #define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "") macro
848 DMA(0); in bfin_debug_mmrs_init()
849 DMA(1); in bfin_debug_mmrs_init()
850 DMA(1); in bfin_debug_mmrs_init()
851 DMA(2); in bfin_debug_mmrs_init()
852 DMA(3); in bfin_debug_mmrs_init()
853 DMA(4); in bfin_debug_mmrs_init()
854 DMA(5); in bfin_debug_mmrs_init()
855 DMA(6); in bfin_debug_mmrs_init()
856 DMA(7); in bfin_debug_mmrs_init()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/display/tilcdc/
Dpanel.txt8 - dma-burst-sz: DMA burst size
10 - fdd: FIFO DMA Request Delay
14 - fifo-th: DMA FIFO threshold
/linux-4.4.14/drivers/media/pci/cx25821/
DKconfig14 tristate "Conexant 25821 DMA audio support"
18 This is a video4linux driver for direct (DMA) audio on
/linux-4.4.14/drivers/dma/bestcomm/
DKconfig6 tristate "Bestcomm DMA engine support"
16 If you want to use drivers that require DMA operations,
/linux-4.4.14/drivers/soc/ti/
DKconfig22 tristate "TI Keystone Navigator Packet DMA support"
25 Say y tp enable support for the Keystone Navigator Packet DMA on
/linux-4.4.14/Documentation/mic/
Dmic_overview.txt38 the host to initiate DMA's to/from the card using the MIC DMA engine and
58 | MIC DMA | | +------+ | +------+ +------+ | | MIC DMA |
Dscif_overview.txt19 7. Remote DMA (RDMA) for high bandwidth DMA transfers
28 DMA, CPU copies or remote memory mapping via mmap. SCIF supports both user and
32 DMA bandwidth comparison between the TCP (over ethernet over PCIe) stack versus
/linux-4.4.14/sound/oss/
DCHANGELOG68 DMA channel. The extra audio/dsp device (the "Not functional" one) used
77 - Got SB16 to work without the 16 bit DMA channel (only the 8 bit one
109 - Changed boot time passing of 16 bit DMA channel number to SB driver.
127 idea to stop inbound DMA transfers before freeing the memory
147 SB DMA of MAD16 so that it doesn't conflict with codec's DMA channels.
148 The side effect is that all 8 bit DMA channels (0,1,3) are populated in
221 - Added allocation of I/O ports, DMA channels and interrupts
242 - Fix to DMA initialization of PSS cards.
249 to use two DMA channels with GUS MAX (16 bit ones recommended).
277 - The I/O, IRQ and DMA settings are jumper selectable or
[all …]
/linux-4.4.14/arch/powerpc/platforms/pasemi/
DKconfig24 bool "Force DMA engine to use IOMMU"
28 DMA engine. Otherwise the kernel will use it only when
/linux-4.4.14/drivers/crypto/ux500/
DKconfig23 Depends on UX500/STM DMA if running in DMA mode.
/linux-4.4.14/drivers/media/pci/cx18/
DKconfig27 tristate "Conexant 23418 DMA audio support"
31 This is a video4linux driver for direct (DMA) audio on
/linux-4.4.14/drivers/rapidio/
DKconfig26 bool "DMA Engine support for RapidIO"
31 Say Y here if you want to use DMA Engine frameork for RapidIO data
34 memory and memory on remote target device. You need a DMA controller
/linux-4.4.14/arch/cris/arch-v32/drivers/
DKconfig48 Normally you want this on. You can control what DMA channels to use
49 if you do not need DMA to something else.
83 bool "Enable DMA on synchronous serial port 0."
86 A synchronous serial port can run in manual or DMA mode.
87 Selecting this option will make it run in DMA mode.
96 bool "Enable DMA on synchronous serial port 1."
99 A synchronous serial port can run in manual or DMA mode.
100 Selecting this option will make it run in DMA mode.
/linux-4.4.14/arch/mn10300/kernel/
Dmn10300-serial-low.S3 # Virtual DMA driver for MN10300 serial ports
36 # serial port interrupt virtual DMA entry point
59 # serial port receive interrupt virtual DMA entry point
106 # serial port transmit interrupt virtual DMA entry point
/linux-4.4.14/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,video.txt17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
19 requires a DMA channel with the identifier string set to "port" followed by
/linux-4.4.14/drivers/staging/sm750fb/
Dddk750_power.c132 gate = FIELD_SET(gate, CURRENT_GATE, DMA, ON); in enableDMA()
134 gate = FIELD_SET(gate, CURRENT_GATE, DMA, OFF); in enableDMA()
/linux-4.4.14/arch/arm/boot/dts/
Dsama5d3xmb.dtsi28 dmas = <0>, <0>; /* Do not use DMA for spi0 */
79 dmas = <0>, <0>; /* Do not use DMA for usart1 */
172 dmas = <0>, <0>; /* Do not use DMA for dbgu */
/linux-4.4.14/drivers/ide/
DKconfig354 IDE controllers. This allows the kernel to change PIO, DMA and UDMA
362 This driver ensures (U)DMA support for ALI 1533, 1543 and 1543C
379 change PIO, DMA and UDMA speeds and to configure the chip to
388 This allows the kernel to change PIO, DMA and UDMA speeds
422 Include support for PIO tuning and virtual DMA on the Cyrix MediaGX
462 HPT366 is an Ultra DMA chipset for ATA-66.
463 HPT368 is an Ultra DMA chipset for ATA-66 RAID Based.
464 HPT370 is an Ultra DMA chipset for ATA-100.
465 HPT372 is an Ultra DMA chipset for ATA-100.
466 HPT374 is an Ultra DMA chipset for ATA-100.
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/linux-4.4.14/Documentation/devicetree/bindings/arm/
Dprimecell.txt19 - dmas : From common DMA binding. If present, refers to one or more dma channels.
20 - dma-names : From common DMA binding, needs to match the 'dmas' property.
/linux-4.4.14/Documentation/x86/x86_64/
Dboot-options.txt187 Currently four x86-64 PCI-DMA mapping implementations exist:
191 Kernel boot message: "PCI-DMA: Disabling IOMMU"
194 Kernel boot message: "PCI-DMA: using GART IOMMU"
199 Kernel boot message: "PCI-DMA: Using software bounce buffering
203 pSeries and xSeries servers. This hardware IOMMU supports DMA address
205 Kernel boot message: "PCI-DMA: Using Calgary IOMMU"
238 allowdac Allow double-address cycle (DAC) mode, i.e. DMA >4GB.
240 two cycles. When off all DMA over >4GB is forced through
242 nodac Forbid DAC mode, i.e. DMA >4GB.
/linux-4.4.14/Documentation/cris/
DREADME31 range of built-in interfaces, all with modern scatter/gather DMA.
111 ttyS0 at 0xb0000060 is a builtin UART with DMA
112 ttyS1 at 0xb0000068 is a builtin UART with DMA
113 ttyS2 at 0xb0000070 is a builtin UART with DMA
114 ttyS3 at 0xb0000078 is a builtin UART with DMA
/linux-4.4.14/Documentation/blockdev/
Dfloppy.txt91 DMA channel for the floppy driver. This option is also useful
92 if you frequently get "Unable to allocate DMA memory" messages.
103 falls back on non DMA mode if no DMA-able memory can be found.
107 Tells the floppy driver that a workable DMA channel is available.
119 Sets the FIFO threshold. This is mostly relevant in DMA
199 Sets the floppy DMA channel to <nr> instead of 2.
/linux-4.4.14/Documentation/devicetree/bindings/media/
Ds5p-mfc.txt25 for DMA contiguous memory allocation and its size.
28 for DMA contiguous memory allocation and its size.
/linux-4.4.14/Documentation/devicetree/bindings/usb/
Dam33xx-usb.txt9 node and its PHY node is optional. The DMA node is also optional.
54 DMA
58 CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager
Dudc-xilinx.txt9 - xlnx,has-builtin-dma : if DMA is included
Dlpc32xx-udc.txt10 * USB Device DMA Interrupt
/linux-4.4.14/drivers/dma/hsu/
DKconfig1 # DMA engine configuration for hsu
/linux-4.4.14/drivers/soc/sunxi/
DKconfig10 whether to the CPU/DMA, or to the devices.
/linux-4.4.14/sound/oss/dmasound/
DKconfig2 tristate "Atari DMA sound support"
16 tristate "Amiga DMA sound support"
/linux-4.4.14/Documentation/arm/Samsung-S3C24XX/
DS3C2412.txt25 DMA
28 No current support for DMA.
/linux-4.4.14/drivers/video/fbdev/omap/
DKconfig52 bool "Set DMA SDRAM access priority high"
56 (SDRAM) this will speed up graphics DMA operations.
/linux-4.4.14/drivers/media/pci/saa7134/
DKconfig18 tristate "Philips SAA7134 DMA audio support"
22 This is a video4linux driver for direct (DMA) audio in
/linux-4.4.14/drivers/staging/netlogic/
DTODO2 * All memory allocation should be changed to DMA allocations
/linux-4.4.14/drivers/staging/goldfish/
DREADME4 - Fix the wrong user page DMA (moving to ALSA may fix that too)
/linux-4.4.14/Documentation/driver-model/
Ddevres.txt56 drivers using devres. For example, coherent DMA memory is acquired
59 for the DMA memory allocated using it is managed and will be
84 /* alloc DMA memory as usual */
240 DMA
337 SLAVE DMA ENGINE
/linux-4.4.14/Documentation/ABI/removed/
Dnet_dma6 that will be offloaded to a DMA copy engine. Removed due to
/linux-4.4.14/drivers/media/platform/exynos4-is/
DKconfig73 bool "EXYNOS4x12 FIMC-IS ISP Direct DMA capture support"
79 video capture interface for the FIMC-IS ISP raw (Bayer) capture DMA.
/linux-4.4.14/drivers/parport/
DKconfig65 bool "Use FIFO/DMA if available"
71 As well as actually having a FIFO, or DMA capability, the kernel
75 specify which IRQ/DMA to use.
82 find out things like base addresses, IRQ lines and DMA channels. It
/linux-4.4.14/Documentation/devicetree/bindings/pci/
Darm,juno-r1-pcie.txt10 in a manner that makes the DMA operations to appear coherent to the CPUs.
/linux-4.4.14/Documentation/devicetree/bindings/xillybus/
Dxillybus.txt11 - dma-coherent: Present if DMA operations are coherent
/linux-4.4.14/drivers/media/pci/cx88/
DKconfig17 tristate "Conexant 2388x DMA audio support"
21 This is a video4linux driver for direct (DMA) audio on
/linux-4.4.14/Documentation/features/io/dma-contiguous/
Darch-support.txt4 # description: arch supports the DMA CMA (continuous memory allocator)
/linux-4.4.14/Documentation/features/io/dma-api-debug/
Darch-support.txt4 # description: arch supports DMA debug facilities
/linux-4.4.14/drivers/gpu/host1x/
DKconfig7 The Tegra host1x module is the DMA engine for register access to
/linux-4.4.14/Documentation/devicetree/bindings/ata/
Dahci-fsl-qoriq.txt11 - dma-coherent: Enable AHCI coherent DMA operation.
/linux-4.4.14/drivers/net/ethernet/ezchip/
DKconfig24 Device does not have DMA ability.
/linux-4.4.14/sound/soc/ux500/
DKconfig17 tristate "Platform - DB8500 (DMA)"
/linux-4.4.14/arch/tile/gxio/
DKconfig7 # Support direct access to the common I/O DMA facility within the

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