Lines Matching refs:DMA

61 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
102 up the DMA buffers and character devices accordingly. As a result, a single
135 * Being bandwidth efficient under load (using DMA) but also handle small
191 the kernel. Since the DMA mapping and synchronization functions, which are bus
195 which execute the DMA-related operations on the bus.
220 * bufsize: Each DMA buffer's size. Always a power of two.
249 the host is done through DMA. In particular, the Interrupt Service Routine
269 sides, the implementation relies on a set of DMA buffers which is allocated
272 FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the
281 stops momentarily before a DMA buffer is filled, the intuitive expectation is
290 the FPGA to submit a DMA buffer as soon as it can. This timeout mechanism
295 partial DMA buffers is somewhat different, though. The user can tell the
305 to lay around in the DMA buffers between read() and write() anyhow.
349 pages from the kernel, and diving them into DMA buffers as necessary. Since
371 catch regarding the FPGA to host direction: The FPGA may have filled a DMA