1* ARM PrimeCells PL080 and PL081 and derivatives DMA controller 2 3Required properties: 4- compatible: "arm,pl080", "arm,primecell"; 5 "arm,pl081", "arm,primecell"; 6- reg: Address range of the PL08x registers 7- interrupt: The PL08x interrupt number 8- clocks: The clock running the IP core clock 9- clock-names: Must contain "apb_pclk" 10- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs 11- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs 12- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents 13- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents 14- #dma-cells: must be <2>. First cell should contain the DMA request, 15 second cell should contain either 1 or 2 depending on 16 which AHB master that is used. 17 18Optional properties: 19- dma-channels: contains the total number of DMA channels supported by the DMAC 20- dma-requests: contains the total number of DMA requests supported by the DMAC 21- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32 22 64, 128 or 256 bytes are legal values 23- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal 24 values 25 26Clients 27Required properties: 28- dmas: List of DMA controller phandle, request channel and AHB master id 29- dma-names: Names of the aforementioned requested channels 30 31Example: 32 33dmac0: dma-controller@10130000 { 34 compatible = "arm,pl080", "arm,primecell"; 35 reg = <0x10130000 0x1000>; 36 interrupt-parent = <&vica>; 37 interrupts = <15>; 38 clocks = <&hclkdma0>; 39 clock-names = "apb_pclk"; 40 lli-bus-interface-ahb1; 41 lli-bus-interface-ahb2; 42 mem-bus-interface-ahb2; 43 memcpy-burst-size = <256>; 44 memcpy-bus-width = <32>; 45 #dma-cells = <2>; 46}; 47 48device@40008000 { 49 ... 50 dmas = <&dmac0 0 2 51 &dmac0 1 2>; 52 dma-names = "tx", "rx"; 53 ... 54}; 55