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Searched refs:CRm (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/arch/arm64/kvm/
Dsys_regs.c444 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
447 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
450 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
453 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
477 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
480 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
483 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
489 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
492 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
510 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
[all …]
Dsys_regs.h29 u8 CRm; member
42 u8 CRm; member
70 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_instr()
134 if (i1->CRm != i2->CRm) in cmp_sys_reg()
135 return i1->CRm - i2->CRm; in cmp_sys_reg()
143 #define CRm(_x) .CRm = _x macro
Dsys_regs_generic_v8.c58 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
64 { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
/linux-4.4.14/arch/arm/kvm/
Dcoproc.c271 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
275 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
279 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
283 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
288 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
290 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
292 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
298 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
302 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
304 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
[all …]
Dcoproc.h24 unsigned long CRm; member
36 unsigned long CRm; member
66 p->CRn, p->CRm, p->Op1, p->Op2, in print_cp_instr()
138 if (i1->CRm != i2->CRm) in cmp_reg()
139 return i1->CRm - i2->CRm; in cmp_reg()
149 #define CRm(_x) .CRm = _x macro
150 #define CRm64(_x) .CRn = _x, .CRm = 0
Dtrace.h139 unsigned long CRm, unsigned long Op2, bool is_write),
140 TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
146 __field( unsigned int, CRm )
156 __entry->CRm = CRm;
163 __entry->CRm, __entry->Op2)
Dcoproc_a15.c36 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
Dcoproc_a7.c39 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
/linux-4.4.14/arch/arm/include/asm/
Darch_gicv3.h26 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) p15, Op1, %0, CRn, CRm, Op2 argument
27 #define __ACCESS_CP15_64(Op1, CRm) p15, Op1, %Q0, %R0, CRm argument