Searched refs:base_addr (Results 1 - 200 of 374) sorted by relevance

12

/linux-4.4.14/arch/arm/mach-gemini/
H A Dirq.c25 #define IRQ_SOURCE(base_addr) (base_addr + 0x00)
26 #define IRQ_MASK(base_addr) (base_addr + 0x04)
27 #define IRQ_CLEAR(base_addr) (base_addr + 0x08)
28 #define IRQ_TMODE(base_addr) (base_addr + 0x0C)
29 #define IRQ_TLEVEL(base_addr) (base_addr + 0x10)
30 #define IRQ_STATUS(base_addr) (base_addr + 0x14)
31 #define FIQ_SOURCE(base_addr) (base_addr + 0x20)
32 #define FIQ_MASK(base_addr) (base_addr + 0x24)
33 #define FIQ_CLEAR(base_addr) (base_addr + 0x28)
34 #define FIQ_TMODE(base_addr) (base_addr + 0x2C)
35 #define FIQ_LEVEL(base_addr) (base_addr + 0x30)
36 #define FIQ_STATUS(base_addr) (base_addr + 0x34)
/linux-4.4.14/arch/mips/mti-sead3/
H A Dsead3-console.c15 #define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4))
19 static inline unsigned int serial_in(int offset, unsigned int base_addr) serial_in() argument
21 return __raw_readl(PORT(base_addr, offset)) & 0xff; serial_in()
24 static inline void serial_out(int offset, int value, unsigned int base_addr) serial_out() argument
26 __raw_writel(value, PORT(base_addr, offset)); serial_out()
36 unsigned int base_addr; prom_putchar() local
38 base_addr = console_port ? SEAD_UART1_REGS_BASE : SEAD_UART0_REGS_BASE; prom_putchar()
40 while ((serial_in(UART_LSR, base_addr) & UART_LSR_THRE) == 0) prom_putchar()
43 serial_out(UART_TX, c, base_addr); prom_putchar()
/linux-4.4.14/drivers/staging/media/davinci_vpfe/
H A Ddm365_ipipe_hw.c27 static void ipipe_clock_enable(void __iomem *base_addr) ipipe_clock_enable() argument
30 regw_ip(base_addr, IPIPE_GCK_MMR_DEFAULT, IPIPE_GCK_MMR); ipipe_clock_enable()
33 regw_ip(base_addr, IPIPE_GCK_PIX_DEFAULT, IPIPE_GCK_PIX); ipipe_clock_enable()
254 void __iomem *ipipe_base = ipipe->base_addr; config_ipipe_hw()
305 void __iomem *ipipe_base = vpfe_dev->vpfe_ipipe.base_addr; config_rsz_hw()
306 void __iomem *rsz_base = vpfe_dev->vpfe_resizer.base_addr; config_rsz_hw()
414 ipipe_set_lutdpc_regs(void __iomem *base_addr, void __iomem *isp5_base_addr, ipipe_set_lutdpc_regs() argument
422 ipipe_clock_enable(base_addr); ipipe_set_lutdpc_regs()
423 regw_ip(base_addr, dpc->en, DPC_LUT_EN); ipipe_set_lutdpc_regs()
429 regw_ip(base_addr, val, DPC_LUT_SEL); ipipe_set_lutdpc_regs()
430 regw_ip(base_addr, LUT_DPC_START_ADDR, DPC_LUT_ADR); ipipe_set_lutdpc_regs()
431 regw_ip(base_addr, dpc->dpc_size, DPC_LUT_SIZ & LUT_DPC_SIZE_MASK); ipipe_set_lutdpc_regs()
449 set_dpc_thresholds(void __iomem *base_addr, set_dpc_thresholds() argument
452 regw_ip(base_addr, dpc_thr->corr_thr.r & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
454 regw_ip(base_addr, dpc_thr->corr_thr.gr & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
456 regw_ip(base_addr, dpc_thr->corr_thr.gb & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
458 regw_ip(base_addr, dpc_thr->corr_thr.b & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
460 regw_ip(base_addr, dpc_thr->det_thr.r & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
462 regw_ip(base_addr, dpc_thr->det_thr.gr & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
464 regw_ip(base_addr, dpc_thr->det_thr.gb & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
466 regw_ip(base_addr, dpc_thr->det_thr.b & OTFDPC_DPC2_THR_MASK, set_dpc_thresholds()
470 void ipipe_set_otfdpc_regs(void __iomem *base_addr, ipipe_set_otfdpc_regs() argument
477 ipipe_clock_enable(base_addr); ipipe_set_otfdpc_regs()
479 regw_ip(base_addr, (otfdpc->en & 1), DPC_OTF_EN); ipipe_set_otfdpc_regs()
485 regw_ip(base_addr, val, DPC_OTF_TYP); ipipe_set_otfdpc_regs()
494 set_dpc_thresholds(base_addr, dpc_2_0); ipipe_set_otfdpc_regs()
499 set_dpc_thresholds(base_addr, dpc_2_0); ipipe_set_otfdpc_regs()
502 regw_ip(base_addr, dpc_3_0->act_adj_shf & ipipe_set_otfdpc_regs()
505 regw_ip(base_addr, ((dpc_3_0->det_thr & OTF_DPC3_0_THR_MASK) << ipipe_set_otfdpc_regs()
507 regw_ip(base_addr, dpc_3_0->det_slp & ipipe_set_otfdpc_regs()
509 regw_ip(base_addr, dpc_3_0->det_thr_min & ipipe_set_otfdpc_regs()
511 regw_ip(base_addr, dpc_3_0->det_thr_max & ipipe_set_otfdpc_regs()
514 regw_ip(base_addr, ((dpc_3_0->corr_thr & OTF_DPC3_0_THR_MASK) << ipipe_set_otfdpc_regs()
516 regw_ip(base_addr, dpc_3_0->corr_slp & ipipe_set_otfdpc_regs()
518 regw_ip(base_addr, dpc_3_0->corr_thr_min & ipipe_set_otfdpc_regs()
520 regw_ip(base_addr, dpc_3_0->corr_thr_max & ipipe_set_otfdpc_regs()
526 ipipe_set_d2f_regs(void __iomem *base_addr, unsigned int id, ipipe_set_d2f_regs() argument
537 ipipe_clock_enable(base_addr); ipipe_set_d2f_regs()
538 regw_ip(base_addr, noise_filter->en & 1, offset + D2F_EN); ipipe_set_d2f_regs()
550 regw_ip(base_addr, val, offset + D2F_TYP); ipipe_set_d2f_regs()
553 regw_ip(base_addr, noise_filter->edge_det_min_thr & ipipe_set_d2f_regs()
557 regw_ip(base_addr, noise_filter->edge_det_max_thr & ipipe_set_d2f_regs()
561 regw_ip(base_addr, ipipe_set_d2f_regs()
566 regw_ip(base_addr, noise_filter->thr[count] & D2F_THR_VAL_MASK, ipipe_set_d2f_regs()
574 void ipipe_set_gic_regs(void __iomem *base_addr, struct vpfe_ipipe_gic *gic) ipipe_set_gic_regs() argument
578 ipipe_clock_enable(base_addr); ipipe_set_gic_regs()
579 regw_ip(base_addr, gic->en & 1, GIC_EN); ipipe_set_gic_regs()
588 regw_ip(base_addr, val, GIC_TYP); ipipe_set_gic_regs()
590 regw_ip(base_addr, gic->gain & GIC_GAIN_MASK, GIC_GAN); ipipe_set_gic_regs()
594 regw_ip(base_addr, GIC_THR_MASK, GIC_THR); ipipe_set_gic_regs()
599 regw_ip(base_addr, gic->thr & GIC_THR_MASK, GIC_THR); ipipe_set_gic_regs()
600 regw_ip(base_addr, gic->slope & GIC_SLOPE_MASK, GIC_SLP); ipipe_set_gic_regs()
605 regw_ip(base_addr, val, GIC_NFGAN); ipipe_set_gic_regs()
612 void ipipe_set_wb_regs(void __iomem *base_addr, struct vpfe_ipipe_wb *wb) ipipe_set_wb_regs() argument
616 ipipe_clock_enable(base_addr); ipipe_set_wb_regs()
618 regw_ip(base_addr, wb->ofst_r & WB_OFFSET_MASK, WB2_OFT_R); ipipe_set_wb_regs()
619 regw_ip(base_addr, wb->ofst_gr & WB_OFFSET_MASK, WB2_OFT_GR); ipipe_set_wb_regs()
620 regw_ip(base_addr, wb->ofst_gb & WB_OFFSET_MASK, WB2_OFT_GB); ipipe_set_wb_regs()
621 regw_ip(base_addr, wb->ofst_b & WB_OFFSET_MASK, WB2_OFT_B); ipipe_set_wb_regs()
625 regw_ip(base_addr, val, WB2_WGN_R); ipipe_set_wb_regs()
628 regw_ip(base_addr, val, WB2_WGN_GR); ipipe_set_wb_regs()
631 regw_ip(base_addr, val, WB2_WGN_GB); ipipe_set_wb_regs()
634 regw_ip(base_addr, val, WB2_WGN_B); ipipe_set_wb_regs()
638 void ipipe_set_cfa_regs(void __iomem *base_addr, struct vpfe_ipipe_cfa *cfa) ipipe_set_cfa_regs() argument
640 ipipe_clock_enable(base_addr); ipipe_set_cfa_regs()
642 regw_ip(base_addr, cfa->alg, CFA_MODE); ipipe_set_cfa_regs()
643 regw_ip(base_addr, cfa->hpf_thr_2dir & CFA_HPF_THR_2DIR_MASK, ipipe_set_cfa_regs()
645 regw_ip(base_addr, cfa->hpf_slp_2dir & CFA_HPF_SLOPE_2DIR_MASK, ipipe_set_cfa_regs()
647 regw_ip(base_addr, cfa->hp_mix_thr_2dir & CFA_HPF_MIX_THR_2DIR_MASK, ipipe_set_cfa_regs()
649 regw_ip(base_addr, cfa->hp_mix_slope_2dir & CFA_HPF_MIX_SLP_2DIR_MASK, ipipe_set_cfa_regs()
651 regw_ip(base_addr, cfa->dir_thr_2dir & CFA_DIR_THR_2DIR_MASK, ipipe_set_cfa_regs()
653 regw_ip(base_addr, cfa->dir_slope_2dir & CFA_DIR_SLP_2DIR_MASK, ipipe_set_cfa_regs()
655 regw_ip(base_addr, cfa->nd_wt_2dir & CFA_ND_WT_2DIR_MASK, ipipe_set_cfa_regs()
657 regw_ip(base_addr, cfa->hue_fract_daa & CFA_DAA_HUE_FRA_MASK, ipipe_set_cfa_regs()
659 regw_ip(base_addr, cfa->edge_thr_daa & CFA_DAA_EDG_THR_MASK, ipipe_set_cfa_regs()
661 regw_ip(base_addr, cfa->thr_min_daa & CFA_DAA_THR_MIN_MASK, ipipe_set_cfa_regs()
663 regw_ip(base_addr, cfa->thr_slope_daa & CFA_DAA_THR_SLP_MASK, ipipe_set_cfa_regs()
665 regw_ip(base_addr, cfa->slope_min_daa & CFA_DAA_SLP_MIN_MASK, ipipe_set_cfa_regs()
667 regw_ip(base_addr, cfa->slope_slope_daa & CFA_DAA_SLP_SLP_MASK, ipipe_set_cfa_regs()
669 regw_ip(base_addr, cfa->lp_wt_daa & CFA_DAA_LP_WT_MASK, ipipe_set_cfa_regs()
674 ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id, ipipe_set_rgb2rgb_regs() argument
682 ipipe_clock_enable(base_addr); ipipe_set_rgb2rgb_regs()
694 regw_ip(base_addr, val, offset + RGB_MUL_RR); ipipe_set_rgb2rgb_regs()
697 regw_ip(base_addr, val, offset + RGB_MUL_GR); ipipe_set_rgb2rgb_regs()
700 regw_ip(base_addr, val, offset + RGB_MUL_BR); ipipe_set_rgb2rgb_regs()
703 regw_ip(base_addr, val, offset + RGB_MUL_RG); ipipe_set_rgb2rgb_regs()
706 regw_ip(base_addr, val, offset + RGB_MUL_GG); ipipe_set_rgb2rgb_regs()
709 regw_ip(base_addr, val, offset + RGB_MUL_BG); ipipe_set_rgb2rgb_regs()
712 regw_ip(base_addr, val, offset + RGB_MUL_RB); ipipe_set_rgb2rgb_regs()
715 regw_ip(base_addr, val, offset + RGB_MUL_GB); ipipe_set_rgb2rgb_regs()
718 regw_ip(base_addr, val, offset + RGB_MUL_BB); ipipe_set_rgb2rgb_regs()
721 regw_ip(base_addr, rgb->out_ofst_r & offset_mask, offset + RGB_OFT_OR); ipipe_set_rgb2rgb_regs()
722 regw_ip(base_addr, rgb->out_ofst_g & offset_mask, offset + RGB_OFT_OG); ipipe_set_rgb2rgb_regs()
723 regw_ip(base_addr, rgb->out_ofst_b & offset_mask, offset + RGB_OFT_OB); ipipe_set_rgb2rgb_regs()
741 ipipe_set_gamma_regs(void __iomem *base_addr, void __iomem *isp5_base_addr, ipipe_set_gamma_regs() argument
747 ipipe_clock_enable(base_addr); ipipe_set_gamma_regs()
754 regw_ip(base_addr, val, GMM_CFG); ipipe_set_gamma_regs()
773 ipipe_set_3d_lut_regs(void __iomem *base_addr, void __iomem *isp5_base_addr, ipipe_set_3d_lut_regs() argument
782 ipipe_clock_enable(base_addr); ipipe_set_3d_lut_regs()
783 regw_ip(base_addr, lut_3d->en, D3LUT_EN); ipipe_set_3d_lut_regs()
822 ipipe_set_lum_adj_regs(void __iomem *base_addr, struct ipipe_lum_adj *lum_adj) ipipe_set_lum_adj_regs() argument
826 ipipe_clock_enable(base_addr); ipipe_set_lum_adj_regs()
831 regw_ip(base_addr, val, YUV_ADJ); ipipe_set_lum_adj_regs()
837 void ipipe_set_rgb2ycbcr_regs(void __iomem *base_addr, ipipe_set_rgb2ycbcr_regs() argument
843 ipipe_clock_enable(base_addr); ipipe_set_rgb2ycbcr_regs()
845 regw_ip(base_addr, val, YUV_MUL_RY); ipipe_set_rgb2ycbcr_regs()
847 regw_ip(base_addr, val, YUV_MUL_GY); ipipe_set_rgb2ycbcr_regs()
849 regw_ip(base_addr, val, YUV_MUL_BY); ipipe_set_rgb2ycbcr_regs()
851 regw_ip(base_addr, val, YUV_MUL_RCB); ipipe_set_rgb2ycbcr_regs()
853 regw_ip(base_addr, val, YUV_MUL_GCB); ipipe_set_rgb2ycbcr_regs()
855 regw_ip(base_addr, val, YUV_MUL_BCB); ipipe_set_rgb2ycbcr_regs()
857 regw_ip(base_addr, val, YUV_MUL_RCR); ipipe_set_rgb2ycbcr_regs()
859 regw_ip(base_addr, val, YUV_MUL_GCR); ipipe_set_rgb2ycbcr_regs()
861 regw_ip(base_addr, val, YUV_MUL_BCR); ipipe_set_rgb2ycbcr_regs()
862 regw_ip(base_addr, yuv->out_ofst_y & RGB2YCBCR_OFST_MASK, YUV_OFT_Y); ipipe_set_rgb2ycbcr_regs()
863 regw_ip(base_addr, yuv->out_ofst_cb & RGB2YCBCR_OFST_MASK, YUV_OFT_CB); ipipe_set_rgb2ycbcr_regs()
864 regw_ip(base_addr, yuv->out_ofst_cr & RGB2YCBCR_OFST_MASK, YUV_OFT_CR); ipipe_set_rgb2ycbcr_regs()
869 ipipe_set_yuv422_conv_regs(void __iomem *base_addr, ipipe_set_yuv422_conv_regs() argument
874 ipipe_clock_enable(base_addr); ipipe_set_yuv422_conv_regs()
878 regw_ip(base_addr, val, YUV_PHS); ipipe_set_yuv422_conv_regs()
882 ipipe_set_gbce_regs(void __iomem *base_addr, void __iomem *isp5_base_addr, ipipe_set_gbce_regs() argument
891 ipipe_clock_enable(base_addr); ipipe_set_gbce_regs()
892 regw_ip(base_addr, gbce->en & 1, GBCE_EN); ipipe_set_gbce_regs()
897 regw_ip(base_addr, gbce->type, GBCE_TYP); ipipe_set_gbce_regs()
909 ipipe_set_ee_regs(void __iomem *base_addr, void __iomem *isp5_base_addr, ipipe_set_ee_regs() argument
915 ipipe_clock_enable(base_addr); ipipe_set_ee_regs()
916 regw_ip(base_addr, ee->en, YEE_EN); ipipe_set_ee_regs()
923 regw_ip(base_addr, val, YEE_TYP); ipipe_set_ee_regs()
925 regw_ip(base_addr, ee->hpf_shft, YEE_SHF); ipipe_set_ee_regs()
926 regw_ip(base_addr, ee->hpf_coef_00 & YEE_COEF_MASK, YEE_MUL_00); ipipe_set_ee_regs()
927 regw_ip(base_addr, ee->hpf_coef_01 & YEE_COEF_MASK, YEE_MUL_01); ipipe_set_ee_regs()
928 regw_ip(base_addr, ee->hpf_coef_02 & YEE_COEF_MASK, YEE_MUL_02); ipipe_set_ee_regs()
929 regw_ip(base_addr, ee->hpf_coef_10 & YEE_COEF_MASK, YEE_MUL_10); ipipe_set_ee_regs()
930 regw_ip(base_addr, ee->hpf_coef_11 & YEE_COEF_MASK, YEE_MUL_11); ipipe_set_ee_regs()
931 regw_ip(base_addr, ee->hpf_coef_12 & YEE_COEF_MASK, YEE_MUL_12); ipipe_set_ee_regs()
932 regw_ip(base_addr, ee->hpf_coef_20 & YEE_COEF_MASK, YEE_MUL_20); ipipe_set_ee_regs()
933 regw_ip(base_addr, ee->hpf_coef_21 & YEE_COEF_MASK, YEE_MUL_21); ipipe_set_ee_regs()
934 regw_ip(base_addr, ee->hpf_coef_22 & YEE_COEF_MASK, YEE_MUL_22); ipipe_set_ee_regs()
935 regw_ip(base_addr, ee->yee_thr & YEE_THR_MASK, YEE_THR); ipipe_set_ee_regs()
936 regw_ip(base_addr, ee->es_gain & YEE_ES_GAIN_MASK, YEE_E_GAN); ipipe_set_ee_regs()
937 regw_ip(base_addr, ee->es_thr1 & YEE_ES_THR1_MASK, YEE_E_THR1); ipipe_set_ee_regs()
938 regw_ip(base_addr, ee->es_thr2 & YEE_THR_MASK, YEE_E_THR2); ipipe_set_ee_regs()
939 regw_ip(base_addr, ee->es_gain_grad & YEE_THR_MASK, YEE_G_GAN); ipipe_set_ee_regs()
940 regw_ip(base_addr, ee->es_ofst_grad & YEE_THR_MASK, YEE_G_OFT); ipipe_set_ee_regs()
953 static void ipipe_set_mf(void __iomem *base_addr) ipipe_set_mf() argument
956 regw_ip(base_addr, VPFE_IPIPE_CAR_DYN_SWITCH, CAR_TYP); ipipe_set_mf()
958 regw_ip(base_addr, CAR_MF_THR, CAR_SW); ipipe_set_mf()
962 ipipe_set_gain_ctrl(void __iomem *base_addr, struct vpfe_ipipe_car *car) ipipe_set_gain_ctrl() argument
964 regw_ip(base_addr, VPFE_IPIPE_CAR_CHR_GAIN_CTRL, CAR_TYP); ipipe_set_gain_ctrl()
965 regw_ip(base_addr, car->hpf, CAR_HPF_TYP); ipipe_set_gain_ctrl()
966 regw_ip(base_addr, car->hpf_shft & CAR_HPF_SHIFT_MASK, CAR_HPF_SHF); ipipe_set_gain_ctrl()
967 regw_ip(base_addr, car->hpf_thr, CAR_HPF_THR); ipipe_set_gain_ctrl()
968 regw_ip(base_addr, car->gain1.gain, CAR_GN1_GAN); ipipe_set_gain_ctrl()
969 regw_ip(base_addr, car->gain1.shft & CAR_GAIN1_SHFT_MASK, CAR_GN1_SHF); ipipe_set_gain_ctrl()
970 regw_ip(base_addr, car->gain1.gain_min & CAR_GAIN_MIN_MASK, ipipe_set_gain_ctrl()
972 regw_ip(base_addr, car->gain2.gain, CAR_GN2_GAN); ipipe_set_gain_ctrl()
973 regw_ip(base_addr, car->gain2.shft & CAR_GAIN2_SHFT_MASK, CAR_GN2_SHF); ipipe_set_gain_ctrl()
974 regw_ip(base_addr, car->gain2.gain_min & CAR_GAIN_MIN_MASK, ipipe_set_gain_ctrl()
978 void ipipe_set_car_regs(void __iomem *base_addr, struct vpfe_ipipe_car *car) ipipe_set_car_regs() argument
982 ipipe_clock_enable(base_addr); ipipe_set_car_regs()
983 regw_ip(base_addr, car->en, CAR_EN); ipipe_set_car_regs()
990 ipipe_set_mf(base_addr); ipipe_set_car_regs()
994 ipipe_set_gain_ctrl(base_addr, car); ipipe_set_car_regs()
999 ipipe_set_mf(base_addr); ipipe_set_car_regs()
1000 ipipe_set_gain_ctrl(base_addr, car); ipipe_set_car_regs()
1004 regw_ip(base_addr, VPFE_IPIPE_CAR_DYN_SWITCH, CAR_TYP); ipipe_set_car_regs()
1008 regw_ip(base_addr, val, CAR_SW); ipipe_set_car_regs()
1013 void ipipe_set_cgs_regs(void __iomem *base_addr, struct vpfe_ipipe_cgs *cgs) ipipe_set_cgs_regs() argument
1015 ipipe_clock_enable(base_addr); ipipe_set_cgs_regs()
1016 regw_ip(base_addr, cgs->en, CGS_EN); ipipe_set_cgs_regs()
1022 regw_ip(base_addr, cgs->h_thr, CGS_GN1_H_THR); ipipe_set_cgs_regs()
1023 regw_ip(base_addr, cgs->h_slope, CGS_GN1_H_GAN); ipipe_set_cgs_regs()
1024 regw_ip(base_addr, cgs->h_shft & CAR_SHIFT_MASK, CGS_GN1_H_SHF); ipipe_set_cgs_regs()
1025 regw_ip(base_addr, cgs->h_min, CGS_GN1_H_MIN); ipipe_set_cgs_regs()
H A Ddm365_isif.c73 static inline u32 isif_read(void __iomem *base_addr, u32 offset) isif_read() argument
75 return readl(base_addr + offset); isif_read()
78 static inline void isif_write(void __iomem *base_addr, u32 val, u32 offset) isif_write() argument
80 writel(val, base_addr + offset); isif_write()
83 static inline u32 isif_merge(void __iomem *base_addr, u32 mask, u32 val, isif_merge() argument
86 u32 new_val = (isif_read(base_addr, offset) & ~mask) | (val & mask); isif_merge()
88 isif_write(base_addr, new_val, offset); isif_merge()
95 isif_merge(isif->isif_cfg.base_addr, ISIF_SYNCEN_WEN_MASK, isif_enable_output_to_sdram()
111 isif_write(isif->isif_cfg.base_addr, 0, CLAMPCFG); isif_disable_all_modules()
113 isif_write(isif->isif_cfg.base_addr, 0, DFCCTL); isif_disable_all_modules()
115 isif_write(isif->isif_cfg.base_addr, 0, CSCCTL); isif_disable_all_modules()
117 isif_write(isif->isif_cfg.base_addr, 0, LINCFG0); isif_disable_all_modules()
131 isif_merge(isif->isif_cfg.base_addr, ISIF_SYNCEN_VDHDEN_MASK, isif_enable()
148 field_status = isif_read(isif->isif_cfg.base_addr, MODESET); vpfe_isif_get_fid()
410 isif_write(isif->isif_cfg.base_addr, (addr >> 21) & isif_video_queue()
412 isif_write(isif->isif_cfg.base_addr, (addr >> 5) & isif_video_queue()
649 void __iomem *base = isif->isif_cfg.base_addr; isif_config_gain_offset()
679 isif_write(isif->isif_cfg.base_addr, val, CLDCOFST); isif_config_bclamp()
691 isif_write(isif->isif_cfg.base_addr, val, CLAMPCFG); isif_config_bclamp()
715 isif_write(isif->isif_cfg.base_addr, val, CLHWIN0); isif_config_bclamp()
718 isif_write(isif->isif_cfg.base_addr, val, CLHWIN1); isif_config_bclamp()
721 isif_write(isif->isif_cfg.base_addr, val, CLHWIN2); isif_config_bclamp()
734 isif_write(isif->isif_cfg.base_addr, val, CLVWIN0); isif_config_bclamp()
739 isif_write(isif->isif_cfg.base_addr, val, CLVRV); isif_config_bclamp()
744 isif_write(isif->isif_cfg.base_addr, val, CLVWIN1); isif_config_bclamp()
748 isif_write(isif->isif_cfg.base_addr, val, CLVWIN2); isif_config_bclamp()
751 isif_write(isif->isif_cfg.base_addr, val, CLVWIN3); isif_config_bclamp()
755 isif_write(isif->isif_cfg.base_addr, val, CLSV); isif_config_bclamp()
778 isif_write(isif->isif_cfg.base_addr, isif_setwin()
780 isif_write(isif->isif_cfg.base_addr, isif_setwin()
795 isif_write(isif->isif_cfg.base_addr, mid_img, VDINT1); isif_setwin()
799 isif_write(isif->isif_cfg.base_addr, 0, VDINT0); isif_setwin()
801 isif_write(isif->isif_cfg.base_addr, vert_nr_lines, VDINT0); isif_setwin()
802 isif_write(isif->isif_cfg.base_addr, isif_setwin()
804 isif_write(isif->isif_cfg.base_addr, isif_setwin()
806 isif_write(isif->isif_cfg.base_addr, isif_setwin()
836 isif_write(isif->isif_cfg.base_addr, val, DFCCTL); isif_config_dfc()
840 isif_write(isif->isif_cfg.base_addr, val, VDFSATLV); isif_config_dfc()
842 isif_write(isif->isif_cfg.base_addr, vdfc->table[0].pos_vert & isif_config_dfc()
844 isif_write(isif->isif_cfg.base_addr, vdfc->table[0].pos_horz & isif_config_dfc()
848 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
850 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
852 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
856 val = isif_read(isif->isif_cfg.base_addr, DFCMEMCTL); isif_config_dfc()
860 isif_write(isif->isif_cfg.base_addr, val, DFCMEMCTL); isif_config_dfc()
862 while (count && (isif_read(isif->isif_cfg.base_addr, DFCMEMCTL) & 0x01)) isif_config_dfc()
865 val = isif_read(isif->isif_cfg.base_addr, DFCMEMCTL); isif_config_dfc()
872 isif_write(isif->isif_cfg.base_addr, vdfc->table[i].pos_vert & isif_config_dfc()
875 isif_write(isif->isif_cfg.base_addr, vdfc->table[i].pos_horz & isif_config_dfc()
880 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
882 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
884 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
887 val = isif_read(isif->isif_cfg.base_addr, DFCMEMCTL); isif_config_dfc()
891 isif_write(isif->isif_cfg.base_addr, val, DFCMEMCTL); isif_config_dfc()
894 while (count && (isif_read(isif->isif_cfg.base_addr, isif_config_dfc()
898 val = isif_read(isif->isif_cfg.base_addr, DFCMEMCTL); isif_config_dfc()
906 isif_write(isif->isif_cfg.base_addr, 0, DFCMEM0); isif_config_dfc()
907 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
909 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
913 isif_merge(isif->isif_cfg.base_addr, (1 << ISIF_VDFC_EN_SHIFT), isif_config_dfc()
916 isif_merge(isif->isif_cfg.base_addr, (1 << ISIF_VDFC_EN_SHIFT), isif_config_dfc()
919 isif_write(isif->isif_cfg.base_addr, 0x6, DFCMEMCTL); isif_config_dfc()
923 (isif_read(isif->isif_cfg.base_addr, DFCMEMCTL) & 0x2)) isif_config_dfc()
925 val = isif_read(isif->isif_cfg.base_addr, DFCMEMCTL); isif_config_dfc()
930 isif_write(isif->isif_cfg.base_addr, isif_config_dfc()
943 isif_write(isif->isif_cfg.base_addr, 0, CSCCTL); isif_config_csc()
966 isif_write(isif->isif_cfg.base_addr, val2, isif_config_csc()
971 isif_write(isif->isif_cfg.base_addr, df_csc->start_pix & isif_config_csc()
979 isif_write(isif->isif_cfg.base_addr, df_csc->num_pixels & isif_config_csc()
981 isif_write(isif->isif_cfg.base_addr, df_csc->start_line & isif_config_csc()
987 isif_write(isif->isif_cfg.base_addr, df_csc->num_lines & isif_config_csc()
990 isif_write(isif->isif_cfg.base_addr, 1, CSCCTL); isif_config_csc()
1001 isif_write(isif->isif_cfg.base_addr, 0, LINCFG0); isif_config_linearization()
1009 isif_write(isif->isif_cfg.base_addr, val, LINCFG0); isif_config_linearization()
1014 isif_write(isif->isif_cfg.base_addr, val, LINCFG1); isif_config_linearization()
1033 isif_write(isif->isif_cfg.base_addr, val, CULH); isif_config_culling()
1035 isif_write(isif->isif_cfg.base_addr, cul->vcpat, CULV); isif_config_culling()
1037 isif_merge(isif->isif_cfg.base_addr, ISIF_LPF_MASK << ISIF_LPF_SHIFT, isif_config_culling()
1085 isif_write(isif->isif_cfg.base_addr, 0, REC656IF); isif_config_raw()
1098 isif_write(isif->isif_cfg.base_addr, val, CCDCFG); isif_config_raw()
1132 isif_write(isif->isif_cfg.base_addr, val, MODESET); isif_config_raw()
1146 isif_write(isif->isif_cfg.base_addr, val, CGAMMAWD); isif_config_raw()
1153 isif_write(isif->isif_cfg.base_addr, val, MISC); isif_config_raw()
1163 isif_write(isif->isif_cfg.base_addr, val, CCOLP); isif_config_raw()
1178 isif_write(isif->isif_cfg.base_addr, val, HSIZE); isif_config_raw()
1183 isif_write(isif->isif_cfg.base_addr, isif_config_raw()
1187 isif_write(isif->isif_cfg.base_addr, isif_config_raw()
1191 isif_write(isif->isif_cfg.base_addr, isif_config_raw()
1195 isif_write(isif->isif_cfg.base_addr, isif_config_raw()
1213 isif_write(isif->isif_cfg.base_addr, val, DATAHOFST); isif_config_raw()
1216 isif_write(isif->isif_cfg.base_addr, val, DATAVOFST); isif_config_raw()
1265 isif_write(isif->isif_cfg.base_addr, 3, REC656IF); isif_config_ycbcr()
1275 isif_write(isif->isif_cfg.base_addr, 3, REC656IF); isif_config_ycbcr()
1286 isif_write(isif->isif_cfg.base_addr, 3, REC656IF); isif_config_ycbcr()
1310 isif_write(isif->isif_cfg.base_addr, modeset, MODESET); isif_config_ycbcr()
1314 isif_write(isif->isif_cfg.base_addr, ccdcfg, CCDCFG); isif_config_ycbcr()
1327 isif_write(isif->isif_cfg.base_addr, isif_config_ycbcr()
1335 isif_write(isif->isif_cfg.base_addr, isif_config_ycbcr()
1784 isif_write(isif->isif_cfg.base_addr, 0, i); isif_restore_defaults()
1786 isif_write(isif->isif_cfg.base_addr, 0xffff, CULH); isif_restore_defaults()
1787 isif_write(isif->isif_cfg.base_addr, 0xff, CULV); isif_restore_defaults()
1950 iounmap(isif->isif_cfg.base_addr); isif_remove()
2022 isif->isif_cfg.base_addr = addr; vpfe_isif_init()
2080 if (isif->isif_cfg.base_addr) vpfe_isif_init()
2081 iounmap(isif->isif_cfg.base_addr); vpfe_isif_init()
H A Ddm365_ipipe_hw.h530 void ipipe_set_d2f_regs(void __iomem *base_addr, unsigned int id,
532 void ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id,
534 void ipipe_set_yuv422_conv_regs(void __iomem *base_addr,
536 void ipipe_set_lum_adj_regs(void __iomem *base_addr,
538 void ipipe_set_rgb2ycbcr_regs(void __iomem *base_addr,
540 void ipipe_set_lutdpc_regs(void __iomem *base_addr,
542 void ipipe_set_otfdpc_regs(void __iomem *base_addr,
544 void ipipe_set_3d_lut_regs(void __iomem *base_addr,
546 void ipipe_set_gamma_regs(void __iomem *base_addr,
548 void ipipe_set_ee_regs(void __iomem *base_addr,
550 void ipipe_set_gbce_regs(void __iomem *base_addr,
552 void ipipe_set_gic_regs(void __iomem *base_addr, struct vpfe_ipipe_gic *gic);
553 void ipipe_set_cfa_regs(void __iomem *base_addr, struct vpfe_ipipe_cfa *cfa);
554 void ipipe_set_car_regs(void __iomem *base_addr, struct vpfe_ipipe_car *car);
555 void ipipe_set_cgs_regs(void __iomem *base_addr, struct vpfe_ipipe_cgs *cgs);
556 void ipipe_set_wb_regs(void __iomem *base_addr, struct vpfe_ipipe_wb *wb);
H A Ddm365_ipipe.c92 ipipe_set_lutdpc_regs(ipipe->base_addr, ipipe->isp5_base_addr, lutdpc); ipipe_set_lutdpc_params()
190 ipipe_set_otfdpc_regs(ipipe->base_addr, otfdpc); ipipe_set_otfdpc_params()
249 ipipe_set_d2f_regs(ipipe->base_addr, id, nf); ipipe_set_nf_params()
318 ipipe_set_gic_regs(ipipe->base_addr, gic); ipipe_set_gic_params()
373 ipipe_set_wb_regs(ipipe->base_addr, wbal); ipipe_set_wb_params()
424 ipipe_set_cfa_regs(ipipe->base_addr, cfa); ipipe_set_cfa_params()
531 ipipe_set_rgb2rgb_regs(ipipe->base_addr, id, rgb2rgb); ipipe_set_rgb2rgb_params()
674 ipipe_set_gamma_regs(ipipe->base_addr, ipipe->isp5_base_addr, gamma); ipipe_set_gamma_params()
776 ipipe_set_3d_lut_regs(ipipe->base_addr, ipipe->isp5_base_addr, lut); ipipe_set_3d_lut_params()
863 ipipe_set_rgb2ycbcr_regs(ipipe->base_addr, rgb2yuv); ipipe_set_rgb2yuv_params()
913 ipipe_set_gbce_regs(ipipe->base_addr, ipipe->isp5_base_addr, gbce); ipipe_set_gbce_params()
966 ipipe_set_yuv422_conv_regs(ipipe->base_addr, yuv422_conv); ipipe_set_yuv422_conv_params()
1035 ipipe_set_ee_regs(ipipe->base_addr, ipipe->isp5_base_addr, yee); ipipe_set_yee_params()
1098 ipipe_set_car_regs(ipipe->base_addr, car); ipipe_set_car_params()
1136 ipipe_set_cgs_regs(ipipe->base_addr, cgs); ipipe_set_cgs_params()
1385 val = regr_ip(vpfe_dev->vpfe_ipipe.base_addr, vpfe_ipipe_enable()
1389 regw_ip(vpfe_dev->vpfe_ipipe.base_addr, en, IPIPE_SRC_EN); vpfe_ipipe_enable()
1611 ipipe_set_lum_adj_regs(ipipe->base_addr, lum_adj); ipipe_s_ctrl()
1616 ipipe_set_lum_adj_regs(ipipe->base_addr, lum_adj); ipipe_s_ctrl()
1805 ipipe->base_addr = ioremap_nocache(res->start, res_len); vpfe_ipipe_init()
1806 if (!ipipe->base_addr) vpfe_ipipe_init()
1857 iounmap(ipipe->base_addr); vpfe_ipipe_cleanup()
H A Ddm365_resizer.c975 return resizer_set_outaddr(resizer->base_addr, resizer_a_video_out_queue()
989 return resizer_set_outaddr(resizer->base_addr, resizer_b_video_out_queue()
1013 val = regr_rsz(resizer->base_addr, RSZ_SRC_EN); resizer_enable()
1018 val = regr_rsz(resizer->base_addr, RSZ_A); resizer_enable()
1023 val = regr_rsz(resizer->base_addr, RSZ_B); resizer_enable()
1028 rsz_enable(resizer->base_addr, RSZ_A, en); resizer_enable()
1031 rsz_enable(resizer->base_addr, RSZ_B, en); resizer_enable()
1116 rsz_src_enable(resizer->base_addr, 1); vpfe_resizer_buffer_isr()
1118 rsz_src_enable(resizer->base_addr, 0); vpfe_resizer_buffer_isr()
1898 vpfe_rsz->base_addr = ioremap_nocache(res->start, res_len); vpfe_resizer_init()
1899 if (!vpfe_rsz->base_addr) vpfe_resizer_init()
1991 iounmap(vpfe_rsz->base_addr); vpfe_resizer_cleanup()
H A Ddm365_ipipe.h123 void __iomem *base_addr; member in struct:vpfe_ipipe_device
H A Ddm365_isif.h162 void __iomem *base_addr; member in struct:isif_oper_config
H A Ddm365_resizer.h231 void __iomem *base_addr; member in struct:vpfe_resizer_device
/linux-4.4.14/arch/microblaze/kernel/
H A Dheartbeat.c18 static unsigned int base_addr; variable
24 if (base_addr) { microblaze_heartbeat()
26 out_be32(base_addr, 1); microblaze_heartbeat()
28 out_be32(base_addr, 0); microblaze_heartbeat()
62 base_addr = be32_to_cpup(of_get_property(gpio, "reg", NULL)); microblaze_setup_heartbeat()
63 base_addr = (unsigned long) ioremap(base_addr, PAGE_SIZE); microblaze_setup_heartbeat()
64 pr_notice("Heartbeat GPIO at 0x%x\n", base_addr); microblaze_setup_heartbeat()
69 out_be32(base_addr + 4, 0); microblaze_setup_heartbeat()
H A Dearly_printk.c24 static u32 base_addr; variable
39 while (--retries && (in_be32(base_addr + 8) & (1 << 3))) early_printk_uartlite_putc()
45 out_be32(base_addr + 4, c & 0xff); early_printk_uartlite_putc()
85 !((in_be32(base_addr + 0x14) & BOTH_EMPTY) == BOTH_EMPTY)) early_printk_uart16550_putc()
89 out_be32(base_addr, c & 0xff); early_printk_uart16550_putc()
118 base_addr = of_early_console(&version); setup_early_printk()
119 if (base_addr) { setup_early_printk()
121 early_console_reg_tlb_alloc(base_addr); setup_early_printk()
127 base_addr); setup_early_printk()
134 base_addr); setup_early_printk()
156 pr_info("early_printk_console remapping from 0x%x to ", base_addr); remap_early_printk()
157 base_addr = (u32) ioremap(base_addr, PAGE_SIZE); remap_early_printk()
158 pr_cont("0x%x\n", base_addr); remap_early_printk()
/linux-4.4.14/arch/nios2/kernel/
H A Dearly_printk.c21 static unsigned long base_addr; variable
31 __builtin_ldwio((void *)(base_addr + ALTERA_JTAGUART_CONTROL_REG))
33 __builtin_stwio((void *)(base_addr + ALTERA_JTAGUART_CONTROL_REG), v)
35 __builtin_stwio((void *)(base_addr + ALTERA_JTAGUART_DATA_REG), v)
61 __builtin_ldwio((void *)(base_addr + ALTERA_UART_STATUS_REG))
63 __builtin_stwio((void *)(base_addr + ALTERA_UART_TXDATA_REG), v)
99 base_addr = of_early_console(); setup_early_printk()
101 base_addr = 0; setup_early_printk()
104 if (!base_addr) setup_early_printk()
117 pr_info("early_console initialized at 0x%08lx\n", base_addr); setup_early_printk()
/linux-4.4.14/arch/sparc/prom/
H A Dmemory.c23 sp_banks[index].base_addr = (unsigned long) p->start_adr; prom_meminit_v0()
42 sp_banks[i].base_addr = reg[i].phys_addr; prom_meminit_v2()
53 if (x->base_addr > y->base_addr) sp_banks_cmp()
55 if (x->base_addr < y->base_addr) sp_banks_cmp()
82 sp_banks[num_ents].base_addr = 0xdeadbeef; prom_meminit()
/linux-4.4.14/drivers/clk/mediatek/
H A Dclk-apmixed.c29 void __iomem *base_addr; member in struct:mtk_ref2usb_tx
41 return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK; mtk_ref2usb_tx_is_prepared()
49 val = readl(tx->base_addr); mtk_ref2usb_tx_prepare()
52 writel(val, tx->base_addr); mtk_ref2usb_tx_prepare()
56 writel(val, tx->base_addr); mtk_ref2usb_tx_prepare()
59 writel(val, tx->base_addr); mtk_ref2usb_tx_prepare()
69 val = readl(tx->base_addr); mtk_ref2usb_tx_unprepare()
71 writel(val, tx->base_addr); mtk_ref2usb_tx_unprepare()
91 tx->base_addr = reg; mtk_clk_register_ref2usb_tx()
H A Dclk-pll.c46 void __iomem *base_addr; member in struct:mtk_clk_pll
63 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; mtk_pll_is_prepared()
96 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; mtk_pll_set_rate_regs()
115 con1 = readl(pll->base_addr + REG_CON1); mtk_pll_set_rate_regs()
120 writel(con1, pll->base_addr + REG_CON1); mtk_pll_set_rate_regs()
226 r = readl(pll->base_addr + REG_CON0); mtk_pll_prepare()
228 writel(r, pll->base_addr + REG_CON0); mtk_pll_prepare()
238 r = readl(pll->base_addr + REG_CON0); mtk_pll_prepare()
240 writel(r, pll->base_addr + REG_CON0); mtk_pll_prepare()
252 r = readl(pll->base_addr + REG_CON0); mtk_pll_unprepare()
254 writel(r, pll->base_addr + REG_CON0); mtk_pll_unprepare()
262 r = readl(pll->base_addr + REG_CON0); mtk_pll_unprepare()
264 writel(r, pll->base_addr + REG_CON0); mtk_pll_unprepare()
294 pll->base_addr = base + data->reg; mtk_clk_register_pll()
/linux-4.4.14/arch/x86/um/asm/
H A Dmm_context.h38 ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
41 (((info)->base_addr & 0xff000000) | \
42 (((info)->base_addr & 0x00ff0000) >> 16) | \
53 (info)->base_addr == 0 && \
H A Ddesc.h7 (info)->base_addr == 0 && \
/linux-4.4.14/drivers/staging/netlogic/
H A Dxlr_net.c72 static inline void xlr_reg_update(u32 *base_addr, xlr_reg_update() argument
77 tmp = xlr_nae_rdreg(base_addr, off); xlr_reg_update()
78 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask)); xlr_reg_update()
306 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0, xlr_hw_set_mac_addr()
309 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1, xlr_hw_set_mac_addr()
312 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff); xlr_hw_set_mac_addr()
313 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff); xlr_hw_set_mac_addr()
314 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff); xlr_hw_set_mac_addr()
315 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff); xlr_hw_set_mac_addr()
317 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, xlr_hw_set_mac_addr()
324 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f); xlr_hw_set_mac_addr()
343 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG); xlr_set_rx_mode()
355 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval); xlr_set_rx_mode()
362 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER); xlr_stats()
363 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER); xlr_stats()
364 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER); xlr_stats()
365 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER); xlr_stats()
366 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER); xlr_stats()
367 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr, xlr_stats()
369 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr, xlr_stats()
372 stats->multicast = xlr_nae_rdreg(priv->base_addr, xlr_stats()
374 stats->collisions = xlr_nae_rdreg(priv->base_addr, xlr_stats()
377 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
379 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
381 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
383 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
386 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
388 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
395 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
397 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
399 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr, xlr_stats()
431 base = priv->base_addr; xlr_config_spill()
507 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff)); xlr_config_pde()
508 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1, xlr_config_pde()
511 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff)); xlr_config_pde()
512 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1, xlr_config_pde()
515 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff)); xlr_config_pde()
516 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1, xlr_config_pde()
519 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff)); xlr_config_pde()
520 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1, xlr_config_pde()
538 xlr_nae_wreg(priv->base_addr, xlr_config_common()
549 xlr_nae_wreg(priv->base_addr, xlr_config_common()
554 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3); xlr_config_common()
555 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff); xlr_config_common()
556 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff); xlr_config_common()
557 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff); xlr_config_common()
558 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff); xlr_config_common()
559 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0); xlr_config_common()
613 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val); xlr_config_translate_table()
623 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01); xlr_config_parser()
626 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG, xlr_config_parser()
631 xlr_nae_wreg(priv->base_addr, R_L3CTABLE, xlr_config_parser()
634 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1, xlr_config_parser()
639 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6); xlr_config_parser()
640 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17); xlr_config_parser()
642 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val); xlr_config_parser()
643 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val); xlr_config_parser()
648 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val) xlr_phy_write() argument
658 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum); xlr_phy_write()
661 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val); xlr_phy_write()
666 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0) xlr_phy_write()
678 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum) xlr_phy_read() argument
689 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, xlr_phy_read()
693 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, xlr_phy_read()
699 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0) xlr_phy_read()
709 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0); xlr_phy_read()
712 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS); xlr_phy_read()
784 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217); xlr_set_gmac_speed()
788 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117); xlr_set_gmac_speed()
794 xlr_nae_wreg(priv->base_addr, xlr_set_gmac_speed()
797 xlr_nae_wreg(priv->base_addr, xlr_set_gmac_speed()
800 xlr_nae_wreg(priv->base_addr, xlr_set_gmac_speed()
804 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2); xlr_set_gmac_speed()
806 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1); xlr_set_gmac_speed()
808 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0); xlr_set_gmac_speed()
819 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG); xlr_gmac_link_adjust()
893 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7); xlr_setup_mdio()
918 xlr_reg_update(priv->base_addr, R_RX_CONTROL, xlr_port_enable()
922 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1, xlr_port_enable()
929 xlr_reg_update(priv->base_addr, R_TX_CONTROL, xlr_port_enable()
934 xlr_reg_update(priv->base_addr, R_RX_CONTROL, xlr_port_enable()
942 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1, xlr_port_disable()
948 xlr_reg_update(priv->base_addr, R_TX_CONTROL, xlr_port_disable()
953 xlr_reg_update(priv->base_addr, R_RX_CONTROL, xlr_port_disable()
969 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL, xlr_gmac_init()
980 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217); xlr_gmac_init()
982 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02); xlr_gmac_init()
984 xlr_nae_wreg(priv->base_addr, R_INTMASK, xlr_gmac_init()
995 xlr_reg_update(priv->base_addr, R_STATCTRL, xlr_gmac_init()
997 xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, xlr_gmac_init()
1046 priv->base_addr = devm_ioremap_resource(&pdev->dev, res); xlr_net_probe()
1047 if (IS_ERR(priv->base_addr)) { xlr_net_probe()
1048 err = PTR_ERR(priv->base_addr); xlr_net_probe()
/linux-4.4.14/drivers/net/ethernet/amd/
H A Dam79c961a.c59 static inline unsigned short read_rreg(u_long base_addr, u_int reg) read_rreg() argument
79 static inline unsigned short read_ireg(u_long base_addr, u_int reg) read_ireg() argument
247 write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP); am79c961_init_for_open()
250 write_ireg (dev->base_addr, 5, 0x00a0); /* Receive address LED */ am79c961_init_for_open()
251 write_ireg (dev->base_addr, 6, 0x0081); /* Collision LED */ am79c961_init_for_open()
252 write_ireg (dev->base_addr, 7, 0x0090); /* XMIT LED */ am79c961_init_for_open()
253 write_ireg (dev->base_addr, 2, 0x0000); /* MODE register selects media */ am79c961_init_for_open()
256 write_rreg (dev->base_addr, i, multi_hash[i - LADRL]); am79c961_init_for_open()
259 write_rreg (dev->base_addr, i, p[0] | (p[1] << 8)); am79c961_init_for_open()
261 write_rreg (dev->base_addr, MODE, mode); am79c961_init_for_open()
262 write_rreg (dev->base_addr, POLLINT, 0); am79c961_init_for_open()
263 write_rreg (dev->base_addr, SIZERXR, -RX_BUFFERS); am79c961_init_for_open()
264 write_rreg (dev->base_addr, SIZETXR, -TX_BUFFERS); am79c961_init_for_open()
295 write_rreg (dev->base_addr, BASERXL, priv->rxhdr); am79c961_init_for_open()
296 write_rreg (dev->base_addr, BASERXH, 0); am79c961_init_for_open()
297 write_rreg (dev->base_addr, BASETXL, priv->txhdr); am79c961_init_for_open()
298 write_rreg (dev->base_addr, BASERXH, 0); am79c961_init_for_open()
299 write_rreg (dev->base_addr, CSR0, CSR0_STOP); am79c961_init_for_open()
300 write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO); am79c961_init_for_open()
301 write_rreg (dev->base_addr, CSR4, CSR4_APAD_XMIT|CSR4_MFCOM|CSR4_RCVCCOM|CSR4_TXSTRTM|CSR4_JABM); am79c961_init_for_open()
302 write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT); am79c961_init_for_open()
313 lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST; am79c961_timer()
368 write_rreg (dev->base_addr, CSR0, CSR0_STOP); am79c961_close()
369 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL); am79c961_close()
389 stopped = read_rreg(dev->base_addr, CSR0) & CSR0_STOP; am79c961_setmulticastlist()
395 write_rreg(dev->base_addr, CTRL1, CTRL1_SPND); am79c961_setmulticastlist()
400 while ((read_rreg(dev->base_addr, CTRL1) & CTRL1_SPND) == 0) { am79c961_setmulticastlist()
411 write_rreg(dev->base_addr, i + LADRL, multi_hash[i]); am79c961_setmulticastlist()
416 write_rreg(dev->base_addr, MODE, mode); am79c961_setmulticastlist()
422 write_rreg(dev->base_addr, CTRL1, 0); am79c961_setmulticastlist()
464 write_rreg (dev->base_addr, CSR0, CSR0_TDMD|CSR0_IENA); am79c961_sendpacket()
596 status = read_rreg(dev->base_addr, CSR0); am79c961_interrupt()
597 write_rreg(dev->base_addr, CSR0, status & am79c961_interrupt()
642 write_rreg (dev->base_addr, CSR0, CSR0_STOP); am79c961_hw_init()
643 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL); am79c961_hw_init()
698 dev->base_addr = res->start; am79c961_probe()
708 if (!request_region(dev->base_addr, 0x18, dev->name)) am79c961_probe()
714 inb(dev->base_addr + NET_RESET); am79c961_probe()
721 if (inb(dev->base_addr) != 0x08 || am79c961_probe()
722 inb(dev->base_addr + 2) != 0x00 || am79c961_probe()
723 inb(dev->base_addr + 4) != 0x2b) am79c961_probe()
727 dev->dev_addr[i] = inb(dev->base_addr + i * 2) & 0xff; am79c961_probe()
749 release_region(dev->base_addr, 0x18); am79c961_probe()
H A Dariadne.c242 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; ariadne_interrupt()
394 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; ariadne_open()
499 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; ariadne_close()
524 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; ariadne_reset()
535 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; ariadne_tx_timeout()
547 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; ariadne_start_xmit()
623 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; ariadne_get_stats()
645 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr; set_multicast_list()
690 release_mem_region(ZTWO_PADDR(dev->base_addr), sizeof(struct Am79C960)); ariadne_remove_one()
717 unsigned long base_addr = board + ARIADNE_LANCE; ariadne_init_one() local
724 r1 = request_mem_region(base_addr, sizeof(struct Am79C960), "Am79C960"); ariadne_init_one()
729 release_mem_region(base_addr, sizeof(struct Am79C960)); ariadne_init_one()
735 release_mem_region(base_addr, sizeof(struct Am79C960)); ariadne_init_one()
750 dev->base_addr = (unsigned long)ZTWO_VADDR(base_addr); ariadne_init_one()
759 release_mem_region(base_addr, sizeof(struct Am79C960)); ariadne_init_one()
H A Dmvme147.c93 dev->base_addr = (unsigned long)MVME147_LANCE_BASE; mvme147lance_probe()
110 dev->name, dev->base_addr, MVME147_LANCE_IRQ, mvme147lance_probe()
122 lp->lance.base = dev->base_addr; mvme147lance_probe()
H A Dlance.c346 dev->base_addr = io[this_dev]; init_module()
365 release_region(dev->base_addr, LANCE_TOTAL_SIZE); cleanup_card()
546 dev->base_addr = ioaddr; lance_probe1()
753 int ioaddr = dev->base_addr; lance_open()
912 outw(0x0000, dev->base_addr + LANCE_ADDR); lance_restart()
913 outw(csr0_bits, dev->base_addr + LANCE_DATA); lance_restart()
920 int ioaddr = dev->base_addr; lance_tx_timeout()
955 int ioaddr = dev->base_addr; lance_start_xmit()
1028 ioaddr = dev->base_addr; lance_interrupt()
1033 outw(0x00, dev->base_addr + LANCE_ADDR); lance_interrupt()
1034 while ((csr0 = inw(dev->base_addr + LANCE_DATA)) & 0x8600 && lance_interrupt()
1037 outw(csr0 & ~0x004f, dev->base_addr + LANCE_DATA); lance_interrupt()
1043 dev->name, csr0, inw(dev->base_addr + LANCE_DATA)); lance_interrupt()
1125 outw(0x0000, dev->base_addr + LANCE_ADDR); lance_interrupt()
1126 outw(0x0004, dev->base_addr + LANCE_DATA); lance_interrupt()
1132 outw(0x0000, dev->base_addr + LANCE_ADDR); lance_interrupt()
1133 outw(0x7940, dev->base_addr + LANCE_DATA); lance_interrupt()
1138 inw(dev->base_addr + LANCE_DATA)); lance_interrupt()
1228 int ioaddr = dev->base_addr; lance_close()
1265 short ioaddr = dev->base_addr; lance_get_stats()
1285 short ioaddr = dev->base_addr; set_multicast_list()
H A Da2065.c679 unsigned long base_addr = board + A2065_LANCE; a2065_init_one() local
685 r1 = request_mem_region(base_addr, sizeof(struct lance_regs), a2065_init_one()
691 release_mem_region(base_addr, sizeof(struct lance_regs)); a2065_init_one()
697 release_mem_region(base_addr, sizeof(struct lance_regs)); a2065_init_one()
719 dev->base_addr = (unsigned long)ZTWO_VADDR(base_addr); a2065_init_one()
723 priv->ll = (volatile struct lance_regs *)dev->base_addr; a2065_init_one()
745 release_mem_region(base_addr, sizeof(struct lance_regs)); a2065_init_one()
764 release_mem_region(ZTWO_PADDR(dev->base_addr), a2065_remove_one()
H A Dnmclan_cs.c632 dev->base_addr = link->resource[0]->start; nmclan_config()
634 ioaddr = dev->base_addr; nmclan_config()
679 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr); nmclan_config()
749 mace_init(lp, dev->base_addr, dev->dev_addr); nmclan_reset()
750 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT); nmclan_reset()
780 unsigned int ioaddr = dev->base_addr; mace_open()
803 unsigned int ioaddr = dev->base_addr; mace_close()
824 "PCMCIA 0x%lx", dev->base_addr); netdev_get_drvinfo()
862 unsigned int ioaddr = dev->base_addr; mace_start_xmit()
931 ioaddr = dev->base_addr; mace_interrupt()
1066 unsigned int ioaddr = dev->base_addr; mace_rx()
1275 update_stats(dev->base_addr, dev); mace_get_stats()
1367 unsigned int ioaddr = dev->base_addr; restore_multicast_list()
1457 unsigned int ioaddr = dev->base_addr; restore_multicast_list()
H A Dpcnet32.c459 ulong ioaddr = dev->base_addr; pcnet32_netif_start()
721 "VLB 0x%lx", dev->base_addr); pcnet32_get_drvinfo()
734 ulong ioaddr = dev->base_addr; /* card base I/O address */ pcnet32_get_link()
787 ulong ioaddr = dev->base_addr; pcnet32_set_ringparam()
874 ulong ioaddr = dev->base_addr; /* card base I/O address */ pcnet32_loopback_test()
1038 ulong ioaddr = dev->base_addr; pcnet32_set_phys_id()
1079 ulong ioaddr = dev->base_addr; pcnet32_suspend()
1336 unsigned long ioaddr = dev->base_addr; pcnet32_poll()
1388 ulong ioaddr = dev->base_addr; pcnet32_get_regs()
1782 dev->base_addr = ioaddr; pcnet32_probe1()
2039 unsigned long ioaddr = dev->base_addr; pcnet32_open()
2369 unsigned long ioaddr = dev->base_addr; pcnet32_restart()
2398 unsigned long ioaddr = dev->base_addr, flags; pcnet32_tx_timeout()
2439 unsigned long ioaddr = dev->base_addr; pcnet32_start_xmit()
2504 ioaddr = dev->base_addr; pcnet32_interrupt()
2566 unsigned long ioaddr = dev->base_addr; pcnet32_close()
2609 unsigned long ioaddr = dev->base_addr; pcnet32_get_stats()
2626 unsigned long ioaddr = dev->base_addr; pcnet32_load_multicast()
2660 unsigned long ioaddr = dev->base_addr, flags; pcnet32_set_multicast_list()
2699 unsigned long ioaddr = dev->base_addr; mdio_read()
2715 unsigned long ioaddr = dev->base_addr; mdio_write()
2797 ulong ioaddr = dev->base_addr; /* card base I/O address */ pcnet32_check_media()
2821 bcr9 = lp->a->read_bcr(dev->base_addr, 9); pcnet32_check_media()
2827 lp->a->write_bcr(dev->base_addr, 9, bcr9); pcnet32_check_media()
2889 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); pcnet32_remove_one()
2971 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); pcnet32_cleanup_module()
/linux-4.4.14/drivers/scsi/
H A DNCR_Q720.c149 __u32 base_addr, mem_size; NCR_Q720_probe() local
189 base_addr = (pos4 & 0x7e) << 20; NCR_Q720_probe()
190 base_addr += (pos4 & 0x80) << 23; NCR_Q720_probe()
192 base_addr += (asr10 & 0x80) << 24; NCR_Q720_probe()
193 base_addr += (asr10 & 0x70) << 23; NCR_Q720_probe()
212 if(!request_mem_region(base_addr, mem_size, "NCR_Q720")) { NCR_Q720_probe()
214 (unsigned long)base_addr, NCR_Q720_probe()
215 (unsigned long)(base_addr + mem_size)); NCR_Q720_probe()
219 if (dma_declare_coherent_memory(dev, base_addr, base_addr, NCR_Q720_probe()
228 mem_base = dma_mark_declared_memory_occupied(dev, base_addr, NCR_Q720_probe()
248 printk(KERN_ERR "NCR_Q720, adapter failed to memory map registers correctly at 0x%lx(0x%x)\n", (unsigned long)base_addr, i); NCR_Q720_probe()
258 printk(KERN_NOTICE "NCR Q720: found in slot %d irq = %d mem base = 0x%lx siops = %d\n", slot, irq, (unsigned long)base_addr, siops); NCR_Q720_probe()
263 p->phys_mem_base = base_addr; NCR_Q720_probe()
285 __u32 siop_p_base = base_addr + NCR_Q720_CHIP_REGISTER_OFFSET NCR_Q720_probe()
315 release_mem_region(base_addr, mem_size); NCR_Q720_probe()
H A D3w-sas.h177 #define TWL_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_STATUS)
178 #define TWL_HOBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPL)
179 #define TWL_HOBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPH)
180 #define TWL_HOBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDB)
181 #define TWL_HOBDBC_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDBC)
182 #define TWL_HIMASK_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIMASK)
183 #define TWL_HISTAT_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HISTAT)
184 #define TWL_HIBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPH)
185 #define TWL_HIBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPL)
186 #define TWL_HIBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBDB)
187 #define TWL_SCRPD3_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_SCRPD3)
358 void __iomem *base_addr; member in struct:TAG_TW_Device_Extension
H A Dsim710.c97 static int sim710_probe_common(struct device *dev, unsigned long base_addr, sim710_probe_common() argument
107 irq, clock, base_addr, scsi_id); sim710_probe_common()
114 if(request_region(base_addr, 64, "sim710") == NULL) { sim710_probe_common()
116 base_addr); sim710_probe_common()
121 hostdata->base = ioport_map(base_addr, 64); sim710_probe_common()
134 host->base = base_addr; sim710_probe_common()
149 release_region(base_addr, 64); sim710_probe_common()
183 unsigned long io_addr = edev->base_addr; sim710_eisa_probe()
H A DNCR_D700.c257 __u32 base_addr, offset_addr; NCR_D700_probe() local
273 base_addr = ((pos3j << 8) | pos3k) & 0xfffffff0; NCR_D700_probe()
287 base_addr = mca_device_transform_ioport(mca_dev, base_addr); NCR_D700_probe()
292 /*outb(BOARD_RESET, base_addr);*/ NCR_D700_probe()
295 (void)inb(base_addr + 0x08); NCR_D700_probe()
297 switch(differential = (inb(base_addr + 0x08) >> 6)) { NCR_D700_probe()
H A D3w-9xxx.h444 #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
445 #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4)
446 #define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8))
447 #define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x20)
448 #define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC)
449 #define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30)
640 u32 __iomem *base_addr; member in struct:TAG_TW_Device_Extension
H A D3w-xxxx.h249 #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
250 #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
251 #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
252 #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
393 u32 base_addr; member in struct:TAG_TW_Device_Extension
/linux-4.4.14/drivers/misc/
H A Dqcom-coincell.c25 u32 base_addr; member in struct:qcom_coincell
47 chgr->base_addr + QCOM_COINCELL_REG_ENABLE, 0); qcom_coincell_chgr_config()
70 chgr->base_addr + QCOM_COINCELL_REG_RSET, i); qcom_coincell_chgr_config()
73 * This is mainly to flag a bad base_addr (reg) from dts. qcom_coincell_chgr_config()
83 chgr->base_addr + QCOM_COINCELL_REG_VSET, j); qcom_coincell_chgr_config()
89 chgr->base_addr + QCOM_COINCELL_REG_ENABLE, qcom_coincell_chgr_config()
109 rc = of_property_read_u32(node, "reg", &chgr.base_addr); qcom_coincell_probe()
/linux-4.4.14/arch/powerpc/include/asm/
H A Ddcr-native.h89 static inline unsigned __mfdcri(int base_addr, int base_data, int reg) __mfdcri() argument
96 mtdcrx(base_addr, reg); __mfdcri()
99 __mtdcr(base_addr, reg); __mfdcri()
106 static inline void __mtdcri(int base_addr, int base_data, int reg, __mtdcri() argument
113 mtdcrx(base_addr, reg); __mtdcri()
116 __mtdcr(base_addr, reg); __mtdcri()
122 static inline void __dcri_clrset(int base_addr, int base_data, int reg, __dcri_clrset() argument
130 mtdcrx(base_addr, reg); __dcri_clrset()
134 __mtdcr(base_addr, reg); __dcri_clrset()
/linux-4.4.14/arch/mips/rb532/
H A Dirq.c51 volatile u32 *base_addr; member in struct:intr_group
63 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
66 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
69 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
72 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
75 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
129 addr = intr_group[group].base_addr; rb532_enable_irq()
147 addr = intr_group[group].base_addr; rb532_disable_irq()
227 addr = intr_group[group].base_addr; plat_irq_dispatch()
/linux-4.4.14/arch/sparc/mm/
H A Dinit_32.c77 unsigned long start_pfn = sp_banks[i].base_addr >> PAGE_SHIFT; calc_highpages()
78 unsigned long end_pfn = (sp_banks[i].base_addr + sp_banks[i].num_bytes) >> PAGE_SHIFT; calc_highpages()
98 last_pfn = (sp_banks[0].base_addr + sp_banks[0].num_bytes) >> PAGE_SHIFT; calc_max_low_pfn()
100 curr_pfn = sp_banks[i].base_addr >> PAGE_SHIFT; calc_max_low_pfn()
108 last_pfn = (sp_banks[i].base_addr + sp_banks[i].num_bytes) >> PAGE_SHIFT; calc_max_low_pfn()
123 end_of_phys_memory = sp_banks[i].base_addr + bootmem_init()
135 sp_banks[i].base_addr = 0xdeadbeef; bootmem_init()
138 sp_banks[i+1].base_addr = 0xdeadbeef; bootmem_init()
198 curr_pfn = sp_banks[i].base_addr >> PAGE_SHIFT; bootmem_init()
202 last_pfn = (sp_banks[i].base_addr + sp_banks[i].num_bytes) >> PAGE_SHIFT; bootmem_init()
216 free_bootmem(sp_banks[i].base_addr, size); bootmem_init()
266 start = sp_banks[i].base_addr; taint_real_pages()
324 unsigned long start_pfn = sp_banks[i].base_addr >> PAGE_SHIFT; mem_init()
325 unsigned long end_pfn = (sp_banks[i].base_addr + sp_banks[i].num_bytes) >> PAGE_SHIFT; mem_init()
/linux-4.4.14/drivers/net/ethernet/ti/
H A Dtlan.h444 static inline u8 tlan_dio_read8(u16 base_addr, u16 internal_addr) tlan_dio_read8() argument
446 outw(internal_addr, base_addr + TLAN_DIO_ADR); tlan_dio_read8()
447 return inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)); tlan_dio_read8()
454 static inline u16 tlan_dio_read16(u16 base_addr, u16 internal_addr) tlan_dio_read16() argument
456 outw(internal_addr, base_addr + TLAN_DIO_ADR); tlan_dio_read16()
457 return inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)); tlan_dio_read16()
464 static inline u32 tlan_dio_read32(u16 base_addr, u16 internal_addr) tlan_dio_read32() argument
466 outw(internal_addr, base_addr + TLAN_DIO_ADR); tlan_dio_read32()
467 return inl(base_addr + TLAN_DIO_DATA); tlan_dio_read32()
474 static inline void tlan_dio_write8(u16 base_addr, u16 internal_addr, u8 data) tlan_dio_write8() argument
476 outw(internal_addr, base_addr + TLAN_DIO_ADR); tlan_dio_write8()
477 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3)); tlan_dio_write8()
484 static inline void tlan_dio_write16(u16 base_addr, u16 internal_addr, u16 data) tlan_dio_write16() argument
486 outw(internal_addr, base_addr + TLAN_DIO_ADR); tlan_dio_write16()
487 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); tlan_dio_write16()
494 static inline void tlan_dio_write32(u16 base_addr, u16 internal_addr, u32 data) tlan_dio_write32() argument
496 outw(internal_addr, base_addr + TLAN_DIO_ADR); tlan_dio_write32()
497 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); tlan_dio_write32()
H A Dtlan.c338 outl(TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD); tlan_stop()
524 dev->base_addr = pci_io_base; tlan_probe1()
541 dev->base_addr = ioaddr; tlan_probe1()
599 (int)dev->base_addr, tlan_probe1()
634 release_region(dev->base_addr, 0x10); tlan_eisa_cleanup()
920 priv->tlan_rev = tlan_dio_read8(dev->base_addr, TLAN_DEF_REVISION); tlan_open()
1108 outl(tail_list_phys, dev->base_addr + TLAN_CH_PARM); tlan_start_tx()
1109 outl(TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD); tlan_start_tx()
1162 host_int = inw(dev->base_addr + TLAN_HOST_INT); tlan_handle_interrupt()
1168 outw(host_int, dev->base_addr + TLAN_HOST_INT); tlan_handle_interrupt()
1173 outl(host_cmd, dev->base_addr + TLAN_HOST_CMD); tlan_handle_interrupt()
1243 tlan_print_dio(dev->base_addr); tlan_get_stats()
1290 tmp = tlan_dio_read8(dev->base_addr, TLAN_NET_CMD); tlan_set_multicast_list()
1291 tlan_dio_write8(dev->base_addr, tlan_set_multicast_list()
1294 tmp = tlan_dio_read8(dev->base_addr, TLAN_NET_CMD); tlan_set_multicast_list()
1295 tlan_dio_write8(dev->base_addr, tlan_set_multicast_list()
1300 tlan_dio_write32(dev->base_addr, TLAN_HASH_1, tlan_set_multicast_list()
1302 tlan_dio_write32(dev->base_addr, TLAN_HASH_2, tlan_set_multicast_list()
1322 tlan_dio_write32(dev->base_addr, TLAN_HASH_1, hash1);
1323 tlan_dio_write32(dev->base_addr, TLAN_HASH_2, hash2);
1419 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM); tlan_handle_tx_eof()
1427 tlan_dio_write8(dev->base_addr, tlan_handle_tx_eof()
1573 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM); tlan_handle_rx_eof()
1579 tlan_dio_write8(dev->base_addr, tlan_handle_rx_eof()
1665 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM); tlan_handle_tx_eoc()
1712 error = inl(dev->base_addr + TLAN_CH_PARM); tlan_handle_status_check()
1715 outl(TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD); tlan_handle_status_check()
1725 net_sts = tlan_dio_read8(dev->base_addr, TLAN_NET_STS); tlan_handle_status_check()
1727 tlan_dio_write8(dev->base_addr, TLAN_NET_STS, net_sts); tlan_handle_status_check()
1790 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM); tlan_handle_rx_eoc()
1874 tlan_dio_write8(dev->base_addr, tlan_timer()
2105 outw(TLAN_GOOD_TX_FRMS, dev->base_addr + TLAN_DIO_ADR); tlan_read_and_clear_stats()
2106 tx_good = inb(dev->base_addr + TLAN_DIO_DATA); tlan_read_and_clear_stats()
2107 tx_good += inb(dev->base_addr + TLAN_DIO_DATA + 1) << 8; tlan_read_and_clear_stats()
2108 tx_good += inb(dev->base_addr + TLAN_DIO_DATA + 2) << 16; tlan_read_and_clear_stats()
2109 tx_under = inb(dev->base_addr + TLAN_DIO_DATA + 3); tlan_read_and_clear_stats()
2111 outw(TLAN_GOOD_RX_FRMS, dev->base_addr + TLAN_DIO_ADR); tlan_read_and_clear_stats()
2112 rx_good = inb(dev->base_addr + TLAN_DIO_DATA); tlan_read_and_clear_stats()
2113 rx_good += inb(dev->base_addr + TLAN_DIO_DATA + 1) << 8; tlan_read_and_clear_stats()
2114 rx_good += inb(dev->base_addr + TLAN_DIO_DATA + 2) << 16; tlan_read_and_clear_stats()
2115 rx_over = inb(dev->base_addr + TLAN_DIO_DATA + 3); tlan_read_and_clear_stats()
2117 outw(TLAN_DEFERRED_TX, dev->base_addr + TLAN_DIO_ADR); tlan_read_and_clear_stats()
2118 def_tx = inb(dev->base_addr + TLAN_DIO_DATA); tlan_read_and_clear_stats()
2119 def_tx += inb(dev->base_addr + TLAN_DIO_DATA + 1) << 8; tlan_read_and_clear_stats()
2120 crc = inb(dev->base_addr + TLAN_DIO_DATA + 2); tlan_read_and_clear_stats()
2121 code = inb(dev->base_addr + TLAN_DIO_DATA + 3); tlan_read_and_clear_stats()
2123 outw(TLAN_MULTICOL_FRMS, dev->base_addr + TLAN_DIO_ADR); tlan_read_and_clear_stats()
2124 multi_col = inb(dev->base_addr + TLAN_DIO_DATA); tlan_read_and_clear_stats()
2125 multi_col += inb(dev->base_addr + TLAN_DIO_DATA + 1) << 8; tlan_read_and_clear_stats()
2126 single_col = inb(dev->base_addr + TLAN_DIO_DATA + 2); tlan_read_and_clear_stats()
2127 single_col += inb(dev->base_addr + TLAN_DIO_DATA + 3) << 8; tlan_read_and_clear_stats()
2129 outw(TLAN_EXCESSCOL_FRMS, dev->base_addr + TLAN_DIO_ADR); tlan_read_and_clear_stats()
2130 excess_col = inb(dev->base_addr + TLAN_DIO_DATA); tlan_read_and_clear_stats()
2131 late_col = inb(dev->base_addr + TLAN_DIO_DATA + 1); tlan_read_and_clear_stats()
2132 loss = inb(dev->base_addr + TLAN_DIO_DATA + 2); tlan_read_and_clear_stats()
2187 data = inl(dev->base_addr + TLAN_HOST_CMD); tlan_reset_adapter()
2189 outl(data, dev->base_addr + TLAN_HOST_CMD); tlan_reset_adapter()
2195 data = inl(dev->base_addr + TLAN_HOST_CMD); tlan_reset_adapter()
2197 outl(data, dev->base_addr + TLAN_HOST_CMD); tlan_reset_adapter()
2202 tlan_dio_write32(dev->base_addr, (u16) i, 0); tlan_reset_adapter()
2207 tlan_dio_write16(dev->base_addr, TLAN_NET_CONFIG, (u16) data); tlan_reset_adapter()
2211 outl(TLAN_HC_LD_TMR | 0x3f, dev->base_addr + TLAN_HOST_CMD); tlan_reset_adapter()
2212 outl(TLAN_HC_LD_THR | 0x9, dev->base_addr + TLAN_HOST_CMD); tlan_reset_adapter()
2216 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR); tlan_reset_adapter()
2217 addr = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO; tlan_reset_adapter()
2224 tlan_dio_write8(dev->base_addr, TLAN_INT_DIS, data8); tlan_reset_adapter()
2232 tlan_dio_write8(dev->base_addr, TLAN_ACOMMIT, 0x0a); tlan_reset_adapter()
2234 tlan_dio_write8(dev->base_addr, TLAN_ACOMMIT, 0x00); tlan_reset_adapter()
2237 tlan_dio_write8(dev->base_addr, TLAN_ACOMMIT, 0x08); tlan_reset_adapter()
2245 tlan_dio_write16(dev->base_addr, TLAN_NET_CONFIG, (u16) data); tlan_reset_adapter()
2276 tlan_dio_write8(dev->base_addr, TLAN_NET_CMD, data); tlan_finish_reset()
2280 tlan_dio_write8(dev->base_addr, TLAN_NET_MASK, data); tlan_finish_reset()
2281 tlan_dio_write16(dev->base_addr, TLAN_MAX_RX, ((1536)+7)&~7); tlan_finish_reset()
2333 sio = tlan_dio_read8(dev->base_addr, TLAN_NET_SIO); tlan_finish_reset()
2335 tlan_dio_write8(dev->base_addr, TLAN_NET_SIO, sio); tlan_finish_reset()
2341 outb((TLAN_HC_INT_ON >> 8), dev->base_addr + TLAN_HOST_CMD + 1); tlan_finish_reset()
2344 dev->base_addr + TLAN_HOST_CMD + 1); tlan_finish_reset()
2345 outl(priv->rx_list_dma, dev->base_addr + TLAN_CH_PARM); tlan_finish_reset()
2346 outl(TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD); tlan_finish_reset()
2347 tlan_dio_write8(dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK); tlan_finish_reset()
2390 tlan_dio_write8(dev->base_addr, tlan_set_mac()
2394 tlan_dio_write8(dev->base_addr, tlan_set_mac()
2528 tlan_mii_sync(dev->base_addr); tlan_phy_power_down()
2534 tlan_mii_sync(dev->base_addr); tlan_phy_power_down()
2555 tlan_mii_sync(dev->base_addr); tlan_phy_power_up()
2558 tlan_mii_sync(dev->base_addr); tlan_phy_power_up()
2580 tlan_mii_sync(dev->base_addr); tlan_phy_reset()
2659 tlan_dio_write16(dev->base_addr, TLAN_NET_CONFIG, data); tlan_phy_start_link()
2785 tlan_dio_write8(dev->base_addr, TLAN_LED_REG, 0); tlan_phy_monitor()
2792 tlan_mii_sync(dev->base_addr); tlan_phy_monitor()
2807 tlan_dio_write8(dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK); tlan_phy_monitor()
2865 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR); tlan_mii_read_reg()
2866 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO; tlan_mii_read_reg()
2871 tlan_mii_sync(dev->base_addr); tlan_mii_read_reg()
2877 tlan_mii_send_data(dev->base_addr, 0x1, 2); /* start (01b) */ tlan_mii_read_reg()
2878 tlan_mii_send_data(dev->base_addr, 0x2, 2); /* read (10b) */ tlan_mii_read_reg()
2879 tlan_mii_send_data(dev->base_addr, phy, 5); /* device # */ tlan_mii_read_reg()
2880 tlan_mii_send_data(dev->base_addr, reg, 5); /* register # */ tlan_mii_read_reg()
3033 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR); tlan_mii_write_reg()
3034 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO; tlan_mii_write_reg()
3039 tlan_mii_sync(dev->base_addr); tlan_mii_write_reg()
3045 tlan_mii_send_data(dev->base_addr, 0x1, 2); /* start (01b) */ tlan_mii_write_reg()
3046 tlan_mii_send_data(dev->base_addr, 0x1, 2); /* write (01b) */ tlan_mii_write_reg()
3047 tlan_mii_send_data(dev->base_addr, phy, 5); /* device # */ tlan_mii_write_reg()
3048 tlan_mii_send_data(dev->base_addr, reg, 5); /* register # */ tlan_mii_write_reg()
3050 tlan_mii_send_data(dev->base_addr, 0x2, 2); /* send ACK */ tlan_mii_write_reg()
3051 tlan_mii_send_data(dev->base_addr, val, 16); /* send data */ tlan_mii_write_reg()
3266 tlan_ee_send_start(dev->base_addr); tlan_ee_read_byte()
3267 err = tlan_ee_send_byte(dev->base_addr, 0xa0, TLAN_EEPROM_ACK); tlan_ee_read_byte()
3272 err = tlan_ee_send_byte(dev->base_addr, ee_addr, TLAN_EEPROM_ACK); tlan_ee_read_byte()
3277 tlan_ee_send_start(dev->base_addr); tlan_ee_read_byte()
3278 err = tlan_ee_send_byte(dev->base_addr, 0xa1, TLAN_EEPROM_ACK); tlan_ee_read_byte()
3283 tlan_ee_receive_byte(dev->base_addr, data, TLAN_EEPROM_STOP); tlan_ee_read_byte()
/linux-4.4.14/drivers/misc/mic/scif/
H A Dscif_map.h38 *dma_handle = *dma_handle + scifdev->base_addr; scif_alloc_coherent()
50 if (scifdev_is_p2p(scifdev) && local > scifdev->base_addr) scif_free_coherent()
51 local = local - scifdev->base_addr; scif_free_coherent()
71 *dma_handle = *dma_handle + scifdev->base_addr; scif_map_single()
84 local = local - scifdev->base_addr; scif_unmap_single()
130 *dma_handle = *dma_handle + scifdev->base_addr; scif_map_page()
/linux-4.4.14/drivers/clocksource/
H A Dcadence_ttc_timer.c73 * @base_addr: Base address of timer
79 void __iomem *base_addr; member in struct:ttc_timer
120 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); ttc_set_interval()
122 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); ttc_set_interval()
124 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); ttc_set_interval()
132 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); ttc_set_interval()
149 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); ttc_clock_event_interrupt()
165 return (cycle_t)readl_relaxed(timer->base_addr + __ttc_clocksource_read()
203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); ttc_shutdown()
205 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); ttc_shutdown()
225 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); ttc_resume()
227 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); ttc_resume()
270 readl_relaxed(ttccs->ttc.base_addr + ttc_rate_change_clocksource_cb()
296 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); ttc_rate_change_clocksource_cb()
306 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); ttc_rate_change_clocksource_cb()
316 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); ttc_rate_change_clocksource_cb()
352 ttccs->ttc.base_addr = base; ttc_setup_clocksource()
364 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); ttc_setup_clocksource()
366 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); ttc_setup_clocksource()
368 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); ttc_setup_clocksource()
430 ttcce->ttc.base_addr = base; ttc_setup_clockevent()
447 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); ttc_setup_clockevent()
449 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); ttc_setup_clockevent()
450 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); ttc_setup_clockevent()
/linux-4.4.14/drivers/parisc/
H A Ddino.c179 void __iomem *base_addr = d->hba.base_addr; dino_cfg_read() local
182 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, dino_cfg_read()
187 __raw_writel(v, base_addr + DINO_PCI_ADDR); dino_cfg_read()
191 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); dino_cfg_read()
193 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); dino_cfg_read()
195 *val = readl(base_addr + DINO_CONFIG_DATA); dino_cfg_read()
214 void __iomem *base_addr = d->hba.base_addr; dino_cfg_write() local
217 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, dino_cfg_write()
222 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); dino_cfg_write()
223 __raw_readl(base_addr + DINO_CONFIG_DATA); dino_cfg_write()
226 __raw_writel(v, base_addr + DINO_PCI_ADDR); dino_cfg_write()
229 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); dino_cfg_write()
231 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); dino_cfg_write()
233 writel(val, base_addr + DINO_CONFIG_DATA); dino_cfg_write()
262 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
264 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
279 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
281 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
307 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); dino_mask_irq()
324 __raw_readl(dino_dev->hba.base_addr+DINO_IPR); dino_unmask_irq()
328 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); dino_unmask_irq()
339 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); dino_unmask_irq()
370 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; dino_isr()
392 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; dino_isr()
397 dino_dev->hba.base_addr, mask); dino_isr()
458 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) dino_card_setup() argument
500 i, res->start, base_addr + DINO_IO_ADDR_EN); dino_card_setup()
501 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); dino_card_setup()
559 dino_card_setup(bus, dino_dev->hba.base_addr); dino_fixup_bus()
658 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); dino_card_init()
661 dino_dev->hba.base_addr+DINO_IO_COMMAND); dino_card_init()
665 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); dino_card_init()
666 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); dino_card_init()
667 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); dino_card_init()
677 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); dino_card_init()
684 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); dino_card_init()
686 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); dino_card_init()
687 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); dino_card_init()
688 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); dino_card_init()
690 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); dino_card_init()
691 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); dino_card_init()
692 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); dino_card_init()
695 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); dino_card_init()
696 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); dino_card_init()
697 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); dino_card_init()
704 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); dino_card_init()
725 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); dino_bridge_init()
832 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); dino_common_init()
838 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); dino_common_init()
854 dino_dev->hba.base_addr); dino_common_init()
953 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096); dino_probe()
H A Dlba_pci.c208 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
211 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
217 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
223 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
229 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
238 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
243 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
248 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
253 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
308 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
311 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
316 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
348 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); lba_rd_cfg()
350 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; lba_rd_cfg()
359 LBA_CFG_RESTORE(d, d->hba.base_addr); lba_rd_cfg()
369 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; elroy_cfg_read()
412 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; lba_wr_cfg()
421 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); lba_wr_cfg()
422 LBA_CFG_RESTORE(d, d->hba.base_addr); lba_wr_cfg()
457 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); elroy_cfg_write()
459 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); elroy_cfg_write()
461 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); elroy_cfg_write()
465 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); elroy_cfg_write()
486 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; mercury_cfg_read()
516 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; mercury_cfg_write()
539 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); mercury_cfg_write()
897 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
955 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1046 lba_len = ~READ_REG32(lba_dev->hba.base_addr lba_pat_resources()
1149 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); lba_legacy_resources()
1231 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); lba_legacy_resources()
1239 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); lba_legacy_resources()
1277 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); lba_legacy_resources()
1285 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); lba_legacy_resources()
1295 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; lba_legacy_resources()
1296 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); lba_legacy_resources()
1325 d->hba.base_addr, lba_hw_init()
1326 READ_REG64(d->hba.base_addr + LBA_STAT_CTL), lba_hw_init()
1327 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), lba_hw_init()
1328 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), lba_hw_init()
1329 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); lba_hw_init()
1331 READ_REG64(d->hba.base_addr + LBA_ARB_MASK), lba_hw_init()
1332 READ_REG64(d->hba.base_addr + LBA_ARB_PRI), lba_hw_init()
1333 READ_REG64(d->hba.base_addr + LBA_ARB_MODE), lba_hw_init()
1334 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); lba_hw_init()
1336 READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); lba_hw_init()
1340 printk(" %Lx", READ_REG64(d->hba.base_addr + i)); lba_hw_init()
1354 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; lba_hw_init()
1359 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); lba_hw_init()
1363 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); lba_hw_init()
1367 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); lba_hw_init()
1368 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); lba_hw_init()
1378 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { lba_hw_init()
1389 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); lba_hw_init()
1499 lba_dev->hba.base_addr = addr; lba_driver_probe()
1641 void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096); lba_set_iregs() local
1650 WRITE_REG32( imask, base_addr + LBA_IMASK); lba_set_iregs()
1651 WRITE_REG32( ibase, base_addr + LBA_IBASE); lba_set_iregs()
1652 iounmap(base_addr); lba_set_iregs()
/linux-4.4.14/arch/powerpc/platforms/pseries/
H A Dhotplug-memory.c111 lmbs[i].base_addr = be64_to_cpu(lmbs[i].base_addr); dlpar_clone_drconf_property()
125 section_nr = pfn_to_section_nr(PFN_DOWN(lmb->base_addr)); lmb_to_memblock()
203 phys_addr = lmb->base_addr; lmb_is_removable()
238 nid = memory_add_physaddr_to_nid(lmb->base_addr); dlpar_remove_lmb()
240 remove_memory(nid, lmb->base_addr, block_sz); dlpar_remove_lmb()
243 memblock_remove(lmb->base_addr, block_sz); dlpar_remove_lmb()
313 lmbs[i].base_addr); dlpar_memory_remove_by_count()
350 lmbs[i].base_addr); dlpar_memory_remove_by_index()
352 pr_info("Memory at %llx was hot-removed\n", lmbs[i].base_addr); dlpar_memory_remove_by_index()
403 nid = memory_add_physaddr_to_nid(lmb->base_addr); dlpar_add_lmb()
406 rc = add_memory(nid, lmb->base_addr, block_sz); dlpar_add_lmb()
413 rc = memblock_add(lmb->base_addr, block_sz); dlpar_add_lmb()
415 remove_memory(nid, lmb->base_addr, block_sz); dlpar_add_lmb()
422 remove_memory(nid, lmb->base_addr, block_sz); dlpar_add_lmb()
430 remove_memory(nid, lmb->base_addr, block_sz); dlpar_add_lmb()
497 lmbs[i].base_addr, lmbs[i].drc_index); dlpar_memory_add_by_count()
534 lmbs[i].base_addr, drc_index); dlpar_memory_add_by_index()
554 lmbs[i].base_addr = cpu_to_be64(lmbs[i].base_addr); dlpar_update_drconf_property()
689 be64_to_cpu(old_drmem[i].base_addr), pseries_update_drconf_memory()
696 rc = memblock_add(be64_to_cpu(old_drmem[i].base_addr), pseries_update_drconf_memory()
/linux-4.4.14/drivers/net/arcnet/
H A Dcom90io.c73 int ioaddr = dev->base_addr; get_buffer_byte()
85 int ioaddr = dev->base_addr; put_buffer_byte()
98 int ioaddr = dev->base_addr; get_whole_buffer()
114 int ioaddr = dev->base_addr; put_whole_buffer()
132 int ioaddr = dev->base_addr, status; com90io_probe()
224 int ioaddr = dev->base_addr; com90io_found()
234 if (!request_region(dev->base_addr, ARCNET_TOTAL_SIZE, com90io_found()
262 release_region(dev->base_addr, ARCNET_TOTAL_SIZE); com90io_found()
267 dev->dev_addr[0], dev->base_addr, dev->irq); com90io_found()
282 short ioaddr = dev->base_addr; com90io_reset()
313 short ioaddr = dev->base_addr; com90io_command()
320 short ioaddr = dev->base_addr; com90io_status()
327 short ioaddr = dev->base_addr; com90io_setmask()
389 dev->base_addr = io; com90io_init()
408 int ioaddr = dev->base_addr; com90io_exit()
419 release_region(dev->base_addr, ARCNET_TOTAL_SIZE); com90io_exit()
H A Dcom20020.c65 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; com20020_copy_from_card()
80 int ioaddr = dev->base_addr, ofs = 512 * bufnum + offset; com20020_copy_to_card()
94 int ioaddr = dev->base_addr, status; com20020_check()
156 int ioaddr = dev->base_addr; com20020_set_hwaddr()
169 int ioaddr = dev->base_addr; com20020_netdev_open()
180 int ioaddr = dev->base_addr; com20020_netdev_close()
206 int ioaddr = dev->base_addr; com20020_found()
249 dev->base_addr = ioaddr; com20020_found()
252 lp->card_name, dev->dev_addr[0], dev->base_addr, dev->irq); com20020_found()
287 u_int ioaddr = dev->base_addr; com20020_reset()
336 u_int ioaddr = dev->base_addr; com20020_setmask()
344 u_int ioaddr = dev->base_addr; com20020_command()
351 u_int ioaddr = dev->base_addr; com20020_status()
360 int ioaddr = dev->base_addr; com20020_close()
377 int ioaddr = dev->base_addr; com20020_set_mc_list()
H A Dcom20020-isa.c60 ioaddr = dev->base_addr; com20020isa_probe()
165 dev->base_addr = io; com20020_init()
184 release_region(my_dev->base_addr, ARCNET_TOTAL_SIZE); com20020_exit()
H A Dcom20020_cs.c55 int ioaddr = dev->base_addr; regdump()
225 ioaddr = dev->base_addr = link->resource[0]->start; com20020_config()
261 dev->base_addr, dev->irq); com20020_config()
293 int ioaddr = dev->base_addr; com20020_resume()
H A Dcom90xx.c536 dev->base_addr = ioaddr; com90xx_found()
540 dev->base_addr, dev->irq, dev->mem_start, com90xx_found()
563 short ioaddr = dev->base_addr; com90xx_command()
570 short ioaddr = dev->base_addr; com90xx_status()
577 short ioaddr = dev->base_addr; com90xx_setmask()
592 short ioaddr = dev->base_addr; com90xx_reset()
672 release_region(dev->base_addr, ARCNET_TOTAL_SIZE); com90xx_exit()
/linux-4.4.14/drivers/net/hamradio/
H A Dbaycom_ser_fdx.c187 outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */ ser12_set_divisor()
188 outb(divisor, DLL(dev->base_addr)); ser12_set_divisor()
189 outb(divisor >> 8, DLM(dev->base_addr)); ser12_set_divisor()
190 outb(0x01, LCR(dev->base_addr)); /* word length = 6 */ ser12_set_divisor()
196 outb(0x00, THR(dev->base_addr)); ser12_set_divisor()
297 if ((iir = inb(IIR(dev->base_addr))) & 1) ser12_interrupt()
301 msr = inb(MSR(dev->base_addr)); ser12_interrupt()
308 inb(LSR(dev->base_addr)); ser12_interrupt()
312 inb(RBR(dev->base_addr)); ser12_interrupt()
321 outb(0x00, THR(dev->base_addr)); ser12_interrupt()
329 outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr)); ser12_interrupt()
331 outb(0x0d, MCR(dev->base_addr)); /* transmitter off */ ser12_interrupt()
335 msr = inb(MSR(dev->base_addr)); ser12_interrupt()
341 iir = inb(IIR(dev->base_addr)); ser12_interrupt()
420 if (!dev->base_addr || dev->base_addr > 0xffff-SER12_EXTENT || ser12_open()
432 if (!request_region(dev->base_addr, SER12_EXTENT, "baycom_ser_fdx")) { ser12_open()
434 dev->base_addr); ser12_open()
441 if ((u = ser12_check_uart(dev->base_addr)) == c_uart_unknown){ ser12_open()
442 release_region(dev->base_addr, SER12_EXTENT); ser12_open()
445 outb(0, FCR(dev->base_addr)); /* disable FIFOs */ ser12_open()
446 outb(0x0d, MCR(dev->base_addr)); ser12_open()
447 outb(0, IER(dev->base_addr)); ser12_open()
450 release_region(dev->base_addr, SER12_EXTENT); ser12_open()
464 outb(0x0a, IER(dev->base_addr)); ser12_open()
470 outb(0x00, THR(dev->base_addr)); ser12_open()
473 bc_drvname, dev->base_addr, dev->irq, bc->baud, uart_str[u]); ser12_open()
488 outb(0, IER(dev->base_addr)); ser12_close()
489 outb(1, MCR(dev->base_addr)); ser12_close()
491 release_region(dev->base_addr, SER12_EXTENT); ser12_close()
493 bc_drvname, dev->base_addr, dev->irq); ser12_close()
H A Dbaycom_ser_hdx.c174 outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */ ser12_set_divisor()
175 outb(divisor, DLL(dev->base_addr)); ser12_set_divisor()
176 outb(0, DLM(dev->base_addr)); ser12_set_divisor()
177 outb(0x01, LCR(dev->base_addr)); /* word length = 6 */ ser12_set_divisor()
183 outb(0x00, THR(dev->base_addr)); ser12_set_divisor()
209 outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr)); ser12_tx()
225 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ ser12_rx()
355 outb(0x0d, MCR(dev->base_addr)); /* transmitter off */ ser12_rx()
362 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); ser12_rx()
387 if ((iir = inb(IIR(dev->base_addr))) & 1) ser12_interrupt()
393 inb(LSR(dev->base_addr)); ser12_interrupt()
397 inb(RBR(dev->base_addr)); ser12_interrupt()
410 outb(0x00, THR(dev->base_addr)); ser12_interrupt()
414 inb(MSR(dev->base_addr)); ser12_interrupt()
417 iir = inb(IIR(dev->base_addr)); ser12_interrupt()
479 if (!dev->base_addr || dev->base_addr > 0x1000-SER12_EXTENT || ser12_open()
482 if (!request_region(dev->base_addr, SER12_EXTENT, "baycom_ser12")) ser12_open()
486 if ((u = ser12_check_uart(dev->base_addr)) == c_uart_unknown) { ser12_open()
487 release_region(dev->base_addr, SER12_EXTENT); ser12_open()
490 outb(0, FCR(dev->base_addr)); /* disable FIFOs */ ser12_open()
491 outb(0x0d, MCR(dev->base_addr)); ser12_open()
492 outb(0, IER(dev->base_addr)); ser12_open()
495 release_region(dev->base_addr, SER12_EXTENT); ser12_open()
501 outb(2, IER(dev->base_addr)); ser12_open()
509 bc_drvname, dev->base_addr, dev->irq, uart_str[u]); ser12_open()
524 outb(0, IER(dev->base_addr)); ser12_close()
525 outb(1, MCR(dev->base_addr)); ser12_close()
527 release_region(dev->base_addr, SER12_EXTENT); ser12_close()
529 bc_drvname, dev->base_addr, dev->irq); ser12_close()
H A Dyam.c480 outb(0, IER(dev->base_addr)); yam_set_uart()
481 outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr)); yam_set_uart()
482 outb(divisor, DLL(dev->base_addr)); yam_set_uart()
483 outb(0, DLM(dev->base_addr)); yam_set_uart()
484 outb(LCR_BIT8, LCR(dev->base_addr)); yam_set_uart()
485 outb(PTT_OFF, MCR(dev->base_addr)); yam_set_uart()
486 outb(0x00, FCR(dev->base_addr)); yam_set_uart()
490 inb(RBR(dev->base_addr)); yam_set_uart()
491 inb(MSR(dev->base_addr)); yam_set_uart()
495 outb(ENABLE_RTXINT, IER(dev->base_addr)); yam_set_uart()
587 outb(PTT_ON, MCR(dev->base_addr)); ptt_on()
592 outb(PTT_OFF, MCR(dev->base_addr)); ptt_off()
701 outb(b, THR(dev->base_addr)); yam_tx_byte()
712 outb(yp->tx_crcl, THR(dev->base_addr)); yam_tx_byte()
716 outb(chktabh[yp->tx_crch] ^ 0xFF, THR(dev->base_addr)); yam_tx_byte()
759 while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) { yam_interrupt()
760 unsigned char msr = inb(MSR(dev->base_addr)); yam_interrupt()
761 unsigned char lsr = inb(LSR(dev->base_addr)); yam_interrupt()
782 rxb = inb(RBR(dev->base_addr)); yam_interrupt()
870 printk(KERN_INFO "Trying %s at iobase 0x%lx irq %u\n", dev->name, dev->base_addr, dev->irq); yam_open()
874 if (!dev->base_addr || dev->base_addr > 0x1000 - YAM_EXTENT || yam_open()
878 if (!request_region(dev->base_addr, YAM_EXTENT, dev->name)) yam_open()
880 printk(KERN_ERR "%s: cannot 0x%lx busy\n", dev->name, dev->base_addr); yam_open()
883 if ((u = yam_check_uart(dev->base_addr)) == c_uart_unknown) { yam_open()
888 if (fpga_download(dev->base_addr, yp->bitrate)) { yam_open()
893 outb(0, IER(dev->base_addr)); yam_open()
910 inb(LSR(yam_dev->base_addr)); yam_open()
914 printk(KERN_INFO "%s at iobase 0x%lx irq %u uart %s\n", dev->name, dev->base_addr, dev->irq, yam_open()
919 release_region(dev->base_addr, YAM_EXTENT); yam_open()
936 outb(0, IER(dev->base_addr)); yam_close()
937 outb(1, MCR(dev->base_addr)); yam_close()
940 release_region(dev->base_addr, YAM_EXTENT); yam_close()
946 yam_drvname, dev->base_addr, dev->irq); yam_close()
1011 dev->base_addr = yi.cfg.iobase; yam_ioctl()
1125 dev->base_addr = yp->iobase; yam_setup()
H A Dbaycom_par.c318 pp = parport_find_base(dev->base_addr); par96_open()
320 printk(KERN_ERR "baycom_par: parport at 0x%lx unknown\n", dev->base_addr); par96_open()
339 printk(KERN_ERR "baycom_par: cannot register parport at 0x%lx\n", dev->base_addr); par96_open()
354 bc_drvname, dev->base_addr, dev->irq, bc->options); par96_open()
375 bc_drvname, dev->base_addr, dev->irq); par96_close()
H A Dbaycom_epp.c832 struct parport *pp = parport_find_base(dev->base_addr); epp_open()
839 printk(KERN_ERR "%s: parport at 0x%lx unknown\n", bc_drvname, dev->base_addr); epp_open()
962 bc_drvname, dev->base_addr, dev->irq); epp_close()
1037 hi.data.mp.iobase = dev->base_addr; baycom_ioctl()
1049 dev->base_addr = hi.data.mp.iobase; baycom_ioctl()
1119 * If dev->base_addr == 0, probe all likely locations.
1120 * If dev->base_addr == 1, always return failure.
1121 * If dev->base_addr == 2, allocate space for the device and return success
1220 dev->base_addr = iobase[i]; init_baycomepp()
/linux-4.4.14/drivers/usb/host/
H A Dsl811_cs.c89 static int sl811_hc_init(struct device *parent, resource_size_t base_addr, sl811_hc_init() argument
99 resources[1].start = base_addr; sl811_hc_init()
100 resources[1].end = base_addr; sl811_hc_init()
102 resources[2].start = base_addr + 1; sl811_hc_init()
103 resources[2].end = base_addr + 1; sl811_hc_init()
/linux-4.4.14/fs/f2fs/
H A Dxattr.c251 static struct f2fs_xattr_entry *__find_xattr(void *base_addr, int index, __find_xattr() argument
256 list_for_each_xattr(entry, base_addr) { list_for_each_xattr()
404 void *base_addr; f2fs_getxattr() local
415 base_addr = read_all_xattrs(inode, ipage); f2fs_getxattr()
416 if (!base_addr) f2fs_getxattr()
419 entry = __find_xattr(base_addr, index, len, name); f2fs_getxattr()
439 kzfree(base_addr); f2fs_getxattr()
447 void *base_addr; f2fs_listxattr() local
451 base_addr = read_all_xattrs(inode, NULL); f2fs_listxattr()
452 if (!base_addr) f2fs_listxattr()
455 list_for_each_xattr(entry, base_addr) { list_for_each_xattr()
476 kzfree(base_addr);
486 void *base_addr; __f2fs_setxattr() local
506 base_addr = read_all_xattrs(inode, ipage); __f2fs_setxattr()
507 if (!base_addr) __f2fs_setxattr()
511 here = __find_xattr(base_addr, index, len, name); __f2fs_setxattr()
536 free = MIN_OFFSET(inode) - ((char *)last - (char *)base_addr); __f2fs_setxattr()
560 new_hsize = (char *)last - (char *)base_addr; __f2fs_setxattr()
579 error = write_all_xattrs(inode, new_hsize, base_addr, ipage); __f2fs_setxattr()
597 kzfree(base_addr); __f2fs_setxattr()
/linux-4.4.14/arch/m68k/mvme16x/
H A Dconfig.c218 volatile unsigned char *base_addr = (u_char *)CD2401_ADDR; mvme16x_cons_write() local
228 base_addr[CyCAR] = (u_char)port; mvme16x_cons_write()
229 while (base_addr[CyCCR]) mvme16x_cons_write()
231 base_addr[CyCCR] = CyENB_XMTR; mvme16x_cons_write()
233 ier = base_addr[CyIER]; mvme16x_cons_write()
234 base_addr[CyIER] = CyTxMpty; mvme16x_cons_write()
241 if ((base_addr[CyLICR] >> 2) == port) { mvme16x_cons_write()
244 base_addr[CyTEOIR] = CyNOTRANS; mvme16x_cons_write()
248 base_addr[CyTDR] = '\n'; mvme16x_cons_write()
254 base_addr[CyTDR] = '\r'; mvme16x_cons_write()
258 base_addr[CyTDR] = *str++; mvme16x_cons_write()
261 base_addr[CyTEOIR] = 0; mvme16x_cons_write()
264 base_addr[CyTEOIR] = CyNOTRANS; mvme16x_cons_write()
268 base_addr[CyIER] = ier; mvme16x_cons_write()
/linux-4.4.14/drivers/net/ethernet/8390/
H A Dsmc-ultra.c123 #define ULTRA_NIC_OFFSET 16 /* NIC register offset from the base_addr. */
143 int base_addr = dev->base_addr; do_ultra_probe() local
146 if (base_addr > 0x1ff) /* Check a single specified location. */ do_ultra_probe()
147 return ultra_probe1(dev, base_addr); do_ultra_probe()
148 else if (base_addr != 0) /* Don't probe at all. */ do_ultra_probe()
279 dev->base_addr = ioaddr+ULTRA_NIC_OFFSET; ultra_probe1()
361 dev->base_addr = pnp_port_start(idev, 0); ultra_probe_isapnp()
366 dev->base_addr, dev->irq); ultra_probe_isapnp()
367 if (ultra_probe1(dev, dev->base_addr) != 0) { /* Shouldn't happen. */ ultra_probe_isapnp()
370 dev->base_addr); ultra_probe_isapnp()
390 int ioaddr = dev->base_addr - ULTRA_NIC_OFFSET; /* ASIC addr */ ultra_open()
412 outb_p(E8390_NODMA+E8390_PAGE0, dev->base_addr); ultra_open()
413 outb(0xff, dev->base_addr + EN0_ERWCNT); ultra_open()
421 int cmd_port = dev->base_addr - ULTRA_NIC_OFFSET; /* ASIC base addr */ ultra_reset_8390()
447 outb(ULTRA_MEMENB, dev->base_addr - ULTRA_NIC_OFFSET); /* shmem on */ ultra_get_8390_hdr()
456 outb(0x00, dev->base_addr - ULTRA_NIC_OFFSET); /* shmem off */ ultra_get_8390_hdr()
468 outb(ULTRA_MEMENB, dev->base_addr - ULTRA_NIC_OFFSET); ultra_block_input()
480 outb(0x00, dev->base_addr - ULTRA_NIC_OFFSET); /* Disable memory. */ ultra_block_input()
490 outb(ULTRA_MEMENB, dev->base_addr - ULTRA_NIC_OFFSET); ultra_block_output()
494 outb(0x00, dev->base_addr - ULTRA_NIC_OFFSET); /* Disable memory. */ ultra_block_output()
508 int ioaddr = dev->base_addr - ULTRA_NIC_OFFSET; /* ASIC addr */ ultra_pio_get_hdr()
517 int ioaddr = dev->base_addr - ULTRA_NIC_OFFSET; /* ASIC addr */ ultra_pio_input()
530 int ioaddr = dev->base_addr - ULTRA_NIC_OFFSET; /* ASIC addr */ ultra_pio_output()
540 int ioaddr = dev->base_addr - ULTRA_NIC_OFFSET; /* CMDREG */ ultra_close_card()
591 dev->base_addr = io[this_dev]; init_module()
613 release_region(dev->base_addr - ULTRA_NIC_OFFSET, ULTRA_IO_EXTENT); cleanup_card()
H A Dwd.c75 #define WD_NIC_OFFSET 16 /* Offset to the 8390 from the base_addr. */
91 int base_addr = dev->base_addr; do_wd_probe() local
96 if (base_addr > 0x1ff) { /* Check a user specified location. */ do_wd_probe()
97 r = request_region(base_addr, WD_IO_EXTENT, "wd-probe"); do_wd_probe()
100 i = wd_probe1(dev, base_addr); do_wd_probe()
102 release_region(base_addr, WD_IO_EXTENT); do_wd_probe()
107 else if (base_addr != 0) /* Don't probe at all. */ do_wd_probe()
277 dev->base_addr = ioaddr+WD_NIC_OFFSET; wd_probe1()
374 int ioaddr = dev->base_addr - WD_NIC_OFFSET; /* WD_CMDREG */ wd_open()
391 int wd_cmd_port = dev->base_addr - WD_NIC_OFFSET; /* WD_CMDREG */ wd_reset_8390()
415 int wd_cmdreg = dev->base_addr - WD_NIC_OFFSET; /* WD_CMDREG */ wd_get_8390_hdr()
441 int wd_cmdreg = dev->base_addr - WD_NIC_OFFSET; /* WD_CMDREG */ wd_block_input()
465 int wd_cmdreg = dev->base_addr - WD_NIC_OFFSET; /* WD_CMDREG */ wd_block_output()
482 int wd_cmdreg = dev->base_addr - WD_NIC_OFFSET; /* WD_CMDREG */ wd_close()
537 dev->base_addr = io[this_dev]; init_module()
556 release_region(dev->base_addr - WD_NIC_OFFSET, WD_IO_EXTENT); cleanup_card()
H A Dne.c156 #define NE_BASE (dev->base_addr)
213 unsigned long base_addr = dev->base_addr; do_ne_probe() local
219 if (base_addr > 0x1ff) { /* Check a single specified location. */ do_ne_probe()
220 int ret = ne_probe1(dev, base_addr); do_ne_probe()
223 "i/o = %#lx\n", base_addr); do_ne_probe()
226 else if (base_addr != 0) /* Don't probe at all. */ do_ne_probe()
235 for (base_addr = 0; netcard_portlist[base_addr] != 0; base_addr++) { do_ne_probe()
236 int ioaddr = netcard_portlist[base_addr]; do_ne_probe()
270 dev->base_addr = pnp_port_start(idev, 0); ne_probe_isapnp()
275 dev->base_addr, dev->irq); ne_probe_isapnp()
276 if (ne_probe1(dev, dev->base_addr) != 0) { /* Shouldn't happen. */ ne_probe_isapnp()
279 dev->base_addr); ne_probe_isapnp()
342 bad_card = ((dev->base_addr != 0) && (dev->mem_end == BAD)); ne_probe1()
509 dev->base_addr = ioaddr; ne_probe1()
594 int nic_base = dev->base_addr; ne_get_8390_hdr()
636 int nic_base = dev->base_addr; ne_block_input()
817 dev->base_addr = res->start; ne_drv_probe()
824 dev->base_addr = io[this_dev]; ne_drv_probe()
840 io[this_dev] = dev->base_addr; ne_drv_probe()
862 release_region(dev->base_addr, NE_IO_EXTENT); ne_drv_remove()
992 io[this_dev] = dev->base_addr; ne_probe()
H A Dhydra.c144 dev->base_addr = ioaddr; hydra_init()
209 int nic_base = dev->base_addr; hydra_get_8390_hdr()
225 unsigned long nic_base = dev->base_addr; hydra_block_input()
246 unsigned long nic_base = dev->base_addr; hydra_block_output()
261 release_mem_region(ZTWO_PADDR(dev->base_addr)-HYDRA_NIC_BASE, 0x10000); hydra_remove_one()
H A Dzorro8390.c53 #define NE_BASE (dev->base_addr)
116 int nic_base = dev->base_addr; zorro8390_get_8390_hdr()
159 int nic_base = dev->base_addr; zorro8390_block_input()
267 release_mem_region(ZTWO_PADDR(dev->base_addr), NE_IO_EXTENT * 2); zorro8390_remove_one()
362 dev->base_addr = (unsigned long)ioaddr; zorro8390_init()
H A Daxnet_cs.c192 unsigned int ioaddr = dev->base_addr; get_prom()
300 dev->base_addr = link->resource[0]->start; axnet_config()
318 if (inb(dev->base_addr + AXNET_TEST) != 0) axnet_config()
324 outb(0x10, dev->base_addr + AXNET_GPIO); /* select Internal PHY */ axnet_config()
329 j = mdio_read(dev->base_addr + AXNET_MII_EEP, i, 1); axnet_config()
330 j2 = mdio_read(dev->base_addr + AXNET_MII_EEP, i, 2); axnet_config()
340 j = mdio_read(dev->base_addr + AXNET_MII_EEP, i, 1); axnet_config()
341 j2 = mdio_read(dev->base_addr + AXNET_MII_EEP, i, 2); axnet_config()
360 dev->base_addr, dev->irq, dev->dev_addr); axnet_config()
472 unsigned int nic_base = dev->base_addr; axnet_open()
521 unsigned int nic_base = dev->base_addr; axnet_reset_8390()
555 unsigned int nic_base = dev->base_addr; ei_watchdog()
612 unsigned int mii_addr = dev->base_addr + AXNET_MII_EEP; axnet_ioctl()
632 unsigned int nic_base = dev->base_addr; get_8390_hdr()
650 unsigned int nic_base = dev->base_addr; block_input()
672 unsigned int nic_base = dev->base_addr; block_output()
910 long e8390_base = dev->base_addr; axnet_tx_timeout()
956 long e8390_base = dev->base_addr; axnet_start_xmit()
1096 e8390_base = dev->base_addr; ax_interrupt()
1212 long e8390_base = dev->base_addr; ei_tx_err()
1252 long e8390_base = dev->base_addr; ei_tx_intr()
1336 long e8390_base = dev->base_addr; ei_receive()
1453 long e8390_base = dev->base_addr; ei_rx_overrun()
1518 long ioaddr = dev->base_addr; get_stats()
1566 long e8390_base = dev->base_addr; do_set_multicast_list()
1625 long e8390_base = dev->base_addr; AX88190_init()
1691 long e8390_base = dev->base_addr; NS8390_trigger_send()
H A Dmcf8390.c155 u32 addr = dev->base_addr; mcf8390_reset_8390()
196 u32 addr = dev->base_addr; mcf8390_get_8390_hdr()
231 u32 addr = dev->base_addr; mcf8390_block_input()
261 u32 addr = dev->base_addr; mcf8390_block_output()
325 u32 addr = dev->base_addr; mcf8390_init()
443 dev->base_addr = mem->start; mcf8390_probe()
H A Detherh.c181 addr = (void __iomem *)dev->base_addr + EN0_RCNTHI; etherh_setif()
222 addr = (void __iomem *)dev->base_addr + EN0_RCNTHI; etherh_getifstat()
285 void __iomem *addr = (void __iomem *)dev->base_addr; etherh_reset()
331 addr = (void __iomem *)dev->base_addr; etherh_block_output()
390 addr = (void __iomem *)dev->base_addr; etherh_block_input()
430 addr = (void __iomem *)dev->base_addr; etherh_get_header()
724 dev->base_addr = (unsigned long)eh->memc + data->ns8390_offset; etherh_probe()
H A Dmac8390.c304 dev->base_addr = (ndev->board->slot_addr | mac8390_init()
335 dev->mem_start = dev->base_addr + offset; mac8390_init()
337 dev->base_addr = dev->mem_start + 0x10000; mac8390_init()
352 dev->base_addr = (int)(ndev->board->slot_addr + mac8390_init()
360 dev->base_addr = (int)(ndev->board->slot_addr + mac8390_init()
368 dev->base_addr = (int)(ndev->board->slot_addr + mac8390_init()
378 i = (void *)dev->base_addr; mac8390_init()
H A Dne2k-pci.c157 #define NE_BASE (dev->base_addr)
351 dev->base_addr = ioaddr; ne2k_pci_init_one()
405 long ioaddr = dev->base_addr; set_realtek_fdx()
417 long ioaddr = dev->base_addr; set_holtek_fdx()
484 long nic_base = dev->base_addr; ne2k_pci_get_8390_hdr()
521 long nic_base = dev->base_addr; ne2k_pci_block_input()
675 release_region(dev->base_addr, NE_IO_EXTENT); ne2k_pci_remove_one()
H A Dpcnet_cs.c323 unsigned int ioaddr = dev->base_addr; get_prom()
381 sum += inb_p(dev->base_addr + i); get_dl10019()
385 dev->dev_addr[i] = inb_p(dev->base_addr + 0x14 + i); get_dl10019()
386 i = inb(dev->base_addr + 0x1f); get_dl10019()
399 unsigned int ioaddr = dev->base_addr; get_ax88190()
523 dev->base_addr = link->resource[0]->start; pcnet_try_config()
571 " address for io base %#3lx\n", dev->base_addr); pcnet_config()
619 u_char id = inb(dev->base_addr + 0x1a); pcnet_config()
627 pr_cont("io %#3lx, irq %d,", dev->base_addr, dev->irq); pcnet_config()
838 unsigned int nic_base = dev->base_addr; set_misc_reg()
877 unsigned int mii_addr = dev->base_addr + DLINK_GPIO; mii_phy_probe()
903 unsigned int nic_base = dev->base_addr; pcnet_open()
955 unsigned int nic_base = dev->base_addr; pcnet_reset_8390()
1014 unsigned int nic_base = dev->base_addr; ei_watchdog()
1059 write_asic(dev->base_addr, 4, (p & 0x140) ? DL19FDUPLX : 0); ei_watchdog()
1103 unsigned int mii_addr = dev->base_addr + DLINK_GPIO; ei_ioctl()
1127 unsigned int nic_base = dev->base_addr; dma_get_8390_hdr()
1158 unsigned int nic_base = dev->base_addr; dma_block_input()
1213 unsigned int nic_base = dev->base_addr; dma_block_output()
H A Dapne.c55 #define NE_BASE (dev->base_addr)
320 dev->base_addr = ioaddr; apne_probe1()
391 int nic_base = dev->base_addr; apne_get_8390_hdr()
437 int nic_base = dev->base_addr; apne_block_input()
H A Dlib8390.c256 unsigned long e8390_base = dev->base_addr; __ei_tx_timeout()
303 unsigned long e8390_base = dev->base_addr; __ei_start_xmit()
428 unsigned long e8390_base = dev->base_addr; __ei_interrupt()
533 unsigned long e8390_base = dev->base_addr; ei_tx_err()
579 unsigned long e8390_base = dev->base_addr; ei_tx_intr()
655 unsigned long e8390_base = dev->base_addr; ei_receive()
784 unsigned long e8390_base = dev->base_addr; ei_rx_overrun()
852 unsigned long ioaddr = dev->base_addr; __ei_get_stats()
899 unsigned long e8390_base = dev->base_addr; do_set_multicast_list()
1008 unsigned long e8390_base = dev->base_addr; __NS8390_init()
1071 unsigned long e8390_base = dev->base_addr; NS8390_trigger_send()
/linux-4.4.14/drivers/net/can/sja1000/
H A Dems_pcmcia.c41 void __iomem *base_addr; member in struct:ems_pcmcia_card
98 if (readw(card->base_addr) != 0xAA55) ems_pcmcia_interrupt()
158 writeb(EMS_CMD_UMAP, card->base_addr); ems_pcmcia_del_card()
159 iounmap(card->base_addr); ems_pcmcia_del_card()
184 card->base_addr = ioremap(base, EMS_PCMCIA_MEM_SIZE); ems_pcmcia_add_card()
185 if (!card->base_addr) { ems_pcmcia_add_card()
191 if (readw(card->base_addr) != 0xAA55) { ems_pcmcia_add_card()
197 writeb(EMS_CMD_RESET, card->base_addr); ems_pcmcia_add_card()
200 writeb(EMS_CMD_MAP, card->base_addr); ems_pcmcia_add_card()
218 priv->reg_base = card->base_addr + EMS_PCMCIA_CAN_BASE_OFFSET + ems_pcmcia_add_card()
H A Dkvaser_pci.c153 static int number_of_sja1000_chip(void __iomem *base_addr) number_of_sja1000_chip() argument
160 iowrite8(MOD_RM, base_addr + number_of_sja1000_chip()
162 status = ioread8(base_addr + number_of_sja1000_chip()
212 void __iomem *base_addr) kvaser_pci_add_chan()
253 priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES; kvaser_pci_add_chan()
298 void __iomem *base_addr = NULL; kvaser_pci_init_one() local
328 base_addr = pci_iomap(pdev, 1, PCI_PORT_SIZE); kvaser_pci_init_one()
329 if (base_addr == NULL) { kvaser_pci_init_one()
334 no_channels = number_of_sja1000_chip(base_addr); kvaser_pci_init_one()
343 base_addr); kvaser_pci_init_one()
365 if (base_addr != NULL) kvaser_pci_init_one()
366 pci_iounmap(pdev, base_addr); kvaser_pci_init_one()
208 kvaser_pci_add_chan(struct pci_dev *pdev, int channel, struct net_device **master_dev, void __iomem *conf_addr, void __iomem *res_addr, void __iomem *base_addr) kvaser_pci_add_chan() argument
H A Dems_pci.c50 void __iomem *base_addr; member in struct:ems_pci_card
120 return readb(card->base_addr + (port * 4)); ems_pci_v1_readb()
200 if (card->base_addr != NULL) ems_pci_del_card()
201 pci_iounmap(card->pci_dev, card->base_addr); ems_pci_del_card()
214 writeb(0, card->base_addr); ems_pci_card_reset()
268 card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE); ems_pci_add_card()
269 if (card->base_addr == NULL) { ems_pci_add_card()
307 priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET ems_pci_add_card()
H A Dtscan1.c133 netdev->base_addr = pld_base; tscan1_probe()
185 pld_base = netdev->base_addr; tscan1_remove()
H A Dsja1000_isa.c170 dev->base_addr = mem[idx]; sja1000_isa_probe()
175 dev->base_addr = port[idx]; sja1000_isa_probe()
/linux-4.4.14/drivers/net/ethernet/natsemi/
H A Dxtsonic.c70 (0xffff & *((volatile unsigned int *)dev->base_addr+reg))
73 *((volatile unsigned int *)dev->base_addr+reg) = val
136 unsigned int base_addr = dev->base_addr; sonic_probe1() local
140 if (!request_mem_region(base_addr, 0x100, xtsonic_string)) sonic_probe1()
239 release_region(dev->base_addr, SONIC_MEM_SIZE); sonic_probe1()
271 dev->base_addr = resmem->start; xtsonic_probe()
280 dev->base_addr, dev->dev_addr, dev->irq); xtsonic_probe()
285 release_region(dev->base_addr, SONIC_MEM_SIZE); xtsonic_probe()
307 release_region (dev->base_addr, SONIC_MEM_SIZE); xtsonic_device_remove()
H A Djazzsonic.c55 #define SONIC_READ(reg) (*((volatile unsigned int *)dev->base_addr+reg))
59 *((volatile unsigned int *)dev->base_addr+(reg)) = (val); \
127 if (!request_mem_region(dev->base_addr, SONIC_MEM_SIZE, jazz_sonic_string)) sonic_probe1()
154 dev_name(lp->device), dev->base_addr); sonic_probe1()
213 release_mem_region(dev->base_addr, SONIC_MEM_SIZE); sonic_probe1()
243 dev->base_addr = res->start; jazz_sonic_probe()
257 release_mem_region(dev->base_addr, SONIC_MEM_SIZE); jazz_sonic_probe()
279 release_mem_region(dev->base_addr, SONIC_MEM_SIZE); jazz_sonic_device_remove()
H A Dmacsonic.c69 #define SONIC_READ(reg) (nubus_readw(dev->base_addr + (reg * 4) \
71 #define SONIC_WRITE(reg,val) (nubus_writew(val, dev->base_addr + (reg * 4) \
342 * and dev->base_addr before using SONIC_READ() or SONIC_WRITE() */ mac_onboard_sonic_probe()
343 dev->base_addr = ONBOARD_SONIC_REGISTERS; mac_onboard_sonic_probe()
354 dev_name(lp->device), dev->base_addr); mac_onboard_sonic_probe()
461 unsigned long base_addr, prom_addr; mac_nubus_sonic_probe() local
485 base_addr = ndev->board->slot_addr + DUODOCK_SONIC_REGISTERS; mac_nubus_sonic_probe()
493 base_addr = ndev->board->slot_addr + APPLE_SONIC_REGISTERS; mac_nubus_sonic_probe()
500 base_addr = ndev->board->slot_addr + APPLE_SONIC_REGISTERS; mac_nubus_sonic_probe()
508 base_addr = ndev->board->slot_addr + APPLE_SONIC_REGISTERS; mac_nubus_sonic_probe()
516 base_addr = ndev->board->slot_addr + DAYNA_SONIC_REGISTERS; mac_nubus_sonic_probe()
529 * and dev->base_addr before using SONIC_READ() or SONIC_WRITE() */ mac_nubus_sonic_probe()
530 dev->base_addr = base_addr; mac_nubus_sonic_probe()
/linux-4.4.14/drivers/gpio/
H A Dgpio-zynq.c102 * @base_addr: base address of the GPIO device
109 void __iomem *base_addr; member in struct:zynq_gpio
190 data = readl_relaxed(gpio->base_addr + zynq_gpio_get_value()
230 writel_relaxed(state, gpio->base_addr + reg_offset); zynq_gpio_set_value()
256 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); zynq_gpio_dir_in()
258 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); zynq_gpio_dir_in()
285 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); zynq_gpio_dir_out()
287 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); zynq_gpio_dir_out()
290 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); zynq_gpio_dir_out()
292 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); zynq_gpio_dir_out()
316 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); zynq_gpio_irq_mask()
337 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); zynq_gpio_irq_unmask()
357 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); zynq_gpio_irq_ack()
408 int_type = readl_relaxed(gpio->base_addr + zynq_gpio_set_irq_type()
410 int_pol = readl_relaxed(gpio->base_addr + zynq_gpio_set_irq_type()
412 int_any = readl_relaxed(gpio->base_addr + zynq_gpio_set_irq_type()
447 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); zynq_gpio_set_irq_type()
449 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); zynq_gpio_set_irq_type()
451 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); zynq_gpio_set_irq_type()
539 int_sts = readl_relaxed(gpio->base_addr + zynq_gpio_irqhandler()
541 int_enb = readl_relaxed(gpio->base_addr + zynq_gpio_irqhandler()
687 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res); zynq_gpio_probe()
688 if (IS_ERR(gpio->base_addr)) zynq_gpio_probe()
689 return PTR_ERR(gpio->base_addr); zynq_gpio_probe()
732 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + zynq_gpio_probe()
H A Dgpio-sch311x.c321 unsigned short base_addr; sch311x_detect() local
353 base_addr = (sch311x_sio_inb(sio_config_port, 0x60) << 8) | sch311x_detect()
355 if (!base_addr) { sch311x_detect()
360 *addr = base_addr; sch311x_detect()
362 pr_info("Found an SMSC SCH311%d chip at 0x%04x\n", dev_id, base_addr); sch311x_detect()
/linux-4.4.14/drivers/net/wan/
H A Dsbni.c189 * Look for SBNI card which addr stored in dev->base_addr, if nonzero.
196 if( dev->base_addr > 0x1ff && sbni_isa_probe()
197 request_region( dev->base_addr, SBNI_IO_EXTENT, dev->name ) && sbni_isa_probe()
198 sbni_probe1( dev, dev->base_addr, dev->irq ) ) sbni_isa_probe()
203 dev->base_addr); sbni_isa_probe()
248 release_region( dev->base_addr, SBNI_IO_EXTENT ); sbni_probe()
259 if( dev->base_addr ) sbni_init()
264 dev->base_addr = io[ num ], sbni_init()
270 if( dev->base_addr ) sbni_init()
378 dev->base_addr = ioaddr; sbni_probe1()
413 dev->name, dev->base_addr, dev->irq, sbni_probe1()
515 if( inb( dev->base_addr + CSR0 ) & (RC_RDY | TR_RDY) ) sbni_interrupt()
519 (inb( nl->second->base_addr+CSR0 ) & (RC_RDY | TR_RDY)) ) sbni_interrupt()
535 unsigned long ioaddr = dev->base_addr; handle_channel()
593 unsigned long ioaddr = dev->base_addr; recv_frame()
663 outsb( dev->base_addr + DAT, (u8 *)&crc, sizeof crc ); send_frame()
666 outb( inb( dev->base_addr + CSR0 ) & ~TR_REQ, dev->base_addr + CSR0 ); send_frame()
670 outb( inb( dev->base_addr + CSR0 ) | TR_REQ, send_frame()
671 dev->base_addr + CSR0 ); send_frame()
688 outsb( dev->base_addr + DAT, skb->data + nl->outpos, len ); download_data()
693 outb( 0, dev->base_addr + DAT ), download_data()
719 else if( (frame_ok = skip_tail( dev->base_addr, framelen, crc )) upload_data()
732 frame_ok = skip_tail( dev->base_addr, framelen, crc ); upload_data()
822 insb( dev->base_addr + DAT, p, framelen ); append_frame_to_pkt()
861 outb( inb( dev->base_addr + CSR0 ) | TR_REQ, dev->base_addr + CSR0 ); prepare_to_send()
916 outb( SBNI_SIG, dev->base_addr + DAT ); send_frame_header()
919 outb( value, dev->base_addr + DAT ); send_frame_header()
922 outb( value, dev->base_addr + DAT ); send_frame_header()
925 outb( nl->tx_frameno, dev->base_addr + DAT ); send_frame_header()
927 outb( 0, dev->base_addr + DAT ); send_frame_header()
1043 csr0 = inb( dev->base_addr + CSR0 ); sbni_watchdog()
1056 dev->base_addr + CSR1 ); sbni_watchdog()
1057 csr0 = inb( dev->base_addr + CSR0 ); sbni_watchdog()
1062 outb( csr0 | RC_CHK, dev->base_addr + CSR0 ); sbni_watchdog()
1100 outb( *(u_char *)&nl->csr1 | PR_RES, dev->base_addr + CSR1 ); card_start()
1101 outb( EN_INT, dev->base_addr + CSR0 ); card_start()
1124 inb( dev->base_addr + CSR0 ); /* needs for PCI cards */ change_level()
1125 outb( *(u8 *)&nl->csr1, dev->base_addr + CSR1 ); change_level()
1142 inb( dev->base_addr + CSR0 ); timeout_change_level()
1143 outb( *(unsigned char *)&nl->csr1, dev->base_addr + CSR1 ); timeout_change_level()
1166 if( dev->base_addr < 0x400 ) { /* ISA only */ sbni_open()
1170 ((*p)->base_addr == dev->base_addr + 4 || sbni_open()
1171 (*p)->base_addr == dev->base_addr - 4) && sbni_open()
1237 outb( 0, dev->base_addr + CSR0 ); sbni_close()
1345 outb( *(u8 *)&nl->csr1 | PR_RES, dev->base_addr + CSR1 ); sbni_ioctl()
1497 release_region( dev->base_addr, SBNI_IO_EXTENT ); init_module()
1515 release_region(dev->base_addr, SBNI_IO_EXTENT); cleanup_module()
H A Dsdla.c80 #define SDLA_WINDOW(dev,addr) outb((((addr) >> 13) & 0x1F), (dev)->base_addr + SDLA_REG_Z80_WINDOW)
193 outb(SDLA_S502A_HALT, dev->base_addr + SDLA_REG_CONTROL); sdla_stop()
197 outb(SDLA_HALT, dev->base_addr + SDLA_REG_Z80_CONTROL); sdla_stop()
198 outb(SDLA_S502E_ENABLE, dev->base_addr + SDLA_REG_CONTROL); sdla_stop()
203 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_stop()
207 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_stop()
220 outb(SDLA_S502A_NMI, dev->base_addr + SDLA_REG_CONTROL); sdla_start()
221 outb(SDLA_S502A_START, dev->base_addr + SDLA_REG_CONTROL); sdla_start()
225 outb(SDLA_S502E_CPUEN, dev->base_addr + SDLA_REG_Z80_CONTROL); sdla_start()
226 outb(0x00, dev->base_addr + SDLA_REG_CONTROL); sdla_start()
231 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_start()
235 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_start()
919 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_isr()
921 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_isr()
979 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_close()
988 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_close()
1050 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_open()
1052 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_open()
1064 outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); sdla_open()
1346 if (valid_port[i] == map->base_addr) sdla_set_config()
1352 if (!request_region(map->base_addr, SDLA_IO_EXTENTS, dev->name)){ sdla_set_config()
1353 pr_warn("io-port 0x%04lx in use\n", dev->base_addr); sdla_set_config()
1356 base = map->base_addr; sdla_set_config()
1579 dev->base_addr = base; sdla_set_config()
1653 release_region(sdla->base_addr, SDLA_IO_EXTENTS); exit_sdla()
H A Ddscc4.c239 void __iomem *base_addr; member in struct:dscc4_dev_priv
401 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset); scc_patchl()
412 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset); scc_writel()
423 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); scc_readl_star()
424 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); scc_readl_star()
432 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); dscc4_do_tx()
434 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); dscc4_do_tx()
442 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); dscc4_rx_update()
453 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda; dscc4_tx_quiescent()
564 void __iomem *ioaddr = dscc4_priv(dev)->base_addr; dscc4_do_action()
612 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
614 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
615 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
616 writel(Action, dpriv->base_addr + GCMDR);
638 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
924 d->base_addr = (unsigned long)ioaddr; dscc4_found1()
932 dpriv->base_addr = ioaddr; dscc4_found1()
1486 ioaddr = root->base_addr; dscc4_irq()
1611 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG); dscc4_tx_irq()
1612 writel(Action, dpriv->base_addr + GCMDR); dscc4_tx_irq()
1642 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id; dscc4_tx_irq()
1805 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id; dscc4_rx_irq()
1975 ioaddr = root->base_addr; dscc4_remove_one()
/linux-4.4.14/drivers/mfd/
H A Dlpc_sch.c98 unsigned short base_addr; lpc_sch_get_io() local
104 base_addr = 0; lpc_sch_get_io()
109 base_addr = (unsigned short)base_addr_cfg; lpc_sch_get_io()
111 if (base_addr == 0) { lpc_sch_get_io()
116 res->start = base_addr; lpc_sch_get_io()
117 res->end = base_addr + size - 1; lpc_sch_get_io()
H A Dhtc-egpio.c34 void __iomem *base_addr; member in struct:egpio_info
54 writew(value, ei->base_addr + (reg << ei->bus_shift)); egpio_writew()
59 return readw(ei->base_addr + (reg << ei->bus_shift)); egpio_readw()
165 ei->base_addr, reg << ei->bus_shift, value); egpio_get()
289 ei->base_addr = devm_ioremap_nocache(&pdev->dev, res->start, egpio_probe()
291 if (!ei->base_addr) egpio_probe()
293 pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr); egpio_probe()
H A Dlpc_ich.c891 u32 base_addr; lpc_ich_init_gpio() local
898 base_addr = base_addr_cfg & 0x0000ff80; lpc_ich_init_gpio()
899 if (!base_addr) { lpc_ich_init_gpio()
906 res->start = base_addr + ACPIBASE_GPE_OFF; lpc_ich_init_gpio()
907 res->end = base_addr + ACPIBASE_GPE_END; lpc_ich_init_gpio()
924 base_addr = base_addr_cfg & 0x0000ff80; lpc_ich_init_gpio()
925 if (!base_addr) { lpc_ich_init_gpio()
933 res->start = base_addr; lpc_ich_init_gpio()
968 u32 base_addr; lpc_ich_init_wdt() local
974 base_addr = base_addr_cfg & 0x0000ff80; lpc_ich_init_wdt()
975 if (!base_addr) { lpc_ich_init_wdt()
982 res->start = base_addr + ACPIBASE_TCO_OFF; lpc_ich_init_wdt()
983 res->end = base_addr + ACPIBASE_TCO_END; lpc_ich_init_wdt()
986 res->start = base_addr + ACPIBASE_SMI_OFF; lpc_ich_init_wdt()
987 res->end = base_addr + ACPIBASE_SMI_END; lpc_ich_init_wdt()
1007 base_addr = base_addr_cfg & 0xffffc000; lpc_ich_init_wdt()
1015 res->start = base_addr + ACPIBASE_GCS_OFF; lpc_ich_init_wdt()
1016 res->end = base_addr + ACPIBASE_GCS_END; lpc_ich_init_wdt()
1020 base_addr = base_addr_cfg & 0xfffffe00; lpc_ich_init_wdt()
1023 res->start = base_addr + ACPIBASE_PMC_OFF; lpc_ich_init_wdt()
1024 res->end = base_addr + ACPIBASE_PMC_END; lpc_ich_init_wdt()
/linux-4.4.14/drivers/scsi/qla2xxx/
H A Dqla_tmpl.h81 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
88 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
95 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
105 uint32_t base_addr; member in struct:qla27xx_fwdt_entry::__packed::__packed
/linux-4.4.14/arch/x86/um/shared/sysdep/
H A Dtls.h12 unsigned int base_addr; member in struct:um_dup_user_desc
/linux-4.4.14/scripts/
H A Ddecode_stacktrace.sh33 local base_addr=${cache[$name]}
35 local base_addr=$(nm "$vmlinux" | grep -i ' t ' | awk "/ $name\$/ {print \$1}" | head -n1)
36 cache["$name"]="$base_addr"
44 expr=${expr/$name/0x$base_addr}
/linux-4.4.14/arch/parisc/include/asm/
H A Dunwind.h47 unsigned long base_addr; member in struct:unwind_table
65 unwind_table_add(const char *name, unsigned long base_addr,
/linux-4.4.14/drivers/net/wireless/hostap/
H A Dhostap_cs.c56 outb(v, dev->base_addr + a); hfa384x_outb_debug()
70 v = inb(dev->base_addr + a); hfa384x_inb_debug()
86 outw(v, dev->base_addr + a); hfa384x_outw_debug()
100 v = inw(dev->base_addr + a); hfa384x_inw_debug()
117 outsw(dev->base_addr + a, buf, wc); hfa384x_outsw_debug()
132 insw(dev->base_addr + a, buf, wc); hfa384x_insw_debug()
145 #define HFA384X_OUTB(v,a) outb((v), dev->base_addr + (a))
146 #define HFA384X_INB(a) inb(dev->base_addr + (a))
147 #define HFA384X_OUTW(v,a) outw((v), dev->base_addr + (a))
148 #define HFA384X_INW(a) inw(dev->base_addr + (a))
149 #define HFA384X_INSW(a, buf, wc) insw(dev->base_addr + (a), buf, wc)
150 #define HFA384X_OUTSW(a, buf, wc) outsw(dev->base_addr + (a), buf, wc)
516 * until dev->base_addr is set below. This protect us from prism2_config()
529 dev->base_addr = link->resource[0]->start; prism2_config()
H A Dhostap_plx.c119 outb(v, dev->base_addr + a); hfa384x_outb_debug()
134 v = inb(dev->base_addr + a); hfa384x_inb_debug()
151 outw(v, dev->base_addr + a); hfa384x_outw_debug()
166 v = inw(dev->base_addr + a); hfa384x_inw_debug()
184 outsw(dev->base_addr + a, buf, wc); hfa384x_outsw_debug()
200 insw(dev->base_addr + a, buf, wc); hfa384x_insw_debug()
213 #define HFA384X_OUTB(v,a) outb((v), dev->base_addr + (a))
214 #define HFA384X_INB(a) inb(dev->base_addr + (a))
215 #define HFA384X_OUTW(v,a) outw((v), dev->base_addr + (a))
216 #define HFA384X_INW(a) inw(dev->base_addr + (a))
217 #define HFA384X_INSW(a, buf, wc) insw(dev->base_addr + (a), buf, wc)
218 #define HFA384X_OUTSW(a, buf, wc) outsw(dev->base_addr + (a), buf, wc)
546 dev->base_addr = pccard_ioaddr; prism2_plx_probe()
/linux-4.4.14/drivers/pci/host/
H A Dpci-xgene-msi.c74 * MSI0IR0 base_addr
75 * MSI0IR1 base_addr + 0x10000
77 * MSI0IR6 base_addr + 0x60000
78 * MSI0IR7 base_addr + 0x70000
79 * MSI1IR0 base_addr + 0x80000
80 * MSI1IR1 base_addr + 0x90000
82 * MSI1IR7 base_addr + 0xF0000
83 * MSI2IR0 base_addr + 0x100000
85 * MSIFIR0 base_addr + 0x780000
86 * MSIFIR1 base_addr + 0x790000
88 * MSIFIR7 base_addr + 0x7F0000
89 * MSIINT0 base_addr + 0x800000
90 * MSIINT1 base_addr + 0x810000
92 * MSIINTF base_addr + 0x8F0000
/linux-4.4.14/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c110 * @base_addr: base address of the Emaclite device
129 void __iomem *base_addr; member in struct:net_local
161 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); xemaclite_enable_interrupts()
163 drvdata->base_addr + XEL_TSR_OFFSET); xemaclite_enable_interrupts()
166 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); xemaclite_enable_interrupts()
169 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); xemaclite_enable_interrupts()
184 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); xemaclite_disable_interrupts()
187 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); xemaclite_disable_interrupts()
189 drvdata->base_addr + XEL_TSR_OFFSET); xemaclite_disable_interrupts()
192 reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET); xemaclite_disable_interrupts()
194 drvdata->base_addr + XEL_RSR_OFFSET); xemaclite_disable_interrupts()
319 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; xemaclite_send_data()
381 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); xemaclite_recv_data()
464 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; xemaclite_update_address()
641 void __iomem *base_addr = lp->base_addr; xemaclite_interrupt() local
645 if ((__raw_readl(base_addr + XEL_RSR_OFFSET) & xemaclite_interrupt()
647 (__raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) xemaclite_interrupt()
653 tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET); xemaclite_interrupt()
658 __raw_writel(tx_status, base_addr + XEL_TSR_OFFSET); xemaclite_interrupt()
664 tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); xemaclite_interrupt()
669 __raw_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + xemaclite_interrupt()
703 while (__raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) & xemaclite_mdio_wait()
739 ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); xemaclite_mdio_read()
742 lp->base_addr + XEL_MDIOADDR_OFFSET); xemaclite_mdio_read()
744 lp->base_addr + XEL_MDIOCTRL_OFFSET); xemaclite_mdio_read()
749 rc = __raw_readl(lp->base_addr + XEL_MDIORD_OFFSET); xemaclite_mdio_read()
786 ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); xemaclite_mdio_write()
789 lp->base_addr + XEL_MDIOADDR_OFFSET); xemaclite_mdio_write()
790 __raw_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); xemaclite_mdio_write()
792 lp->base_addr + XEL_MDIOCTRL_OFFSET); xemaclite_mdio_write()
840 lp->base_addr + XEL_MDIOCTRL_OFFSET); xemaclite_mdio_setup()
1121 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); xemaclite_of_probe()
1122 if (IS_ERR(lp->base_addr)) { xemaclite_of_probe()
1123 rc = PTR_ERR(lp->base_addr); xemaclite_of_probe()
1144 __raw_writel(0, lp->base_addr + XEL_TSR_OFFSET); xemaclite_of_probe()
1145 __raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); xemaclite_of_probe()
1172 (unsigned int __force)lp->base_addr, ndev->irq); xemaclite_of_probe()
/linux-4.4.14/arch/parisc/kernel/
H A Dunwind.c95 unsigned long base_addr, unsigned long gp, unwind_table_init()
103 table->base_addr = base_addr; unwind_table_init()
105 table->start = base_addr + start->region_start; unwind_table_init()
106 table->end = base_addr + end->region_end; unwind_table_init()
117 start->region_start += base_addr; unwind_table_init()
118 start->region_end += base_addr; unwind_table_init()
137 unwind_table_add(const char *name, unsigned long base_addr, unwind_table_add() argument
151 unwind_table_init(table, name, base_addr, gp, start, end); unwind_table_add()
94 unwind_table_init(struct unwind_table *table, const char *name, unsigned long base_addr, unsigned long gp, void *table_start, void *table_end) unwind_table_init() argument
/linux-4.4.14/drivers/net/
H A DSpace.c133 unsigned long base_addr = netdev_boot_base("eth", unit); ethif_probe2() local
135 if (base_addr == 1) ethif_probe2()
138 (void)( probe_list2(unit, m68k_probes, base_addr == 0) && ethif_probe2()
139 probe_list2(unit, isa_probes, base_addr == 0)); ethif_probe2()
H A Dsb1000.c186 dev->base_addr = ioaddr[0]; sb1000_probe_one()
193 "S/N %#8.8x, IRQ %d.\n", dev->name, dev->base_addr, sb1000_probe_one()
241 release_region(dev->base_addr, 16); sb1000_remove_one()
764 ioaddr = dev->base_addr; sb1000_rx()
914 ioaddr[0] = dev->base_addr; sb1000_error_dpc()
939 ioaddr[0] = dev->base_addr; sb1000_open()
1007 ioaddr[0] = dev->base_addr; sb1000_dev_ioctl()
1103 ioaddr[0] = dev->base_addr; sb1000_interrupt()
1156 ioaddr[0] = dev->base_addr; sb1000_close()
/linux-4.4.14/drivers/net/wireless/rt2x00/
H A Drt2800soc.c100 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE); rt2800soc_read_eeprom() local
102 if (!base_addr) rt2800soc_read_eeprom()
105 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE); rt2800soc_read_eeprom()
107 iounmap(base_addr); rt2800soc_read_eeprom()
/linux-4.4.14/arch/x86/include/uapi/asm/
H A Dldt.h22 unsigned int base_addr; member in struct:user_desc
/linux-4.4.14/drivers/w1/masters/
H A Dmatrox_w1.c80 void __iomem *base_addr; member in struct:matrox_device
192 dev->base_addr = dev->virt_addr + MATROX_BASE; matrox_w1_probe()
193 dev->port_index = dev->base_addr + MATROX_PORT_INDEX_OFFSET; matrox_w1_probe()
194 dev->port_data = dev->base_addr + MATROX_PORT_DATA_OFFSET; matrox_w1_probe()
/linux-4.4.14/drivers/platform/x86/
H A Dintel_mid_thermal.c250 * @base_addr: index of free msic ADC channel
256 static int set_up_therm_channel(u16 base_addr) set_up_therm_channel() argument
261 ret = intel_msic_reg_write(base_addr, SKIN_SENSOR0_CODE); set_up_therm_channel()
265 ret = intel_msic_reg_write(base_addr + 1, SKIN_SENSOR1_CODE); set_up_therm_channel()
269 ret = intel_msic_reg_write(base_addr + 2, SYS_SENSOR_CODE); set_up_therm_channel()
275 ret = intel_msic_reg_write(base_addr + 3, set_up_therm_channel()
351 u16 base_addr; mid_initialize_adc() local
374 base_addr = ADC_CHNL_START_ADDR + channel_index; mid_initialize_adc()
378 ret = reset_stopbit(base_addr); mid_initialize_adc()
383 base_addr++; mid_initialize_adc()
387 ret = set_up_therm_channel(base_addr); mid_initialize_adc()
/linux-4.4.14/drivers/crypto/qat/qat_common/
H A Dadf_transport.c125 memcpy(ring->base_addr + ring->tail, msg, adf_send_message()
140 uint32_t *msg = (uint32_t *)(ring->base_addr + ring->head); adf_handle_response()
149 msg = (uint32_t *)(ring->base_addr + ring->head); adf_handle_response()
189 ring->base_addr = dma_alloc_coherent(&GET_DEV(accel_dev), adf_init_ring()
192 if (!ring->base_addr) adf_init_ring()
195 memset(ring->base_addr, 0x7F, ring_size_bytes); adf_init_ring()
196 /* The base_addr has to be aligned to the size of the buffer */ adf_init_ring()
200 ring->base_addr, ring->dma_addr); adf_init_ring()
223 if (ring->base_addr) { adf_cleanup_ring()
224 memset(ring->base_addr, 0x7F, ring_size_bytes); adf_cleanup_ring()
226 ring_size_bytes, ring->base_addr, adf_cleanup_ring()
H A Dadf_transport_debug.c69 return ring->base_addr + adf_ring_start()
81 return ring->base_addr + adf_ring_next()
/linux-4.4.14/drivers/usb/gadget/udc/
H A Ds3c2410_udc.c64 static void __iomem *base_addr; variable
71 return readb(base_addr + reg); udc_read()
76 writeb(value, base_addr + reg); udc_write()
311 writesb(base_addr + fifo, buf, len); s3c2410_udc_write_packet()
375 s3c2410_udc_set_ep0_de_in(base_addr); s3c2410_udc_write_fifo()
392 s3c2410_udc_set_ep0_ipr(base_addr); s3c2410_udc_write_fifo()
413 readsb(fifo + base_addr, buf, len); s3c2410_udc_read_packet()
498 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_read_fifo()
511 s3c2410_udc_clear_ep0_opr(base_addr); s3c2410_udc_read_fifo()
538 readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read); s3c2410_udc_read_fifo_crq()
592 s3c2410_udc_set_ep0_de_in(base_addr); s3c2410_udc_get_status()
617 s3c2410_udc_set_ep0_ss(base_addr); s3c2410_udc_handle_ep0_idle()
636 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_handle_ep0_idle()
645 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_handle_ep0_idle()
657 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_handle_ep0_idle()
664 s3c2410_udc_clear_ep0_opr(base_addr); s3c2410_udc_handle_ep0_idle()
673 s3c2410_udc_clear_ep0_opr(base_addr); s3c2410_udc_handle_ep0_idle()
682 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_handle_ep0_idle()
686 s3c2410_udc_clear_ep0_opr(base_addr); s3c2410_udc_handle_ep0_idle()
695 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_handle_ep0_idle()
699 s3c2410_udc_clear_ep0_opr(base_addr); s3c2410_udc_handle_ep0_idle()
727 s3c2410_udc_set_ep0_ss(base_addr); s3c2410_udc_handle_ep0_idle()
728 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_handle_ep0_idle()
764 s3c2410_udc_clear_ep0_sst(base_addr); s3c2410_udc_handle_ep0()
773 s3c2410_udc_clear_ep0_se(base_addr); s3c2410_udc_handle_ep0()
893 udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); s3c2410_udc_irq()
1351 s3c2410_udc_set_ep0_ss(base_addr); s3c2410_udc_set_halt()
1352 s3c2410_udc_set_ep0_de_out(base_addr); s3c2410_udc_set_halt()
1809 base_addr = ioremap(rsrc_start, rsrc_len); s3c2410_udc_probe()
1810 if (!base_addr) { s3c2410_udc_probe()
1904 iounmap(base_addr); s3c2410_udc_probe()
1938 iounmap(base_addr); s3c2410_udc_remove()
H A Dnet2272.h473 u16 __iomem *base_addr; member in struct:net2272
481 /* Bar0, Bar1 is base_addr both mem-mapped */
491 return dev->base_addr + (reg << dev->base_shift); net2272_reg_addr()
504 u8 tmp = readb(dev->base_addr + REGADDRPTR); net2272_write()
525 u8 tmp = readb(dev->base_addr + REGADDRPTR); net2272_read()
/linux-4.4.14/drivers/spi/
H A Dspi-sun4i.c78 void __iomem *base_addr; member in struct:sun4i_spi
91 return readl(sspi->base_addr + reg); sun4i_spi_read()
96 writel(value, sspi->base_addr + reg); sun4i_spi_write()
113 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); sun4i_spi_drain_fifo()
128 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG); sun4i_spi_fill_fifo()
369 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); sun4i_spi_probe()
370 if (IS_ERR(sspi->base_addr)) { sun4i_spi_probe()
371 ret = PTR_ERR(sspi->base_addr); sun4i_spi_probe()
H A Dspi-sun6i.c83 void __iomem *base_addr; member in struct:sun6i_spi
97 return readl(sspi->base_addr + reg); sun6i_spi_read()
102 writel(value, sspi->base_addr + reg); sun6i_spi_write()
119 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); sun6i_spi_drain_fifo()
134 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); sun6i_spi_fill_fifo()
368 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); sun6i_spi_probe()
369 if (IS_ERR(sspi->base_addr)) { sun6i_spi_probe()
370 ret = PTR_ERR(sspi->base_addr); sun6i_spi_probe()
/linux-4.4.14/drivers/nfc/s3fwrn5/
H A Dfirmware.c194 u32 base_addr, const void *data) s3fwrn5_fw_update_sector()
203 args.base_address = base_addr; s3fwrn5_fw_update_sector()
336 struct s3fwrn5_fw_cmd_get_bootinfo_rsp *bootinfo, u32 *base_addr) s3fwrn5_fw_get_base_addr()
341 u32 base_addr; s3fwrn5_fw_get_base_addr() member in struct:__anon8741
354 *base_addr = match[i].base_addr; s3fwrn5_fw_get_base_addr()
392 ret = s3fwrn5_fw_get_base_addr(&bootinfo, &fw_info->base_addr); s3fwrn5_fw_setup()
463 fw_info->base_addr + off, fw->image + off); s3fwrn5_fw_download()
193 s3fwrn5_fw_update_sector(struct s3fwrn5_fw_info *fw_info, u32 base_addr, const void *data) s3fwrn5_fw_update_sector() argument
335 s3fwrn5_fw_get_base_addr( struct s3fwrn5_fw_cmd_get_bootinfo_rsp *bootinfo, u32 *base_addr) s3fwrn5_fw_get_base_addr() argument
H A Dfirmware.h96 u32 base_addr; member in struct:s3fwrn5_fw_info
/linux-4.4.14/drivers/video/fbdev/omap2/dss/
H A Dhdmi.h257 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, hdmi_write_reg() argument
260 __raw_writel(val, base_addr + idx); hdmi_write_reg()
263 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) hdmi_read_reg() argument
265 return __raw_readl(base_addr + idx); hdmi_read_reg()
274 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, hdmi_wait_for_bit_change() argument
278 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { hdmi_wait_for_bit_change()
/linux-4.4.14/arch/ia64/sn/kernel/
H A Dbte.c444 u64 *base_addr; bte_init_node() local
447 base_addr = (u64 *) bte_init_node()
449 mynodepda->bte_if[i].bte_base_addr = base_addr; bte_init_node()
450 mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr); bte_init_node()
451 mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr); bte_init_node()
452 mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr); bte_init_node()
453 mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr); bte_init_node()
/linux-4.4.14/drivers/net/ethernet/3com/
H A D3c589_cs.c280 dev->base_addr = link->resource[0]->start; tc589_config()
281 ioaddr = dev->base_addr; tc589_config()
298 dev->base_addr, dev->base_addr+15); tc589_config()
324 (multi ? "562" : "589"), dev->base_addr, dev->irq, tc589_config()
370 outw(cmd, dev->base_addr + EL3_CMD); tc589_wait_for_completion()
372 if (!(inw(dev->base_addr + EL3_STATUS) & 0x1000)) tc589_wait_for_completion()
400 unsigned int ioaddr = dev->base_addr; tc589_set_xcvr()
429 unsigned int ioaddr = dev->base_addr; dump_status()
444 unsigned int ioaddr = dev->base_addr; tc589_reset()
488 "PCMCIA 0x%lx", dev->base_addr); netdev_get_drvinfo()
525 dev->name, inw(dev->base_addr + EL3_STATUS)); el3_open()
532 unsigned int ioaddr = dev->base_addr; el3_tx_timeout()
546 unsigned int ioaddr = dev->base_addr; pop_tx_status()
569 unsigned int ioaddr = dev->base_addr; el3_start_xmit()
611 ioaddr = dev->base_addr; el3_interrupt()
684 unsigned int ioaddr = dev->base_addr; media_check()
791 unsigned int ioaddr = dev->base_addr; update_stats()
822 unsigned int ioaddr = dev->base_addr; el3_rx()
886 unsigned int ioaddr = dev->base_addr; set_rx_mode()
910 unsigned int ioaddr = dev->base_addr; el3_close()
H A D3c574_cs.c340 dev->base_addr = link->resource[0]->start; tc574_config()
342 ioaddr = dev->base_addr; tc574_config()
360 dev->base_addr, dev->base_addr+15); tc574_config()
432 cardname, dev->base_addr, dev->irq, dev->dev_addr); tc574_config()
475 unsigned int ioaddr = dev->base_addr; dump_status()
494 outw(cmd, dev->base_addr + EL3_CMD); tc574_wait_for_completion()
496 if (!(inw(dev->base_addr + EL3_STATUS) & 0x1000)) break; tc574_wait_for_completion()
595 unsigned int ioaddr = dev->base_addr; tc574_reset()
691 dev->name, inw(dev->base_addr + EL3_STATUS)); el3_open()
698 unsigned int ioaddr = dev->base_addr; el3_tx_timeout()
712 unsigned int ioaddr = dev->base_addr; pop_tx_status()
736 unsigned int ioaddr = dev->base_addr; el3_start_xmit()
780 ioaddr = dev->base_addr; el3_interrupt()
867 unsigned int ioaddr = dev->base_addr; media_check()
956 unsigned int ioaddr = dev->base_addr; update_stats()
990 unsigned int ioaddr = dev->base_addr; el3_rx()
1041 unsigned int ioaddr = dev->base_addr; el3_ioctl()
1095 unsigned int ioaddr = dev->base_addr; set_rx_mode()
1118 unsigned int ioaddr = dev->base_addr; el3_close()
H A D3c509.c278 dev->base_addr = ioaddr; el3_dev_fill()
361 int ioaddr = ndev->base_addr, err; el3_isa_resume()
542 dev->base_addr, dev->irq); el3_common_init()
543 release_region(dev->base_addr, EL3_IO_EXTENT); el3_common_init()
548 dev->name, dev->base_addr, if_names[(dev->if_port & 0x03)], el3_common_init()
560 release_region(dev->base_addr, EL3_IO_EXTENT); el3_common_remove()
576 ioaddr = edev->base_addr; el3_eisa_probe()
667 int ioaddr = dev->base_addr; el3_open()
695 int ioaddr = dev->base_addr; el3_tx_timeout()
714 int ioaddr = dev->base_addr; el3_start_xmit()
781 ioaddr = dev->base_addr; el3_interrupt()
890 int ioaddr = dev->base_addr; update_stats()
918 int ioaddr = dev->base_addr; el3_rx()
983 int ioaddr = dev->base_addr; set_multicast_list()
1010 int ioaddr = dev->base_addr; el3_close()
1034 int ioaddr = dev->base_addr; el3_link_ok()
1047 int ioaddr = dev->base_addr; el3_netdev_get_ecmd()
1092 int ioaddr = dev->base_addr; el3_netdev_set_ecmd()
1205 int ioaddr = dev->base_addr; el3_down()
1234 int ioaddr = dev->base_addr; el3_up()
1330 ioaddr = dev->base_addr; el3_suspend()
1354 ioaddr = dev->base_addr; el3_resume()
H A D3c515.c478 outw(TotalReset, dev->base_addr + EL3_CMD); cleanup_card()
479 release_region(dev->base_addr, CORKSCREW_TOTAL_SIZE); cleanup_card()
598 dev->base_addr = ioaddr; corkscrew_setup()
709 int ioaddr = dev->base_addr; corkscrew_open()
877 int ioaddr = dev->base_addr; corkscrew_timer()
968 int ioaddr = dev->base_addr; corkscrew_timeout()
1005 int ioaddr = dev->base_addr; corkscrew_start_xmit()
1135 ioaddr = dev->base_addr; corkscrew_interrupt()
1268 int ioaddr = dev->base_addr; corkscrew_rx()
1334 int ioaddr = dev->base_addr; boomerang_rx()
1417 int ioaddr = dev->base_addr; corkscrew_close()
1475 update_stats(dev->base_addr, dev); corkscrew_get_stats()
1523 int ioaddr = dev->base_addr; set_rx_mode()
1545 dev->base_addr); netdev_get_drvinfo()
/linux-4.4.14/drivers/net/wireless/
H A Dwl3501_cs.c189 wl3501_outb(page, this->base_addr + WL3501_NIC_BSS); wl3501_switch_page()
200 int base_addr = this->base_addr; wl3501_get_flash_mac_addr() local
203 wl3501_outb(WL3501_BSS_FPAGE3, base_addr + WL3501_NIC_BSS); /* BSS */ wl3501_get_flash_mac_addr()
204 wl3501_outb(0x00, base_addr + WL3501_NIC_LMAL); /* LMAL */ wl3501_get_flash_mac_addr()
205 wl3501_outb(0x40, base_addr + WL3501_NIC_LMAH); /* LMAH */ wl3501_get_flash_mac_addr()
209 this->mac_addr[0] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
211 this->mac_addr[1] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
213 this->mac_addr[2] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
215 this->mac_addr[3] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
217 this->mac_addr[4] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
219 this->mac_addr[5] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
221 this->reg_domain = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
223 wl3501_outb(WL3501_BSS_FPAGE0, base_addr + WL3501_NIC_BSS); wl3501_get_flash_mac_addr()
224 wl3501_outb(0x04, base_addr + WL3501_NIC_LMAL); wl3501_get_flash_mac_addr()
225 wl3501_outb(0x40, base_addr + WL3501_NIC_LMAH); wl3501_get_flash_mac_addr()
227 this->version[0] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
229 this->version[1] = inb(base_addr + WL3501_NIC_IODPA); wl3501_get_flash_mac_addr()
252 wl3501_outb(dest & 0xff, this->base_addr + WL3501_NIC_LMAL); wl3501_set_to_wla()
253 wl3501_outb(((dest >> 8) & 0x7f), this->base_addr + WL3501_NIC_LMAH); wl3501_set_to_wla()
256 wl3501_outsb(this->base_addr + WL3501_NIC_IODPA, src, size); wl3501_set_to_wla()
274 wl3501_outb(src & 0xff, this->base_addr + WL3501_NIC_LMAL); wl3501_get_from_wla()
275 wl3501_outb((src >> 8) & 0x7f, this->base_addr + WL3501_NIC_LMAH); wl3501_get_from_wla()
278 insb(this->base_addr + WL3501_NIC_IODPA, dest, size); wl3501_get_from_wla()
718 u8 old = inb(this->base_addr + WL3501_NIC_GCR); wl3501_block_interrupt()
722 wl3501_outb(new, this->base_addr + WL3501_NIC_GCR); wl3501_block_interrupt()
735 u8 old = inb(this->base_addr + WL3501_NIC_GCR); wl3501_unblock_interrupt()
739 wl3501_outb(new, this->base_addr + WL3501_NIC_GCR); wl3501_unblock_interrupt()
1096 wl3501_outb(WL3501_GCR_ECINT, this->base_addr + WL3501_NIC_GCR); wl3501_ack_interrupt()
1133 wl3501_outb_p(WL3501_GCR_CORESET, this->base_addr + WL3501_NIC_GCR); wl3501_reset_board()
1134 wl3501_outb_p(0, this->base_addr + WL3501_NIC_GCR); wl3501_reset_board()
1135 wl3501_outb_p(WL3501_GCR_CORESET, this->base_addr + WL3501_NIC_GCR); wl3501_reset_board()
1141 wl3501_outb_p(0, this->base_addr + WL3501_NIC_GCR); wl3501_reset_board()
1920 dev->base_addr = link->resource[0]->start; wl3501_config()
1929 this->base_addr = dev->base_addr; wl3501_config()
1944 dev->name, this->base_addr, (int)dev->irq, wl3501_config()
/linux-4.4.14/arch/alpha/kernel/
H A Dsmc37c669.c1238 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device()
1255 base_addr.as_uchar = 0; SMC37c669_enable_device()
1256 base_addr.by_field.addr9_3 = local_config[ func ].port1 >> 3; SMC37c669_enable_device()
1260 base_addr.as_uchar SMC37c669_enable_device()
1267 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device()
1284 base_addr.as_uchar = 0; SMC37c669_enable_device()
1285 base_addr.by_field.addr9_3 = local_config[ func ].port1 >> 3; SMC37c669_enable_device()
1289 base_addr.as_uchar SMC37c669_enable_device()
1296 SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device()
1332 base_addr.as_uchar = 0; SMC37c669_enable_device()
1333 base_addr.by_field.addr9_2 = local_config[ func ].port1 >> 2; SMC37c669_enable_device()
1337 base_addr.as_uchar SMC37c669_enable_device()
1344 SMC37c669_FDC_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device()
1380 base_addr.as_uchar = 0; SMC37c669_enable_device()
1381 base_addr.by_field.addr9_4 = local_config[ func ].port1 >> 4; SMC37c669_enable_device()
1385 base_addr.as_uchar SMC37c669_enable_device()
1468 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device()
1482 base_addr.as_uchar = 0; SMC37c669_disable_device()
1485 base_addr.as_uchar SMC37c669_disable_device()
1492 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device()
1506 base_addr.as_uchar = 0; SMC37c669_disable_device()
1510 base_addr.as_uchar SMC37c669_disable_device()
1517 SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device()
1547 base_addr.as_uchar = 0; SMC37c669_disable_device()
1551 base_addr.as_uchar SMC37c669_disable_device()
1558 SMC37c669_FDC_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device()
1588 base_addr.as_uchar = 0; SMC37c669_disable_device()
1592 base_addr.as_uchar SMC37c669_disable_device()
1742 unsigned char base_addr = 0; SMC37c669_is_device_enabled()
1752 base_addr = SMC37c669_is_device_enabled()
1757 base_addr = SMC37c669_is_device_enabled()
1762 base_addr = SMC37c669_is_device_enabled()
1767 base_addr = SMC37c669_is_device_enabled()
1772 base_addr = SMC37c669_is_device_enabled()
1778 ** If we have a valid device, check base_addr<7:6> to see if the SMC37c669_is_device_enabled()
1781 if ( ( dev_ok ) && ( ( base_addr & 0xC0 ) != 0 ) ) { SMC37c669_is_device_enabled()
1236 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device() local
1265 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device() local
1294 SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device() local
1342 SMC37c669_FDC_BASE_ADDRESS_REGISTER base_addr; SMC37c669_enable_device() local
1465 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device() local
1489 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device() local
1514 SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device() local
1555 SMC37c669_FDC_BASE_ADDRESS_REGISTER base_addr; SMC37c669_disable_device() local
1737 unsigned char base_addr = 0; SMC37c669_is_device_enabled() local
/linux-4.4.14/drivers/net/appletalk/
H A Dcops.c203 release_region(dev->base_addr, COPS_IO_EXTENT); cleanup_card()
208 * If dev->base_addr == 0, probe all likely locations.
209 * If dev->base_addr in [1..0x1ff], always return failure.
216 int base_addr; cops_probe() local
227 base_addr = dev->base_addr; cops_probe()
229 base_addr = dev->base_addr = io; cops_probe()
232 if (base_addr > 0x1ff) { /* Check a single specified location. */ cops_probe()
233 err = cops_probe1(dev, base_addr); cops_probe()
234 } else if (base_addr != 0) { /* Don't probe at all. */ cops_probe()
334 dev->base_addr = ioaddr; cops_probe1()
486 int ioaddr=dev->base_addr; cops_reset()
515 int ioaddr=dev->base_addr; cops_load()
606 int ioaddr = dev->base_addr; cops_nodeid()
688 ioaddr = dev->base_addr; cops_poll()
714 ioaddr = dev->base_addr; cops_interrupt()
751 int ioaddr = dev->base_addr; cops_rx()
854 int ioaddr = dev->base_addr; cops_timeout()
877 int ioaddr = dev->base_addr; cops_send_packet()
H A Dltpc.c344 if ( c != inb_p(dev->base_addr+6) ) return 0; wait_timeout()
372 int base = dev->base_addr; handlefc()
395 int base = dev->base_addr; handlefd()
419 int base = dev->base_addr; handlewrite()
447 int base = dev->base_addr; handleread()
469 int base = dev->base_addr; handlecommand()
505 int base = dev->base_addr; idle()
553 inb_p(dev->base_addr+1); idle()
554 inb_p(dev->base_addr+0); idle()
561 inb_p(dev->base_addr+1); idle()
562 inb_p(dev->base_addr+0); idle()
796 inb_p(dev->base_addr+6); /* disable further interrupts from board */ ltpc_interrupt()
1126 dev->base_addr = io; ltpc_probe()
1273 if (dev_ltpc->base_addr) ltpc_cleanup()
1274 release_region(dev_ltpc->base_addr,8); ltpc_cleanup()
/linux-4.4.14/drivers/net/ethernet/i825xx/
H A Dlasi_82596.c126 gsc_writel(0, dev->base_addr + PA_CHANNEL_ATTENTION); ca()
145 gsc_writel(a, dev->base_addr + PA_CPU_PORT_L_ACCESS); mpu_port()
147 gsc_writel(b, dev->base_addr + PA_CPU_PORT_L_ACCESS); mpu_port()
175 netdevice->base_addr = dev->hpa.start; lan_init_chip()
178 if (pdc_lan_station_id(netdevice->dev_addr, netdevice->base_addr)) { lan_init_chip()
H A Dsni_82596.c109 netdevice->base_addr = res->start; sni_82596_probe()
127 __FILE__, netdevice->base_addr); sni_82596_probe()
H A D82596.c379 ((struct i596_reg *) dev->base_addr)->ca = 1; CA()
386 i = *(volatile u32 *) (dev->base_addr); CA()
396 struct i596_reg *p = (struct i596_reg *) (dev->base_addr); MPU_PORT()
405 *(volatile u32 *) dev->base_addr = v; MPU_PORT()
407 *(volatile u32 *) dev->base_addr = v; MPU_PORT()
939 int ioaddr = dev->base_addr; i596_add_cmd()
1024 int ioaddr = dev->base_addr; i596_tx_timeout()
1147 dev->base_addr = io; i82596_probe()
1159 dev->base_addr = MVME_I596_BASE; i82596_probe()
1174 dev->base_addr = BVME_I596_BASE; i82596_probe()
1189 DEB(DEB_PROBE,printk(KERN_INFO "%s: 82596 at %#3lx,", dev->name, dev->base_addr)); i82596_probe()
1261 ioaddr = dev->base_addr; i596_interrupt()
H A Dsun3_82586.c58 #define sun3_attn586() {*(volatile unsigned char *)(dev->base_addr) |= IEOB_ATTEN; *(volatile unsigned char *)(dev->base_addr) &= ~IEOB_ATTEN;}
59 #define sun3_reset586() {*(volatile unsigned char *)(dev->base_addr) = 0; udelay(100); *(volatile unsigned char *)(dev->base_addr) = IEOB_NORSET;}
60 #define sun3_disint() {*(volatile unsigned char *)(dev->base_addr) &= ~IEOB_IENAB;}
61 #define sun3_enaint() {*(volatile unsigned char *)(dev->base_addr) |= IEOB_IENAB;}
62 #define sun3_active() {*(volatile unsigned char *)(dev->base_addr) |= (IEOB_IENAB|IEOB_ONAIR|IEOB_NORSET);}
313 dev->base_addr = ioaddr; sun3_82586_probe()
354 printk("%s: SUN3 Intel 82586 found at %lx, ",dev->name,dev->base_addr); sun3_82586_probe1()
/linux-4.4.14/drivers/tty/
H A Dcyclades.c299 cy_writeb(port->u.cyy.base_addr + (reg << card->bus_index), val); cyy_writeb()
306 return readb(port->u.cyy.base_addr + (reg << card->bus_index)); cyy_readb()
326 struct FIRM_ID __iomem *fw_id = card->base_addr + ID_ADDRESS; cyz_is_loaded()
361 static int __cyy_issue_cmd(void __iomem *base_addr, u8 cmd, int index) __cyy_issue_cmd() argument
363 void __iomem *ccr = base_addr + (CyCCR << index); __cyy_issue_cmd()
385 return __cyy_issue_cmd(port->u.cyy.base_addr, cmd, cyy_issue_cmd()
441 void __iomem *base_addr) cyy_chip_rx()
452 save_xir = readb(base_addr + (CyRIR << index)); cyy_chip_rx()
569 void __iomem *base_addr) cyy_chip_tx()
584 save_xir = readb(base_addr + (CyTIR << index)); cyy_chip_tx()
586 save_car = readb(base_addr + (CyCAR << index)); cyy_chip_tx()
587 cy_writeb(base_addr + (CyCAR << index), save_xir); cyy_chip_tx()
682 void __iomem *base_addr) cyy_chip_modem()
690 save_xir = readb(base_addr + (CyMIR << index)); cyy_chip_modem()
762 void __iomem *base_addr, *card_base_addr; cyy_interrupt() local
774 card_base_addr = cinfo->base_addr; cyy_interrupt()
789 base_addr = cinfo->base_addr + cyy_interrupt()
792 while ((status = readb(base_addr + cyy_interrupt()
804 cyy_chip_rx(cinfo, chip, base_addr); cyy_interrupt()
806 cyy_chip_tx(cinfo, chip, base_addr); cyy_interrupt()
808 cyy_chip_modem(cinfo, chip, base_addr); cyy_interrupt()
967 memcpy_fromio(buf, cinfo->base_addr + cyz_handle_rx()
979 data = readb(cinfo->base_addr + rx_bufaddr + cyz_handle_rx()
1043 cy_writeb(cinfo->base_addr + tx_bufaddr + tx_put, data); cyz_handle_tx()
1056 memcpy_toio((char *)(cinfo->base_addr + tx_bufaddr + tx_put), cyz_handle_tx()
1074 cy_writeb(cinfo->base_addr + tx_bufaddr + tx_put, data); cyz_handle_tx()
1323 "base_addr %p\n", card, channel, card->base_addr); cy_startup()
1457 "base_addr %p\n", card, channel, card->base_addr); cy_shutdown()
1518 struct FIRM_ID __iomem *firm_id = cinfo->base_addr + ID_ADDRESS; cy_open()
3101 struct FIRM_ID *firm_id = cinfo->base_addr + ID_ADDRESS; cy_init_card()
3107 zfw_ctrl = cinfo->base_addr + cy_init_card()
3132 info->u.cyy.base_addr = cinfo->base_addr + cy_init_card()
3173 void __iomem *base_addr; cyy_init_card() local
3183 base_addr = cyy_init_card()
3186 if (readb(base_addr + (CyCCR << index)) != 0x00) { cyy_init_card()
3189 chip_number, (unsigned long)base_addr); cyy_init_card()
3194 cy_writeb(base_addr + (CyGFRCR << index), 0); cyy_init_card()
3209 cy_writeb(base_addr + (CyCCR << index), CyCHIP_RESET); cyy_init_card()
3212 if (readb(base_addr + (CyGFRCR << index)) == 0x00) { cyy_init_card()
3215 chip_number, (unsigned long)base_addr); cyy_init_card()
3220 if ((0xf0 & (readb(base_addr + (CyGFRCR << index)))) != cyy_init_card()
3225 chip_number, (unsigned long)base_addr, cyy_init_card()
3226 base_addr[CyGFRCR<<index]); cyy_init_card()
3230 cy_writeb(base_addr + (CyGCR << index), CyCH0_SERIAL); cyy_init_card()
3231 if (readb(base_addr + (CyGFRCR << index)) >= CD1400_REV_J) { cyy_init_card()
3235 cy_writeb(base_addr + (CyPPR << index), CyCLOCK_60_2MS); cyy_init_card()
3238 cy_writeb(base_addr + (CyPPR << index), CyCLOCK_25_5MS); cyy_init_card()
3243 chip_number, (unsigned long)base_addr, cyy_init_card()
3244 readb(base_addr+(CyGFRCR<<index))); cyy_init_card()
3321 if (card->base_addr == NULL) cy_detect_isa()
3344 card->base_addr = cy_isa_address; cy_detect_isa()
3352 card->base_addr = NULL; cy_detect_isa()
3499 static int cyz_load_fw(struct pci_dev *pdev, void __iomem *base_addr, cyz_load_fw() argument
3503 struct FIRM_ID __iomem *fid = base_addr + ID_ADDRESS; cyz_load_fw()
3504 struct CUSTOM_REG __iomem *cust = base_addr; cyz_load_fw()
3520 u32 cntval = readl(base_addr + 0x190); cyz_load_fw()
3523 if (cntval != readl(base_addr + 0x190)) { cyz_load_fw()
3551 base_addr); cyz_load_fw()
3568 for (tmp = base_addr; tmp < base_addr + RAM_SIZE; tmp++) cyz_load_fw()
3573 for (tmp = base_addr; tmp < base_addr + RAM_SIZE; tmp++) cyz_load_fw()
3579 retval = __cyz_load_fw(fw, "Cyclom-Z", mailbox, base_addr, NULL); cyz_load_fw()
3622 pt_zfwctrl = base_addr + readl(&fid->zfwctrl_addr); cyz_load_fw()
3625 base_addr + ID_ADDRESS, readl(&fid->zfwctrl_addr), cyz_load_fw()
3626 base_addr + readl(&fid->zfwctrl_addr)); cyz_load_fw()
3804 if (card->base_addr == NULL) cy_pci_probe()
3847 card->base_addr = addr2; cy_pci_probe()
3890 card->base_addr = NULL; cy_pci_probe()
3910 if (!cy_is_Z(cinfo) && (readb(cinfo->base_addr + CyPLX_VER) & 0x0f) == cy_pci_remove()
3921 iounmap(cinfo->base_addr); cy_pci_remove()
3932 cinfo->base_addr = NULL; cy_pci_remove()
4127 if (card->base_addr) { cy_cleanup_module()
4129 cy_writeb(card->base_addr + Cy_ClrIntr, 0); cy_cleanup_module()
4130 iounmap(card->base_addr); cy_cleanup_module()
440 cyy_chip_rx(struct cyclades_card *cinfo, int chip, void __iomem *base_addr) cyy_chip_rx() argument
568 cyy_chip_tx(struct cyclades_card *cinfo, unsigned int chip, void __iomem *base_addr) cyy_chip_tx() argument
681 cyy_chip_modem(struct cyclades_card *cinfo, int chip, void __iomem *base_addr) cyy_chip_modem() argument
/linux-4.4.14/drivers/net/ethernet/smsc/
H A Dsmc91c92_cs.c436 dev->base_addr = link->resource[0]->start; mhz_mfc_config()
520 unsigned int ioaddr = dev->base_addr; mot_config()
540 unsigned int ioaddr = dev->base_addr; mot_setup()
589 dev->base_addr = link->resource[0]->start; smc_config()
640 dev->base_addr = link->resource[0]->start + 0x10; osi_config()
733 set_bits(0x0300, dev->base_addr-0x10+OSITECH_AUI_PWR); smc91c92_resume()
734 set_bits(0x0300, dev->base_addr-0x10+OSITECH_RESET_ISR); smc91c92_resume()
765 unsigned int ioaddr = dev->base_addr; check_sig()
885 ioaddr = dev->base_addr; smc91c92_config()
924 name, (rev & 0x0f), dev->base_addr, dev->irq, dev->dev_addr); smc91c92_config()
987 unsigned int addr = dev->base_addr + MGMT; mdio_read()
1007 unsigned int addr = dev->base_addr + MGMT; mdio_write()
1033 unsigned int ioaddr = dev->base_addr; smc_dump()
1053 dev->name, dev, inw(dev->base_addr + BANK_SELECT)); smc_open()
1085 unsigned int ioaddr = dev->base_addr; smc_close()
1122 unsigned int ioaddr = dev->base_addr; smc_hardware_send_packet()
1184 unsigned int ioaddr = dev->base_addr; smc_tx_timeout()
1199 unsigned int ioaddr = dev->base_addr; smc_start_xmit()
1268 unsigned int ioaddr = dev->base_addr; smc_tx_err()
1310 unsigned int ioaddr = dev->base_addr; smc_eph_irq()
1353 ioaddr = dev->base_addr; smc_interrupt()
1472 unsigned int ioaddr = dev->base_addr; smc_rx()
1544 unsigned int ioaddr = dev->base_addr; set_rx_mode()
1614 unsigned int ioaddr = dev->base_addr; smc_set_xcvr()
1637 unsigned int ioaddr = dev->base_addr; smc_reset()
1714 unsigned int ioaddr = dev->base_addr; media_check()
1834 unsigned int ioaddr = dev->base_addr; smc_link_ok()
1848 unsigned int ioaddr = dev->base_addr; smc_netdev_get_ecmd()
1870 unsigned int ioaddr = dev->base_addr; smc_netdev_set_ecmd()
1913 unsigned int ioaddr = dev->base_addr; smc_get_settings()
1932 unsigned int ioaddr = dev->base_addr; smc_set_settings()
1951 unsigned int ioaddr = dev->base_addr; smc_get_link()
1968 unsigned int ioaddr = dev->base_addr; smc_nway_reset()
1996 unsigned int ioaddr = dev->base_addr; smc_ioctl()
H A Dsmc9194.c471 unsigned int ioaddr = dev->base_addr; smc_wait_to_send_packet()
587 ioaddr = dev->base_addr; smc_hardware_send_packet()
676 | dev->base_addr == 0, try to find all possible locations
677 | dev->base_addr == 1, return failure code
678 | dev->base_addr == 2, always allocate space, and return success
679 | dev->base_addr == <anything else> this is the address to check
702 io = dev->base_addr; smc_init()
726 release_region(dev->base_addr, SMC_IO_EXTENT); smc_init()
918 dev->base_addr = ioaddr; smc_probe()
1049 int ioaddr = dev->base_addr; smc_open()
1105 smc_reset( dev->base_addr ); smc_timeout()
1106 smc_enable( dev->base_addr ); smc_timeout()
1127 int ioaddr = dev->base_addr; smc_rcv()
1248 int ioaddr = dev->base_addr; smc_tx()
1313 int ioaddr = dev->base_addr; smc_interrupt()
1437 smc_shutdown( dev->base_addr ); smc_close()
1453 short ioaddr = dev->base_addr; smc_set_multicast_list()
1527 release_region(devSMC9194->base_addr, SMC_IO_EXTENT); cleanup_module()
/linux-4.4.14/drivers/net/ethernet/dec/tulip/
H A Dinterrupt.c93 if(((ioread32(tp->base_addr + CSR5)>>17)&0x07) == 4) { tulip_refill_rx()
97 iowrite32(0x01, tp->base_addr + CSR2); tulip_refill_rx()
135 if (ioread32(tp->base_addr + CSR5) == 0xffffffff) { tulip_poll()
140 iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5); tulip_poll()
276 } while ((ioread32(tp->base_addr + CSR5) & RxIntr)); tulip_poll()
301 iowrite32(mit_table[MIT_TABLE], tp->base_addr + CSR11); tulip_poll()
307 iowrite32(0, tp->base_addr + CSR11); tulip_poll()
323 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7); tulip_poll()
493 int csr12 = ioread32(tp->base_addr + CSR12) & 0xff; phy_interrupt()
497 iowrite32(csr12 | 0x02, tp->base_addr + CSR12); phy_interrupt()
504 iowrite32(csr12 & ~0x02, tp->base_addr + CSR12); phy_interrupt()
519 void __iomem *ioaddr = tp->base_addr; tulip_interrupt()
H A Dpnic.c22 void __iomem *ioaddr = tp->base_addr; pnic_do_nway()
55 void __iomem *ioaddr = tp->base_addr; pnic_lnk_change()
91 void __iomem *ioaddr = tp->base_addr; pnic_timer()
H A Dtimer.c22 void __iomem *ioaddr = tp->base_addr; tulip_media_task()
144 void __iomem *ioaddr = tp->base_addr; mxic_timer()
H A Dwinbond-840.c322 void __iomem *base_addr; member in struct:netdev_private
410 np->base_addr = ioaddr; w840_probe1()
570 void __iomem *mdio_addr = np->base_addr + MIICtrl; mdio_read()
600 void __iomem *mdio_addr = np->base_addr + MIICtrl; mdio_write()
632 void __iomem *ioaddr = np->base_addr; netdev_open()
741 void __iomem *ioaddr = np->base_addr; update_csr6()
782 void __iomem *ioaddr = np->base_addr; netdev_timer()
836 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr); init_rxtx_rings()
838 np->base_addr + TxRingPtr); init_rxtx_rings()
872 void __iomem *ioaddr = np->base_addr; init_registers()
930 void __iomem *ioaddr = np->base_addr; tx_timeout()
959 iowrite32(1, np->base_addr+PCIBusCfg); tx_timeout()
1042 iowrite32(0, np->base_addr + TxStartDemand); start_tx()
1117 void __iomem *ioaddr = np->base_addr; intr_handler()
1289 void __iomem *ioaddr = np->base_addr; netdev_error()
1331 void __iomem *ioaddr = np->base_addr; get_stats()
1346 void __iomem *ioaddr = np->base_addr; __set_rx_mode()
1480 void __iomem *ioaddr = np->base_addr; netdev_close()
1541 pci_iounmap(pdev, np->base_addr); w840_remove1()
1575 void __iomem *ioaddr = np->base_addr; w840_suspend()
1622 iowrite32(1, np->base_addr+PCIBusCfg); w840_resume()
1623 ioread32(np->base_addr+PCIBusCfg); w840_resume()
H A D21142.c33 void __iomem *ioaddr = tp->base_addr; t21142_media_task()
114 void __iomem *ioaddr = tp->base_addr; t21142_start_nway()
142 void __iomem *ioaddr = tp->base_addr; t21142_lnk_change()
H A Dpnic2.c83 void __iomem *ioaddr = tp->base_addr; pnic2_timer()
99 void __iomem *ioaddr = tp->base_addr; pnic2_start_nway()
173 void __iomem *ioaddr = tp->base_addr; pnic2_lnk_change()
H A Dde4x5.c1133 dev->base_addr = iobase; de4x5_hw_init()
1295 u_long iobase = dev->base_addr; de4x5_open()
1385 u_long iobase = dev->base_addr; de4x5_sw_reset()
1463 u_long iobase = dev->base_addr; de4x5_queue_pkt()
1546 iobase = dev->base_addr; de4x5_interrupt()
1604 u_long iobase = dev->base_addr; de4x5_rx()
1694 u_long iobase = dev->base_addr; de4x5_tx()
1771 u_long iobase = dev->base_addr; de4x5_txur()
1794 u_long iobase = dev->base_addr; de4x5_rx_ovfc()
1815 u_long iobase = dev->base_addr; de4x5_close()
1851 u_long iobase = dev->base_addr; de4x5_get_stats()
1919 u_long iobase = dev->base_addr; set_multicast_list()
1950 u_long iobase = dev->base_addr; SetMulticastFilter()
2005 iobase = edev->base_addr; de4x5_eisa_probe()
2085 iobase = dev->base_addr; de4x5_eisa_remove()
2322 iobase = dev->base_addr; de4x5_pci_remove()
2362 u_long iobase = dev->base_addr; autoconf_media()
2392 u_long iobase = dev->base_addr; dc21040_autoconf()
2546 u_long iobase = dev->base_addr; dc21041_autoconf()
2750 u_long imr, omr, iobase = dev->base_addr; dc21140m_autoconf()
2932 u_long iobase = dev->base_addr; dc2114x_autoconf()
3261 u_long iobase = dev->base_addr; de4x5_init_connection()
3288 u_long iobase = dev->base_addr; de4x5_reset_phy()
3322 u_long iobase = dev->base_addr; test_media()
3360 u_long iobase = dev->base_addr; test_tp()
3443 u_long iobase = dev->base_addr; test_mii_reg()
3465 u_long iobase = dev->base_addr; is_spd_100()
3489 u_long iobase = dev->base_addr; is_100_up()
3510 u_long iobase = dev->base_addr; is_10_up()
3533 u_long iobase = dev->base_addr; is_anc_capable()
3552 u_long iobase = dev->base_addr; ping_media()
3677 u_long iobase = dev->base_addr; de4x5_save_skbs()
3696 u_long iobase = dev->base_addr; de4x5_rst_desc_ring()
3727 u_long iobase = dev->base_addr; de4x5_cache_state()
3783 u_long iobase = dev->base_addr; test_ans()
3811 u_long iobase = dev->base_addr; de4x5_setup_intr()
3830 u_long iobase = dev->base_addr; reset_init_sia()
4024 u_long iobase = dev->base_addr; get_hw_addr()
4383 u_long iobase = dev->base_addr; srom_exec()
4966 u_long iobase = dev->base_addr; mii_get_phy()
5069 u_long iobase = dev->base_addr; de4x5_switch_mac_port()
5105 u_long iobase = dev->base_addr; gep_wr()
5118 u_long iobase = dev->base_addr; gep_rd()
5133 u_long iobase = dev->base_addr; yawn()
5263 u_long iobase = dev->base_addr; de4x5_dbg_mii()
5360 u_long iobase = dev->base_addr; de4x5_ioctl()
H A Dmedia.c53 void __iomem *ioaddr = tp->base_addr; tulip_mdio_read()
114 void __iomem *ioaddr = tp->base_addr; tulip_mdio_write()
170 void __iomem *ioaddr = tp->base_addr; tulip_select_media()
H A Dtulip.h453 void __iomem *base_addr; member in struct:tulip_private
524 void __iomem *ioaddr = tp->base_addr; tulip_start_rxtx()
532 void __iomem *ioaddr = tp->base_addr; tulip_stop_rxtx()
H A Dtulip_core.c296 void __iomem *ioaddr = tp->base_addr; tulip_up()
542 void __iomem *ioaddr = tp->base_addr; tulip_tx_timeout()
707 iowrite32(0, tp->base_addr + CSR1); tulip_start_xmit()
753 void __iomem *ioaddr = tp->base_addr; tulip_down()
835 void __iomem *ioaddr = tp->base_addr; tulip_close()
855 void __iomem *ioaddr = tp->base_addr; tulip_get_stats()
914 void __iomem *ioaddr = tp->base_addr; private_ioctl()
1070 void __iomem *ioaddr = tp->base_addr; set_rx_mode()
1473 tp->base_addr = ioaddr; tulip_init_one()
1808 void __iomem *ioaddr = tp->base_addr; tulip_set_wolopts()
1875 void __iomem *ioaddr = tp->base_addr; tulip_resume()
1938 pci_iounmap(pdev, tp->base_addr); tulip_remove_one()
/linux-4.4.14/drivers/net/ethernet/realtek/
H A Datp.c213 If dev->base_addr == 0, probe all likely locations.
214 If dev->base_addr == 1, always return failure.
215 If dev->base_addr == 2, allocate space for the device and return success
223 int base_addr = io[0]; atp_init() local
225 if (base_addr > 0x1ff) /* Check a single specified location. */ atp_init()
226 return atp_probe1(base_addr); atp_init()
227 else if (base_addr == 1) /* Don't probe at all. */ atp_init()
323 dev->base_addr = ioaddr; atp_probe1()
335 dev->name, dev->base_addr, dev->irq, dev->dev_addr); atp_probe1()
370 long ioaddr = dev->base_addr; get_node_ID()
457 long ioaddr = dev->base_addr; hardware_init()
539 long ioaddr = dev->base_addr; tx_timeout()
556 long ioaddr = dev->base_addr; atp_send_packet()
602 ioaddr = dev->base_addr; atp_interrupt()
717 long ioaddr = dev->base_addr; atp_timed_checker()
755 long ioaddr = dev->base_addr; net_rx()
828 long ioaddr = dev->base_addr; net_close()
854 long ioaddr = dev->base_addr; set_rx_mode()
/linux-4.4.14/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_ppe.c25 void __iomem *base_addr; hns_ppe_common_get_ioaddr() local
30 base_addr = ppe_common->dsaf_dev->ppe_base hns_ppe_common_get_ioaddr()
33 base_addr = ppe_common->dsaf_dev->sds_base hns_ppe_common_get_ioaddr()
37 return base_addr; hns_ppe_common_get_ioaddr()
85 void __iomem *base_addr; hns_ppe_get_iobase() local
89 base_addr = ppe_common->dsaf_dev->ppe_base + hns_ppe_get_iobase()
93 base_addr = ppe_common->dsaf_dev->sds_base + hns_ppe_get_iobase()
97 return base_addr; hns_ppe_get_iobase()
H A Dhns_dsaf_misc.c281 u8 *base_addr = (u8 *)mac_cb->serdes_vaddr + hns_mac_config_sds_loopback() local
307 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en); hns_mac_config_sds_loopback()
/linux-4.4.14/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_vf.c217 u32 base_addr; fm10k_read_mac_addr_vf() local
219 base_addr = fm10k_read_reg(hw, FM10K_TDBAL(0)); fm10k_read_mac_addr_vf()
222 if (base_addr << 24) fm10k_read_mac_addr_vf()
225 perm_addr[3] = (u8)(base_addr >> 24); fm10k_read_mac_addr_vf()
226 perm_addr[4] = (u8)(base_addr >> 16); fm10k_read_mac_addr_vf()
227 perm_addr[5] = (u8)(base_addr >> 8); fm10k_read_mac_addr_vf()
229 base_addr = fm10k_read_reg(hw, FM10K_TDBAH(0)); fm10k_read_mac_addr_vf()
232 if ((~base_addr) >> 24) fm10k_read_mac_addr_vf()
235 perm_addr[0] = (u8)(base_addr >> 16); fm10k_read_mac_addr_vf()
236 perm_addr[1] = (u8)(base_addr >> 8); fm10k_read_mac_addr_vf()
237 perm_addr[2] = (u8)(base_addr); fm10k_read_mac_addr_vf()
/linux-4.4.14/drivers/net/ethernet/cirrus/
H A Dep93xx_eth.c159 void __iomem *base_addr; member in struct:ep93xx_priv
182 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
183 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
184 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
185 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
186 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
187 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
790 if (ep->base_addr != NULL) ep93xx_eth_remove()
791 iounmap(ep->base_addr); ep93xx_eth_remove()
841 ep->base_addr = ioremap(mem->start, resource_size(mem)); ep93xx_eth_probe()
842 if (ep->base_addr == NULL) { ep93xx_eth_probe()
H A Dmac89x0.c143 nubus_writew(swab16(portno), dev->base_addr + ADD_PORT); readreg_io()
144 return swab16(nubus_readw(dev->base_addr + DATA_PORT)); readreg_io()
150 nubus_writew(swab16(portno), dev->base_addr + ADD_PORT); writereg_io()
151 nubus_writew(swab16(value), dev->base_addr + DATA_PORT); writereg_io()
236 dev->base_addr = ioaddr; mac89x0_probe()
265 dev->base_addr); mac89x0_probe()
293 nubus_writew(0, dev->base_addr + ADD_PORT); mac89x0_probe()
423 ioaddr = dev->base_addr; net_interrupt()
433 while ((status = swab16(nubus_readw(dev->base_addr + ISQ_PORT)))) { net_interrupt()
630 nubus_writew(0, dev_cs89x0->base_addr + ADD_PORT); cleanup_module()
/linux-4.4.14/drivers/media/pci/ivtv/
H A Divtv-driver.c742 itv->base_addr = pci_resource_start(itv->pdev, 0); ivtv_init_struct1()
851 if (!request_mem_region(itv->base_addr, IVTV_ENCODER_SIZE, "ivtv encoder")) { ivtv_setup_pci()
856 if (!request_mem_region(itv->base_addr + IVTV_REG_OFFSET, ivtv_setup_pci()
859 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE); ivtv_setup_pci()
864 !request_mem_region(itv->base_addr + IVTV_DECODER_OFFSET, ivtv_setup_pci()
867 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE); ivtv_setup_pci()
868 release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE); ivtv_setup_pci()
903 pdev->irq, pci_latency, (u64)itv->base_addr); ivtv_setup_pci()
1035 IVTV_DEBUG_INFO("base addr: 0x%llx\n", (u64)itv->base_addr); ivtv_probe()
1046 (u64)itv->base_addr + IVTV_ENCODER_OFFSET, IVTV_ENCODER_SIZE); ivtv_probe()
1047 itv->enc_mem = ioremap_nocache(itv->base_addr + IVTV_ENCODER_OFFSET, ivtv_probe()
1063 (u64)itv->base_addr + IVTV_DECODER_OFFSET, IVTV_DECODER_SIZE); ivtv_probe()
1064 itv->dec_mem = ioremap_nocache(itv->base_addr + IVTV_DECODER_OFFSET, ivtv_probe()
1085 (u64)itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE); ivtv_probe()
1087 ioremap_nocache(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE); ivtv_probe()
1296 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE); ivtv_probe()
1297 release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE); ivtv_probe()
1299 release_mem_region(itv->base_addr + IVTV_DECODER_OFFSET, IVTV_DECODER_SIZE); ivtv_probe()
1457 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE); ivtv_remove()
1458 release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE); ivtv_remove()
1460 release_mem_region(itv->base_addr + IVTV_DECODER_OFFSET, IVTV_DECODER_SIZE); ivtv_remove()
/linux-4.4.14/drivers/net/irda/
H A Dbfin_sir.h56 unsigned long base_addr; member in struct:bfin_sir_port_res
H A Dvlsi_ir.c185 unsigned iobase = ndev->base_addr; vlsi_proc_ndev()
666 outw(0, ndev->base_addr+VLSI_PIO_PROMPT); vlsi_rx_interrupt()
850 unsigned iobase = ndev->base_addr; vlsi_hard_start_xmit()
1003 fifocnt = inw(ndev->base_addr+VLSI_PIO_RCVBCNT) & RCVBCNT_MASK; vlsi_hard_start_xmit()
1069 iobase = ndev->base_addr; vlsi_tx_interrupt()
1251 iobase = ndev->base_addr; vlsi_init_chip()
1295 unsigned iobase = ndev->base_addr; vlsi_start_hw()
1327 unsigned iobase = ndev->base_addr; vlsi_stop_hw()
1358 vlsi_reg_debug(ndev->base_addr, __func__); vlsi_tx_timeout()
1398 vlsi_set_baud(idev, ndev->base_addr); vlsi_ioctl()
1413 fifocnt = inw(ndev->base_addr+VLSI_PIO_RCVBCNT) & RCVBCNT_MASK; vlsi_ioctl()
1437 iobase = ndev->base_addr; vlsi_interrupt()
1479 ndev->base_addr = pci_resource_start(idev->pdev,0); vlsi_open()
1486 outb(IRINTR_INT_MASK, ndev->base_addr+VLSI_PIO_IRINTR); vlsi_open()
1498 sprintf(hwname, "VLSI-FIR @ 0x%04x", (unsigned)ndev->base_addr); vlsi_open()
1566 ndev->base_addr = pci_resource_start(pdev,0); vlsi_irda_init()
/linux-4.4.14/drivers/watchdog/
H A Dsp5100_tco.c321 u32 index_reg, data_reg, base_addr; sp5100_tco_setupdevice() local
343 base_addr = SB800_PM_WATCHDOG_BASE;
348 base_addr = SP5100_PM_WATCHDOG_BASE;
361 outb(base_addr+3, index_reg);
363 outb(base_addr+2, index_reg);
365 outb(base_addr+1, index_reg);
367 outb(base_addr+0, index_reg);
H A Dsch311x_wdt.c463 unsigned short base_addr; sch311x_detect() local
485 base_addr = (sch311x_sio_inb(sio_config_port, 0x60) << 8) | sch311x_detect()
487 if (!base_addr) { sch311x_detect()
492 *addr = base_addr; sch311x_detect()
494 pr_info("Found an SMSC SCH311%d chip at 0x%04x\n", dev_id, base_addr); sch311x_detect()
H A Dpcwd.c806 int base_addr = pcwd_ioports[id]; pcwd_isa_match() local
815 if (!request_region(base_addr, 4, "PCWD")) { pcwd_isa_match()
816 pr_info("Port 0x%04x unavailable\n", base_addr); pcwd_isa_match()
822 port0 = inb_p(base_addr); /* For REV A boards */ pcwd_isa_match()
823 port1 = inb_p(base_addr + 1); /* For REV C boards */ pcwd_isa_match()
833 port0 = inb_p(base_addr); pcwd_isa_match()
834 port1 = inb_p(base_addr + 1); pcwd_isa_match()
844 release_region(base_addr, 4); pcwd_isa_match()
/linux-4.4.14/drivers/dma/sh/
H A Dsudmac.c43 u32 base_addr; member in struct:sudmac_regs
106 sudmac_writel(sc, hw->base_addr, SUDMAC_CH0BA + sc->offset); sudmac_set_reg()
189 sd->hw.base_addr = dst; sudmac_desc_setup()
191 sd->hw.base_addr = src; sudmac_desc_setup()
235 return sd->hw.base_addr + sd->hw.base_byte_count == current_addr; sudmac_desc_completed()
/linux-4.4.14/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_main.c1174 void __iomem *base_addr; xgene_enet_get_resources() local
1187 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res)); xgene_enet_get_resources()
1188 if (!pdata->base_addr) { xgene_enet_get_resources()
1278 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET); xgene_enet_get_resources()
1280 base_addr = pdata->base_addr; xgene_enet_get_resources()
1281 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; xgene_enet_get_resources()
1282 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; xgene_enet_get_resources()
1283 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; xgene_enet_get_resources()
1286 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET; xgene_enet_get_resources()
1290 pdata->mcx_mac_csr_addr = base_addr + offset; xgene_enet_get_resources()
1292 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET; xgene_enet_get_resources()
1293 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET; xgene_enet_get_resources()
/linux-4.4.14/tools/testing/selftests/x86/
H A Dldt_gdt.c196 .base_addr = 0, do_simple_tests()
219 desc.base_addr = 0xf0000000; do_simple_tests()
347 desc.base_addr = 1; do_simple_tests()
350 desc.base_addr = 0; do_simple_tests()
461 .base_addr = 0, do_multicpu_tests()
533 .base_addr = 0, do_exec_test()
H A Dsigreturn.c165 .base_addr = (unsigned long)int3, setup_ldt()
178 .base_addr = (unsigned long)stack16, setup_ldt()
191 .base_addr = (unsigned long)int3, setup_ldt()
204 .base_addr = (unsigned long)stack16, setup_ldt()
217 .base_addr = (unsigned long)stack16, setup_ldt()
242 .base_addr = (unsigned long)stack16, setup_ldt()
/linux-4.4.14/drivers/net/ethernet/hp/
H A Dhp100.c417 err = hp100_isa_probe(dev, dev->base_addr); hp100_probe()
489 dev->base_addr = ioaddr; hp100_probe1()
679 dev->base_addr = ioaddr; hp100_probe1()
817 int ioaddr = dev->base_addr; hp100_hwinit()
911 int ioaddr = dev->base_addr; hp100_mmuinit()
1092 int ioaddr = dev->base_addr; hp100_open()
1129 int ioaddr = dev->base_addr; hp100_close()
1169 int ioaddr = dev->base_addr; hp100_init_pdls()
1265 int ioaddr = dev->base_addr; hp100_build_rx_pdl()
1345 int ioaddr = dev->base_addr; hp100_rxfill()
1387 int ioaddr = dev->base_addr; hp100_BM_shutdown()
1495 int ioaddr = dev->base_addr; hp100_start_xmit_bm()
1609 int ioaddr = dev->base_addr; hp100_clean_txring()
1646 int ioaddr = dev->base_addr; hp100_start_xmit()
1778 int ioaddr = dev->base_addr; hp100_rx()
1878 int ioaddr = dev->base_addr; hp100_rx_bm()
1986 int ioaddr = dev->base_addr; hp100_get_stats()
2003 int ioaddr = dev->base_addr; hp100_update_stats()
2028 int ioaddr = dev->base_addr; hp100_misc_interrupt()
2032 int ioaddr = dev->base_addr; hp100_misc_interrupt()
2072 int ioaddr = dev->base_addr; hp100_set_multicast_list()
2208 ioaddr = dev->base_addr; hp100_interrupt()
2331 int ioaddr = dev->base_addr; hp100_start_interface()
2392 int ioaddr = dev->base_addr; hp100_stop_interface()
2428 int ioaddr = probe_ioaddr > 0 ? probe_ioaddr : dev->base_addr; hp100_load_eeprom()
2450 int ioaddr = dev->base_addr; hp100_sense_lan()
2499 int ioaddr = dev->base_addr; hp100_down_vg_link()
2603 int ioaddr = dev->base_addr; hp100_login_to_vg_hub()
2768 int ioaddr = dev->base_addr; hp100_cascade_reset()
2800 int ioaddr = dev->base_addr; hp100_RegisterDump()
2833 release_region(d->base_addr, HP100_REGION_SIZE); cleanup_dev()
2857 err = hp100_probe1(dev, edev->base_addr + 0xC38, HP100_BUS_EISA, NULL); hp100_eisa_probe()
2863 dev->base_addr); hp100_eisa_probe()
/linux-4.4.14/drivers/net/ethernet/cavium/liquidio/
H A Drequest_manager.c99 iq->base_addr = lio_dma_alloc(oct, q_size, octeon_init_instr_queue()
101 if (!iq->base_addr) { octeon_init_instr_queue()
114 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma); octeon_init_instr_queue()
123 iq_no, iq->base_addr, iq->base_addr_dma, iq->max_count); octeon_init_instr_queue()
149 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma); octeon_init_instr_queue()
180 if (iq->base_addr) { octeon_delete_instr_queue()
182 lio_dma_free(oct, (u32)q_size, iq->base_addr, octeon_delete_instr_queue()
269 iqptr = iq->base_addr + (cmdsize * iq->host_write_index); __copy_cmd_into_iq()
H A Docteon_console.c289 desc->base_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(oct, named_addr, __cvmx_bootmem_find_named_block_flags()
290 base_addr); __cvmx_bootmem_find_named_block_flags()
352 * @param base_addr Address the block is at (OUTPUT)
358 u64 *base_addr, u64 *size) octeon_named_block_find()
366 *base_addr = named_block->base_addr; octeon_named_block_find()
357 octeon_named_block_find(struct octeon_device *oct, const char *name, u64 *base_addr, u64 *size) octeon_named_block_find() argument
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb3/
H A Dcxgb3_ctl_defs.h159 unsigned long long base_addr; member in struct:rdma_cq_setup
170 unsigned long long base_addr; member in struct:rdma_ctrlqp_setup
H A Dt3_hw.c2197 * @base_addr: base address of queue
2208 enum sge_context_type type, int respq, u64 base_addr, t3_sge_init_ecntxt()
2214 if (base_addr & 0xfff) /* must be 4K aligned */ t3_sge_init_ecntxt()
2219 base_addr >>= 12; t3_sge_init_ecntxt()
2223 V_EC_BASE_LO(base_addr & 0xffff)); t3_sge_init_ecntxt()
2224 base_addr >>= 16; t3_sge_init_ecntxt()
2225 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr); t3_sge_init_ecntxt()
2226 base_addr >>= 32; t3_sge_init_ecntxt()
2228 V_EC_BASE_HI(base_addr & 0xf) | V_EC_RESPQ(respq) | t3_sge_init_ecntxt()
2239 * @base_addr: base address of queue
2251 int gts_enable, u64 base_addr, unsigned int size, t3_sge_init_flcntxt()
2255 if (base_addr & 0xfff) /* must be 4K aligned */ t3_sge_init_flcntxt()
2260 base_addr >>= 12; t3_sge_init_flcntxt()
2261 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr); t3_sge_init_flcntxt()
2262 base_addr >>= 32; t3_sge_init_flcntxt()
2264 V_FL_BASE_HI((u32) base_addr) | t3_sge_init_flcntxt()
2280 * @base_addr: base address of queue
2291 int irq_vec_idx, u64 base_addr, unsigned int size, t3_sge_init_rspcntxt()
2296 if (base_addr & 0xfff) /* must be 4K aligned */ t3_sge_init_rspcntxt()
2301 base_addr >>= 12; t3_sge_init_rspcntxt()
2304 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); t3_sge_init_rspcntxt()
2305 base_addr >>= 32; t3_sge_init_rspcntxt()
2309 V_CQ_BASE_HI((u32) base_addr) | intr | V_RQ_GEN(gen)); t3_sge_init_rspcntxt()
2318 * @base_addr: base address of queue
2329 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, t3_sge_init_cqcntxt() argument
2333 if (base_addr & 0xfff) /* must be 4K aligned */ t3_sge_init_cqcntxt()
2338 base_addr >>= 12; t3_sge_init_cqcntxt()
2340 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); t3_sge_init_cqcntxt()
2341 base_addr >>= 32; t3_sge_init_cqcntxt()
2343 V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) | t3_sge_init_cqcntxt()
3493 unsigned int base_addr, const char *name) mc7_prep()
3499 mc7->offset = base_addr - MC7_PMRX_BASE_ADDR; mc7_prep()
2207 t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, enum sge_context_type type, int respq, u64 base_addr, unsigned int size, unsigned int token, int gen, unsigned int cidx) t3_sge_init_ecntxt() argument
2250 t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, int gts_enable, u64 base_addr, unsigned int size, unsigned int bsize, unsigned int cong_thres, int gen, unsigned int cidx) t3_sge_init_flcntxt() argument
2290 t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, int irq_vec_idx, u64 base_addr, unsigned int size, unsigned int fl_thres, int gen, unsigned int cidx) t3_sge_init_rspcntxt() argument
3492 mc7_prep(struct adapter *adapter, struct mc7 *mc7, unsigned int base_addr, const char *name) mc7_prep() argument
/linux-4.4.14/sound/firewire/bebob/
H A Dbebob_proc.c23 u32 base_addr; member in struct:hw_info
62 snd_iprintf(buffer, "Base Addr:\t0x%X\n", info->base_addr); proc_read_hw_info()
/linux-4.4.14/drivers/scsi/snic/
H A Dvnic_cq.c61 paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET; svnic_cq_init()
H A Dvnic_dev.h57 dma_addr_t base_addr; member in struct:vnic_dev_ring
H A Dvnic_dev.c239 ring->base_addr = ALIGN(ring->base_addr_unaligned, svnic_dev_alloc_desc_ring()
242 (ring->base_addr - ring->base_addr_unaligned); svnic_dev_alloc_desc_ring()
393 vdev->args[0] = (u64) dc2c->results_ring.base_addr | VNIC_PADDR_TARGET; svnic_dev_init_devcmd2()
H A Dvnic_wq.c162 paddr = (u64)wq->ring.base_addr | VNIC_PADDR_TARGET; vnic_wq_init_start()
/linux-4.4.14/drivers/video/fbdev/
H A Dpmag-aa-fb.c412 unsigned long base_addr = CKSEG1ADDR(get_tc_base_addr(slot)); init_one() local
420 ip->bt455 = (struct bt455_regs *) (base_addr + PMAG_AA_BT455_OFFSET); init_one()
421 ip->bt431 = (struct bt431_regs *) (base_addr + PMAG_AA_BT431_OFFSET); init_one()
422 ip->fb_start = base_addr + PMAG_AA_ONBOARD_FBMEM_OFFSET; init_one()
H A Dgrvga.c244 u32 base_addr; grvga_pan_display() local
249 base_addr = fix->smem_start + (var->yoffset * fix->line_length); grvga_pan_display()
250 base_addr &= ~3UL; grvga_pan_display()
253 __raw_writel(base_addr, grvga_pan_display()
/linux-4.4.14/drivers/scsi/fnic/
H A Dvnic_cq.c60 paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET; vnic_cq_init()
H A Dvnic_wq_copy.c108 paddr = (u64)wq->ring.base_addr | VNIC_PADDR_TARGET; vnic_wq_copy_init()
H A Dvnic_dev.h98 dma_addr_t base_addr; member in struct:vnic_dev_ring
H A Dvnic_rq.c121 paddr = (u64)rq->ring.base_addr | VNIC_PADDR_TARGET; vnic_rq_init()
H A Dvnic_wq.c120 paddr = (u64)wq->ring.base_addr | VNIC_PADDR_TARGET; vnic_wq_init()
/linux-4.4.14/drivers/net/wireless/mwifiex/
H A Dusb.h94 __le32 base_addr; member in struct:fw_header
/linux-4.4.14/arch/x86/platform/atom/
H A Dpmc_atom.c41 u32 base_addr; member in struct:pmc_dev
399 pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr); pmc_setup_dev()
400 pmc->base_addr &= PMC_BASE_ADDR_MASK; pmc_setup_dev()
402 pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN); pmc_setup_dev()
/linux-4.4.14/mm/
H A Dpercpu-km.c69 chunk->base_addr = page_address(pages) - pcpu_group_offsets[0]; pcpu_create_chunk()
/linux-4.4.14/include/linux/
H A Deisa.h38 unsigned long base_addr; member in struct:eisa_device
/linux-4.4.14/arch/sh/mm/
H A Dcache-sh4.c320 unsigned long base_addr = addr; __flush_cache_one() local
353 ea = base_addr + PAGE_SIZE; __flush_cache_one()
354 a = base_addr; __flush_cache_one()
369 base_addr += way_incr; __flush_cache_one()
/linux-4.4.14/sound/pci/aw2/
H A Daw2-saa7146.c41 #define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
42 #define READREG(addr) readl(chip->base_addr + (addr))
61 chip->base_addr = NULL; snd_aw2_saa7146_free()
94 chip->base_addr = pci_base_addr; snd_aw2_saa7146_setup()
H A Daw2-saa7146.h45 void __iomem *base_addr; member in struct:snd_aw2_saa7146
/linux-4.4.14/sound/soc/intel/atom/sst/
H A Dsst_pvt.c407 u32 relocate_imr_addr_mrfld(u32 base_addr) relocate_imr_addr_mrfld() argument
411 base_addr = MRFLD_FW_VIRTUAL_BASE + (base_addr % (512 * 1024 * 1024)); relocate_imr_addr_mrfld()
412 return base_addr; relocate_imr_addr_mrfld()
/linux-4.4.14/drivers/net/ethernet/fujitsu/
H A Dfmvj18x_cs.c434 dev->base_addr = link->resource[0]->start; fmvj18x_config()
441 ioaddr = dev->base_addr; fmvj18x_config()
528 dev->base_addr, dev->irq, dev->dev_addr); fmvj18x_config()
610 ioaddr = dev->base_addr; fmvj18x_setup_mfc()
718 ioaddr = dev->base_addr; fjn_interrupt()
776 unsigned int ioaddr = dev->base_addr; fjn_tx_timeout()
806 unsigned int ioaddr = dev->base_addr; fjn_start_xmit()
878 unsigned int ioaddr = dev->base_addr; fjn_reset()
956 unsigned int ioaddr = dev->base_addr; fjn_rx()
1048 "PCMCIA 0x%lx", dev->base_addr); netdev_get_drvinfo()
1088 unsigned int ioaddr = dev->base_addr; fjn_close()
1123 unsigned int ioaddr = dev->base_addr; set_rx_mode()
/linux-4.4.14/arch/sparc/kernel/
H A Dsetup_32.c348 if (sp_banks[i].base_addr < phys_base) setup_arch()
349 phys_base = sp_banks[i].base_addr; setup_arch()
350 top = sp_banks[i].base_addr + setup_arch()
H A Dchmc.c165 u64 base_addr; member in struct:jbusmc_dimm_group
282 if (phys_addr < dp->base_addr || jbusmc_find_dimm_group()
283 (dp->base_addr + dp->size) <= phys_addr) jbusmc_find_dimm_group()
376 dp->base_addr = (p->portid * (64UL * 1024 * 1024 * 1024)); jbusmc_construct_one_dimm_group()
377 dp->base_addr += (index * (8UL * 1024 * 1024 * 1024)); jbusmc_construct_one_dimm_group()
378 dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs); jbusmc_construct_one_dimm_group()
/linux-4.4.14/arch/x86/include/asm/
H A Ddesc.h15 desc->base0 = (info->base_addr & 0x0000ffff); fill_ldt()
16 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; fill_ldt()
29 desc->base2 = (info->base_addr & 0xff000000) >> 24; fill_ldt()
256 ((info)->base_addr == 0 && \
268 return (info->base_addr == 0 && LDT_zero()
/linux-4.4.14/arch/arc/kernel/
H A Dsetup.c88 cpu->iccm.base_addr = iccm.base << 16; read_arc_build_cfg_regs()
98 cpu->dccm.base_addr = dccm_base.addr << 8; read_arc_build_cfg_regs()
282 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), arc_extn_mumbojumbo()
283 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); arc_extn_mumbojumbo()
310 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) arc_chk_core_config()
/linux-4.4.14/drivers/net/fddi/
H A Ddefxx.c451 unsigned long base_addr = to_eisa_device(bdev)->base_addr; dfx_get_bars() local
456 bar_lo = inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_2); dfx_get_bars()
458 bar_lo |= inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_1); dfx_get_bars()
460 bar_lo |= inb(base_addr + PI_ESIC_K_MEM_ADD_LO_CMP_0); dfx_get_bars()
463 bar_hi = inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_2); dfx_get_bars()
465 bar_hi |= inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_1); dfx_get_bars()
467 bar_hi |= inb(base_addr + PI_ESIC_K_MEM_ADD_HI_CMP_0); dfx_get_bars()
472 bar_start[0] = base_addr; dfx_get_bars()
475 bar_start[1] = base_addr + PI_DEFEA_K_BURST_HOLDOFF; dfx_get_bars()
477 bar_start[2] = base_addr + PI_ESIC_K_ESIC_CSR; dfx_get_bars()
625 dev->base_addr = bar_start[0]; dfx_register()
737 unsigned long base_addr = to_eisa_device(bdev)->base_addr; dfx_bus_init() local
740 outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL); dfx_bus_init()
743 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_bus_init()
778 outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_1); dfx_bus_init()
780 outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_0_0); dfx_bus_init()
783 outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_1); dfx_bus_init()
785 outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_0_0); dfx_bus_init()
788 outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_1); dfx_bus_init()
790 outb(val, base_addr + PI_ESIC_K_IO_ADD_CMP_1_0); dfx_bus_init()
793 outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_1); dfx_bus_init()
795 outb(val, base_addr + PI_ESIC_K_IO_ADD_MASK_1_0); dfx_bus_init()
803 outb(val, base_addr + PI_ESIC_K_FUNCTION_CNTRL); dfx_bus_init()
810 outb(val, base_addr + PI_ESIC_K_SLOT_CNTRL); dfx_bus_init()
816 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); dfx_bus_init()
821 outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF); dfx_bus_init()
824 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_bus_init()
826 outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_bus_init()
890 unsigned long base_addr = to_eisa_device(bdev)->base_addr; dfx_bus_uninit() local
893 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_bus_uninit()
895 outb(val, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_bus_uninit()
898 outb(0, base_addr + PI_ESIC_K_SLOT_CNTRL); dfx_bus_uninit()
901 outb(0, base_addr + PI_ESIC_K_FUNCTION_CNTRL); dfx_bus_uninit()
1982 unsigned long base_addr = to_eisa_device(bdev)->base_addr; dfx_interrupt() local
1985 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_interrupt()
1993 outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_interrupt()
1999 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_interrupt()
2001 outb(status, base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); dfx_interrupt()
/linux-4.4.14/drivers/net/ethernet/toshiba/
H A Dtc35815.c507 (struct tc35815_regs __iomem *)dev->base_addr; tc_mdio_read()
524 (struct tc35815_regs __iomem *)dev->base_addr; tc_mdio_write()
550 (struct tc35815_regs __iomem *)dev->base_addr; tc_handle_link_change()
751 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_init_dev_addr()
833 dev->base_addr = (unsigned long)ioaddr; tc35815_init_one()
860 dev->base_addr, tc35815_init_one()
1206 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_schedule_restart()
1220 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_tx_timeout()
1331 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_send_packet()
1451 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_interrupt()
1644 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_poll()
1718 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_check_tx_stat()
1803 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_txdone()
1871 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_get_stats()
1883 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_set_cam_entry()
1930 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_set_multicast_list()
2068 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_chip_reset()
2111 (struct tc35815_regs __iomem *)dev->base_addr; tc35815_chip_init()
/linux-4.4.14/drivers/tty/serial/
H A Dicom.c878 int_reg = icom_adapter->base_addr + 0x8024; icom_interrupt()
903 int_reg = icom_adapter->base_addr + 0x8004; icom_interrupt()
905 int_reg = icom_adapter->base_addr + 0x4004; icom_interrupt()
1374 icom_port->global_reg = icom_adapter->base_addr + 0x4000; icom_port_active()
1375 icom_port->int_reg = icom_adapter->base_addr + icom_port_active()
1378 icom_port->global_reg = icom_adapter->base_addr + 0x8000; icom_port_active()
1380 icom_port->int_reg = icom_adapter->base_addr + icom_port_active()
1383 icom_port->int_reg = icom_adapter->base_addr + icom_port_active()
1398 icom_port->dram = icom_adapter->base_addr + icom_load_ports()
1479 iounmap(icom_adapter->base_addr); icom_remove_adapter()
1553 icom_adapter->base_addr = pci_ioremap_bar(dev, 0); icom_probe()
1555 if (!icom_adapter->base_addr) { icom_probe()
1593 iounmap(icom_adapter->base_addr); icom_probe()
/linux-4.4.14/drivers/i2c/busses/
H A Di2c-eg20t.c741 void __iomem *base_addr; pch_i2c_probe() local
765 base_addr = pci_iomap(pdev, 1, 0); pch_i2c_probe()
767 if (base_addr == NULL) { pch_i2c_probe()
795 /* base_addr + offset; */ pch_i2c_probe()
796 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i; pch_i2c_probe()
819 pci_iounmap(pdev, base_addr); pch_i2c_probe()
/linux-4.4.14/drivers/infiniband/hw/cxgb3/
H A Dcxio_hal.c129 setup.base_addr = 0; /* NULL address */ cxio_hal_clear_cq_ctx()
181 setup.base_addr = (u64) (cq->dma_addr); cxio_create_cq()
197 setup.base_addr = (u64) (cq->dma_addr); cxio_resize_cq()
504 setup.base_addr = 0; /* NULL address */ cxio_hal_init_ctrl_cq()
518 u64 base_addr; cxio_hal_init_ctrl_qp() local
553 base_addr = rdev_p->ctrl_qp.dma_addr; cxio_hal_init_ctrl_qp()
554 base_addr >>= 12; cxio_hal_init_ctrl_qp()
556 V_EC_BASE_LO((u32) base_addr & 0xffff)); cxio_hal_init_ctrl_qp()
559 base_addr >>= 16; cxio_hal_init_ctrl_qp()
560 ctx1 = (u32) base_addr; cxio_hal_init_ctrl_qp()
561 base_addr >>= 32; cxio_hal_init_ctrl_qp()
562 ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) | cxio_hal_init_ctrl_qp()
/linux-4.4.14/drivers/scsi/isci/
H A Drequest.h278 char *base_addr = (char *)ireq; sci_io_request_get_dma_addr() local
280 BUG_ON(requested_addr < base_addr); sci_io_request_get_dma_addr()
281 BUG_ON((requested_addr - base_addr) >= sizeof(*ireq)); sci_io_request_get_dma_addr()
283 return ireq->request_daddr + (requested_addr - base_addr); sci_io_request_get_dma_addr()
/linux-4.4.14/drivers/net/fddi/skfp/h/
H A Dtargetos.h128 unsigned long base_addr; member in struct:s_smt_os
/linux-4.4.14/drivers/net/ethernet/cisco/enic/
H A Dvnic_cq.c65 paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET; vnic_cq_init()
/linux-4.4.14/arch/sparc/include/asm/
H A Dpage_32.h38 unsigned long base_addr; member in struct:sparc_phys_banks
/linux-4.4.14/drivers/media/pci/cx18/
H A Dcx18-driver.c732 cx->base_addr = pci_resource_start(cx->pci_dev, 0); cx18_init_struct1()
826 if (!request_mem_region(cx->base_addr, CX18_MEM_SIZE, "cx18 encoder")) { cx18_setup_pci()
851 cx->pci_dev->irq, pci_latency, (u64)cx->base_addr); cx18_setup_pci()
948 CX18_DEBUG_INFO("base addr: 0x%llx\n", (u64)cx->base_addr); cx18_probe()
957 (u64)cx->base_addr + CX18_MEM_OFFSET, CX18_MEM_SIZE); cx18_probe()
958 cx->enc_mem = ioremap_nocache(cx->base_addr + CX18_MEM_OFFSET, cx18_probe()
1145 release_mem_region(cx->base_addr, CX18_MEM_SIZE); cx18_probe()
1310 release_mem_region(cx->base_addr, CX18_MEM_SIZE); cx18_remove()
/linux-4.4.14/drivers/net/wireless/ath/ath10k/
H A Dce.c841 "boot init ce src ring id %d entries %d base_addr %p\n", ath10k_ce_init_src_ring()
875 "boot ce dest ring id %d entries %d base_addr %p\n", ath10k_ce_init_dest_ring()
887 dma_addr_t base_addr; ath10k_ce_alloc_src_ring() local
909 &base_addr, GFP_KERNEL); ath10k_ce_alloc_src_ring()
915 src_ring->base_addr_ce_space_unaligned = base_addr; ath10k_ce_alloc_src_ring()
933 dma_addr_t base_addr; ath10k_ce_alloc_dest_ring() local
955 &base_addr, GFP_KERNEL); ath10k_ce_alloc_dest_ring()
961 dest_ring->base_addr_ce_space_unaligned = base_addr; ath10k_ce_alloc_dest_ring()
/linux-4.4.14/arch/mips/cavium-octeon/
H A Dsmp.c277 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + octeon_cpu_die()
330 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); octeon_update_boot_vector()
/linux-4.4.14/drivers/net/ethernet/xircom/
H A Dxirc2ps_cs.c318 unsigned int ioaddr = dev->base_addr;
900 dev->base_addr = link->resource[0]->start; xirc2ps_config()
914 local->manf_str, (u_long)dev->base_addr, (int)dev->irq, xirc2ps_config()
992 ioaddr = dev->base_addr; xirc2ps_interrupt()
1219 unsigned int ioaddr = dev->base_addr; do_start_xmit()
1302 unsigned int ioaddr = dev->base_addr; set_addresses()
1338 unsigned int ioaddr = dev->base_addr; set_multicast_list()
1414 dev->base_addr); netdev_get_drvinfo()
1425 unsigned int ioaddr = dev->base_addr; do_ioctl()
1457 unsigned int ioaddr = dev->base_addr; hardreset()
1474 unsigned int ioaddr = dev->base_addr; do_reset()
1635 unsigned int ioaddr = dev->base_addr; init_mii()
1705 unsigned int ioaddr = dev->base_addr; do_powerdown()
1717 unsigned int ioaddr = dev->base_addr; do_stop()
/linux-4.4.14/drivers/media/platform/davinci/
H A Ddm355_ccdc.c62 void __iomem *base_addr; member in struct:ccdc_oper_config
129 return __raw_readl(ccdc_cfg.base_addr + offset); regr()
134 __raw_writel(val, ccdc_cfg.base_addr + offset); regw()
989 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res)); dm355_ccdc_probe()
990 if (!ccdc_cfg.base_addr) { dm355_ccdc_probe()
1010 iounmap(ccdc_cfg.base_addr); dm355_ccdc_probe()
1022 iounmap(ccdc_cfg.base_addr); dm355_ccdc_remove()
H A Disif.c91 void __iomem *base_addr; member in struct:isif_oper_config
153 return __raw_readl(isif_cfg.base_addr + offset); regr()
158 __raw_writel(val, isif_cfg.base_addr + offset); regw()
1080 isif_cfg.base_addr = addr; isif_probe()
1102 if (isif_cfg.base_addr) isif_probe()
1103 iounmap(isif_cfg.base_addr); isif_probe()
1121 iounmap(isif_cfg.base_addr); isif_remove()
/linux-4.4.14/sound/soc/qcom/
H A Dlpass-platform.c316 unsigned int base_addr, curr_addr; lpass_platform_pcmops_pointer() local
320 LPAIF_RDMABASE_REG(v, ch), &base_addr); lpass_platform_pcmops_pointer()
335 return bytes_to_frames(substream->runtime, curr_addr - base_addr); lpass_platform_pcmops_pointer()
/linux-4.4.14/drivers/scsi/aic7xxx/
H A Daic7770_osm.c81 u_int eisaBase = edev->base_addr+AHC_EISA_SLOT_OFFSET; aic7770_probe()
/linux-4.4.14/drivers/net/wireless/orinoco/
H A Dorinoco.h190 int orinoco_if_add(struct orinoco_private *priv, unsigned long base_addr,
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100_core.c101 void __iomem *ioaddr = (void __iomem *)dev->base_addr; dwmac100_set_filter()

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