1/* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10#include <linux/module.h> 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/netdevice.h> 14#include <linux/etherdevice.h> 15#include <linux/platform_device.h> 16#include <linux/of.h> 17#include <linux/of_address.h> 18#include <linux/of_platform.h> 19 20#include "hns_dsaf_ppe.h" 21 22static void __iomem *hns_ppe_common_get_ioaddr( 23 struct ppe_common_cb *ppe_common) 24{ 25 void __iomem *base_addr; 26 27 int idx = ppe_common->comm_index; 28 29 if (idx == HNS_DSAF_COMM_SERVICE_NW_IDX) 30 base_addr = ppe_common->dsaf_dev->ppe_base 31 + PPE_COMMON_REG_OFFSET; 32 else 33 base_addr = ppe_common->dsaf_dev->sds_base 34 + (idx - 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET 35 + PPE_COMMON_REG_OFFSET; 36 37 return base_addr; 38} 39 40/** 41 * hns_ppe_common_get_cfg - get ppe common config 42 * @dsaf_dev: dasf device 43 * comm_index: common index 44 * retuen 0 - success , negative --fail 45 */ 46int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index) 47{ 48 struct ppe_common_cb *ppe_common; 49 int ppe_num; 50 51 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) 52 ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM; 53 else 54 ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM; 55 56 ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) + 57 ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL); 58 if (!ppe_common) 59 return -ENOMEM; 60 61 ppe_common->ppe_num = ppe_num; 62 ppe_common->dsaf_dev = dsaf_dev; 63 ppe_common->comm_index = comm_index; 64 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) 65 ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE; 66 else 67 ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG; 68 ppe_common->dev = dsaf_dev->dev; 69 70 ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common); 71 72 dsaf_dev->ppe_common[comm_index] = ppe_common; 73 74 return 0; 75} 76 77void hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index) 78{ 79 dsaf_dev->ppe_common[comm_index] = NULL; 80} 81 82static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common, 83 int ppe_idx) 84{ 85 void __iomem *base_addr; 86 int common_idx = ppe_common->comm_index; 87 88 if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) { 89 base_addr = ppe_common->dsaf_dev->ppe_base + 90 ppe_idx * PPE_REG_OFFSET; 91 92 } else { 93 base_addr = ppe_common->dsaf_dev->sds_base + 94 (common_idx - 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET; 95 } 96 97 return base_addr; 98} 99 100static int hns_ppe_get_port(struct ppe_common_cb *ppe_common, int idx) 101{ 102 int port; 103 104 if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) 105 port = idx; 106 else 107 port = HNS_PPE_SERVICE_NW_ENGINE_NUM 108 + ppe_common->comm_index - 1; 109 110 return port; 111} 112 113static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common) 114{ 115 u32 i; 116 struct hns_ppe_cb *ppe_cb; 117 u32 ppe_num = ppe_common->ppe_num; 118 119 for (i = 0; i < ppe_num; i++) { 120 ppe_cb = &ppe_common->ppe_cb[i]; 121 ppe_cb->dev = ppe_common->dev; 122 ppe_cb->next = NULL; 123 ppe_cb->ppe_common_cb = ppe_common; 124 ppe_cb->index = i; 125 ppe_cb->port = hns_ppe_get_port(ppe_common, i); 126 ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i); 127 ppe_cb->virq = 0; 128 } 129} 130 131static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb) 132{ 133 dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG, 134 PPE_CNT_CLR_CE_B, 1); 135} 136 137/** 138 * hns_ppe_checksum_hw - set ppe checksum caculate 139 * @ppe_device: ppe device 140 * @value: value 141 */ 142static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value) 143{ 144 dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG, 145 0xfffffff, 0, value); 146} 147 148static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common, 149 enum ppe_qid_mode qid_mdoe) 150{ 151 dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG, 152 PPE_CFG_QID_MODE_CF_QID_MODE_M, 153 PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe); 154} 155 156/** 157 * hns_ppe_set_qid - set ppe qid 158 * @ppe_common: ppe common device 159 * @qid: queue id 160 */ 161static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid) 162{ 163 u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); 164 165 if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, 166 PPE_CFG_QID_MODE_DEF_QID_S)) { 167 dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, 168 PPE_CFG_QID_MODE_DEF_QID_S, qid); 169 dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod); 170 } 171} 172 173/** 174 * hns_ppe_set_port_mode - set port mode 175 * @ppe_device: ppe device 176 * @mode: port mode 177 */ 178static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb, 179 enum ppe_port_mode mode) 180{ 181 dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode); 182} 183 184/** 185 * hns_ppe_common_init_hw - init ppe common device 186 * @ppe_common: ppe common device 187 * 188 * Return 0 on success, negative on failure 189 */ 190static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common) 191{ 192 enum ppe_qid_mode qid_mode; 193 enum dsaf_mode dsaf_mode = ppe_common->dsaf_dev->dsaf_mode; 194 195 hns_ppe_com_srst(ppe_common, 0); 196 mdelay(100); 197 hns_ppe_com_srst(ppe_common, 1); 198 mdelay(100); 199 200 if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) { 201 switch (dsaf_mode) { 202 case DSAF_MODE_ENABLE_FIX: 203 case DSAF_MODE_DISABLE_FIX: 204 qid_mode = PPE_QID_MODE0; 205 hns_ppe_set_qid(ppe_common, 0); 206 break; 207 case DSAF_MODE_ENABLE_0VM: 208 case DSAF_MODE_DISABLE_2PORT_64VM: 209 qid_mode = PPE_QID_MODE3; 210 break; 211 case DSAF_MODE_ENABLE_8VM: 212 case DSAF_MODE_DISABLE_2PORT_16VM: 213 qid_mode = PPE_QID_MODE4; 214 break; 215 case DSAF_MODE_ENABLE_16VM: 216 case DSAF_MODE_DISABLE_6PORT_0VM: 217 qid_mode = PPE_QID_MODE5; 218 break; 219 case DSAF_MODE_ENABLE_32VM: 220 case DSAF_MODE_DISABLE_6PORT_16VM: 221 qid_mode = PPE_QID_MODE2; 222 break; 223 case DSAF_MODE_ENABLE_128VM: 224 case DSAF_MODE_DISABLE_6PORT_4VM: 225 qid_mode = PPE_QID_MODE1; 226 break; 227 case DSAF_MODE_DISABLE_2PORT_8VM: 228 qid_mode = PPE_QID_MODE7; 229 break; 230 case DSAF_MODE_DISABLE_6PORT_2VM: 231 qid_mode = PPE_QID_MODE6; 232 break; 233 default: 234 dev_err(ppe_common->dev, 235 "get ppe queue mode failed! dsaf_mode=%d\n", 236 dsaf_mode); 237 return -EINVAL; 238 } 239 hns_ppe_set_qid_mode(ppe_common, qid_mode); 240 } 241 242 dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG, 243 PPE_COMMON_CNT_CLR_CE_B, 1); 244 245 return 0; 246} 247 248/*clr ppe exception irq*/ 249static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en) 250{ 251 u32 clr_vlue = 0xfffffffful; 252 u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/ 253 u32 vld_msk = 0; 254 255 /*only care bit 0,1,7*/ 256 dsaf_set_bit(vld_msk, 0, 1); 257 dsaf_set_bit(vld_msk, 1, 1); 258 dsaf_set_bit(vld_msk, 7, 1); 259 260 /*clr sts**/ 261 dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue); 262 263 /*for some reserved bits, so set 0**/ 264 dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk); 265} 266 267/** 268 * ppe_init_hw - init ppe 269 * @ppe_device: ppe device 270 */ 271static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb) 272{ 273 struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb; 274 u32 port = ppe_cb->port; 275 struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev; 276 277 hns_ppe_srst_by_port(dsaf_dev, port, 0); 278 mdelay(10); 279 hns_ppe_srst_by_port(dsaf_dev, port, 1); 280 281 /* clr and msk except irq*/ 282 hns_ppe_exc_irq_en(ppe_cb, 0); 283 284 if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) 285 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE); 286 else 287 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE); 288 hns_ppe_checksum_hw(ppe_cb, 0xffffffff); 289 hns_ppe_cnt_clr_ce(ppe_cb); 290} 291 292/** 293 * ppe_uninit_hw - uninit ppe 294 * @ppe_device: ppe device 295 */ 296static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb) 297{ 298 u32 port; 299 300 if (ppe_cb->ppe_common_cb) { 301 port = ppe_cb->index; 302 hns_ppe_srst_by_port(ppe_cb->ppe_common_cb->dsaf_dev, port, 0); 303 } 304} 305 306void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common) 307{ 308 u32 i; 309 310 for (i = 0; i < ppe_common->ppe_num; i++) { 311 hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]); 312 memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb)); 313 } 314} 315 316void hns_ppe_uninit(struct dsaf_device *dsaf_dev) 317{ 318 u32 i; 319 320 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 321 if (dsaf_dev->ppe_common[i]) 322 hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]); 323 hns_rcb_common_free_cfg(dsaf_dev, i); 324 hns_ppe_common_free_cfg(dsaf_dev, i); 325 } 326} 327 328/** 329 * hns_ppe_reset - reinit ppe/rcb hw 330 * @dsaf_dev: dasf device 331 * retuen void 332 */ 333void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index) 334{ 335 u32 i; 336 int ret; 337 struct ppe_common_cb *ppe_common; 338 339 ppe_common = dsaf_dev->ppe_common[ppe_common_index]; 340 ret = hns_ppe_common_init_hw(ppe_common); 341 if (ret) 342 return; 343 344 ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]); 345 if (ret) 346 return; 347 348 for (i = 0; i < ppe_common->ppe_num; i++) 349 hns_ppe_init_hw(&ppe_common->ppe_cb[i]); 350 351 hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]); 352} 353 354void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb) 355{ 356 struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats; 357 358 hw_stats->rx_pkts_from_sw 359 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); 360 hw_stats->rx_pkts 361 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); 362 hw_stats->rx_drop_no_bd 363 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); 364 hw_stats->rx_alloc_buf_fail 365 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); 366 hw_stats->rx_alloc_buf_wait 367 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); 368 hw_stats->rx_drop_no_buf 369 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); 370 hw_stats->rx_err_fifo_full 371 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); 372 373 hw_stats->tx_bd_form_rcb 374 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); 375 hw_stats->tx_pkts_from_rcb 376 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); 377 hw_stats->tx_pkts 378 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); 379 hw_stats->tx_err_fifo_empty 380 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); 381 hw_stats->tx_err_checksum 382 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); 383} 384 385int hns_ppe_get_sset_count(int stringset) 386{ 387 if (stringset == ETH_SS_STATS) 388 return ETH_PPE_STATIC_NUM; 389 return 0; 390} 391 392int hns_ppe_get_regs_count(void) 393{ 394 return ETH_PPE_DUMP_NUM; 395} 396 397/** 398 * ppe_get_strings - get ppe srting 399 * @ppe_device: ppe device 400 * @stringset: string set type 401 * @data: output string 402 */ 403void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data) 404{ 405 char *buff = (char *)data; 406 int index = ppe_cb->index; 407 408 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index); 409 buff = buff + ETH_GSTRING_LEN; 410 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index); 411 buff = buff + ETH_GSTRING_LEN; 412 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index); 413 buff = buff + ETH_GSTRING_LEN; 414 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index); 415 buff = buff + ETH_GSTRING_LEN; 416 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index); 417 buff = buff + ETH_GSTRING_LEN; 418 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index); 419 buff = buff + ETH_GSTRING_LEN; 420 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index); 421 buff = buff + ETH_GSTRING_LEN; 422 423 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index); 424 buff = buff + ETH_GSTRING_LEN; 425 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index); 426 buff = buff + ETH_GSTRING_LEN; 427 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index); 428 buff = buff + ETH_GSTRING_LEN; 429 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index); 430 buff = buff + ETH_GSTRING_LEN; 431 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index); 432} 433 434void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data) 435{ 436 u64 *regs_buff = data; 437 struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats; 438 439 regs_buff[0] = hw_stats->rx_pkts_from_sw; 440 regs_buff[1] = hw_stats->rx_pkts; 441 regs_buff[2] = hw_stats->rx_drop_no_bd; 442 regs_buff[3] = hw_stats->rx_alloc_buf_fail; 443 regs_buff[4] = hw_stats->rx_alloc_buf_wait; 444 regs_buff[5] = hw_stats->rx_drop_no_buf; 445 regs_buff[6] = hw_stats->rx_err_fifo_full; 446 447 regs_buff[7] = hw_stats->tx_bd_form_rcb; 448 regs_buff[8] = hw_stats->tx_pkts_from_rcb; 449 regs_buff[9] = hw_stats->tx_pkts; 450 regs_buff[10] = hw_stats->tx_err_fifo_empty; 451 regs_buff[11] = hw_stats->tx_err_checksum; 452} 453 454/** 455 * hns_ppe_init - init ppe device 456 * @dsaf_dev: dasf device 457 * retuen 0 - success , negative --fail 458 */ 459int hns_ppe_init(struct dsaf_device *dsaf_dev) 460{ 461 int i, k; 462 int ret; 463 464 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 465 ret = hns_ppe_common_get_cfg(dsaf_dev, i); 466 if (ret) 467 goto get_ppe_cfg_fail; 468 469 ret = hns_rcb_common_get_cfg(dsaf_dev, i); 470 if (ret) 471 goto get_rcb_cfg_fail; 472 473 hns_ppe_get_cfg(dsaf_dev->ppe_common[i]); 474 475 hns_rcb_get_cfg(dsaf_dev->rcb_common[i]); 476 } 477 478 for (i = 0; i < HNS_PPE_COM_NUM; i++) 479 hns_ppe_reset_common(dsaf_dev, i); 480 481 return 0; 482 483get_rcb_cfg_fail: 484 hns_ppe_common_free_cfg(dsaf_dev, i); 485get_ppe_cfg_fail: 486 for (k = i - 1; k >= 0; k--) { 487 hns_rcb_common_free_cfg(dsaf_dev, k); 488 hns_ppe_common_free_cfg(dsaf_dev, k); 489 } 490 return ret; 491} 492 493void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data) 494{ 495 struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb; 496 u32 *regs = data; 497 u32 i; 498 u32 offset; 499 500 /* ppe common registers */ 501 regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); 502 regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG); 503 regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG); 504 regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG); 505 regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG); 506 507 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) { 508 offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i; 509 regs[5 + i] = dsaf_read_dev(ppe_common, offset); 510 offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i; 511 regs[5 + i + DSAF_TOTAL_QUEUE_NUM] 512 = dsaf_read_dev(ppe_common, offset); 513 offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i; 514 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2] 515 = dsaf_read_dev(ppe_common, offset); 516 offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i; 517 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3] 518 = dsaf_read_dev(ppe_common, offset); 519 } 520 521 /* mark end of ppe regs */ 522 for (i = 521; i < 524; i++) 523 regs[i] = 0xeeeeeeee; 524 525 /* ppe channel registers */ 526 regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG); 527 regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG); 528 regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG); 529 regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG); 530 regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG); 531 regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG); 532 regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG); 533 regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG); 534 535 regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG); 536 regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG); 537 regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG); 538 regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG); 539 regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG); 540 regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG); 541 regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG); 542 543 regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG); 544 regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG); 545 regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG); 546 regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG); 547 548 regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG); 549 regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG); 550 551 /* ppe static */ 552 regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); 553 regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); 554 regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); 555 regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); 556 regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); 557 regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); 558 regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); 559 regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); 560 regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); 561 regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); 562 regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); 563 regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); 564 565 regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG); 566 regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG); 567 regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG); 568 regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG); 569 regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG); 570 regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG); 571 regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG); 572 regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG); 573 regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG); 574 regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG); 575 regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG); 576 regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG); 577 regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG); 578 regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG); 579 580 /* mark end of ppe regs */ 581 for (i = 572; i < 576; i++) 582 regs[i] = 0xeeeeeeee; 583} 584