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Searched refs:invalidate (Results 1 – 100 of 100) sorted by relevance

/linux-4.1.27/arch/arm/mm/
Dcache-fa.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
[all …]
Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
[all …]
Dproc-arm926.S83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm925.S123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-mohawk.S75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm920.S91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dcache-v4wt.S51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
Dproc-arm922.S93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
234 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-fa526.S63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
142 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
145 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
147 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
[all …]
Dproc-arm1026.S90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
266 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
Dproc-arm1022.S90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
Dproc-arm946.S87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm1020e.S99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
252 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
281 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
Dtlb-v7.S50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
Dtlb-v6.S49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
Dproc-arm1020.S99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
198 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
236 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
258 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
292 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
Dproc-feroceon.S104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
191 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
193 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
194 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-xsc3.S71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
205 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
[all …]
Dcache-v4wb.S61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
80 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
120 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
167 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
172 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
194 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
Dtlb-v4wb.S41 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
44 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
64 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
65 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dtlb-v4wbi.S43 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
44 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
55 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
56 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dcache-v7.S77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
78 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
157 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
190 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
191 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
208 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
209 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
290 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
295 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
296 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
[all …]
Dproc-sa1100.S76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dproc-sa110.S68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
Dproc-v6.S156 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
208 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
Dproc-xscale.S150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
162 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
308 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
334 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
369 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
478 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
548 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
549 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
[all …]
Dproc-arm720.S80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
Dproc-arm940.S80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
237 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
280 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
Dtlb-fa.S46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
Dtlb-v4.S41 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
Dproc-arm740.S55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
Dproc-v7.S120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
429 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
431 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
DKconfig553 ARM Architecture Version 4 TLB with writeback cache and invalidate
565 and invalidate instruction cache entry. Branch target buffer is
910 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
916 clean operation followed immediately by an invalidate operation,
/linux-4.1.27/arch/mn10300/mm/
Dcache-flush-by-reg.S181 # Flush the entire data cache and invalidate all entries
196 # wait for busy bit of area purge & invalidate
206 # area purge & invalidate
210 # wait for busy bit of area purge & invalidate
227 # Flush and invalidate a range of addresses on a page in the dcache
271 # wait for busy bit of area purge & invalidate
286 # area purge & invalidate
291 # wait for busy bit of area purge & invalidate
297 # check purge & invalidate of end address
DKconfig.cache53 prompt "CPU cache flush/invalidate method"
112 Set if the debugger needs to flush the dcache and invalidate the
121 Set if the debugger needs to flush the dcache and invalidate the
130 Set if the debugger needs to invalidate the icache using the cache
139 Set if the debugger needs to invalidate the icache using automatic
147 invalidate the icache to make breakpoints work.
Dcache.inc45 # invalidate
66 # invalidate
106 # invalidate
127 # invalidate
Dcache-dbg-flush-by-reg.S25 # Flush the entire data cache back to RAM and invalidate the icache
74 # secondly, invalidate the icache if it is enabled
Dcache-dbg-inv.S36 # we only need to invalidate the icache in this cache mode
Dcache-dbg-flush-by-tag.S26 # Flush the entire data cache back to RAM and invalidate the icache
Dcache-inv-by-reg.S136 # writeback mode, in which case we would be in flush and invalidate by
Dcache-inv-by-tag.S155 # cache line then invalidate that line
/linux-4.1.27/arch/unicore32/mm/
Dproc-ucv2.S40 movc p0.c5, ip, #28 @ Cache invalidate all
43 movc p0.c6, ip, #6 @ TLB invalidate all
107 movc p0.c6, ip, #6 @ TLB invalidate all
Dcache-ucv2.S38 movc p0.c5, r0, #20 @ Icache invalidate all
77 movc p0.c5, ip, #20 @ Icache invalidate all
127 movc p0.c5, ip, #20 @ Icache invalidate all
/linux-4.1.27/arch/unicore32/boot/compressed/
Dhead.S87 movc p0.c5, r0, #28 @ cache invalidate all
89 movc p0.c6, r0, #6 @ tlb invalidate all
145 movc p0.c5, r0, #20 @ icache invalidate all
/linux-4.1.27/arch/m32r/boot/compressed/
Dhead.S138 ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache
143 ldi r1, 0x0100 ; invalidate
148 ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
/linux-4.1.27/arch/arm/boot/compressed/
Dhead.S658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1069 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1070 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1086 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1088 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1111 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1114 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1121 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
/linux-4.1.27/drivers/gpu/drm/i915/
Di915_trace.h478 TP_PROTO(struct intel_engine_cs *ring, u32 invalidate, u32 flush),
479 TP_ARGS(ring, invalidate, flush),
484 __field(u32, invalidate)
491 __entry->invalidate = invalidate;
497 __entry->invalidate, __entry->flush)
Dintel_ringbuffer.c2334 u32 invalidate, u32 flush) in gen6_bsd_ring_flush() argument
2360 if (invalidate & I915_GEM_GPU_DOMAINS) in gen6_bsd_ring_flush()
2446 u32 invalidate, u32 flush) in gen6_ring_flush() argument
2473 if (invalidate & I915_GEM_DOMAIN_RENDER) in gen6_ring_flush()
/linux-4.1.27/fs/ceph/
Dsnap.c649 int invalidate = 0; in ceph_update_snap_trace() local
678 invalidate += err; in ceph_update_snap_trace()
703 invalidate = 1; in ceph_update_snap_trace()
707 invalidate = 1; in ceph_update_snap_trace()
714 realm, invalidate, p, e); in ceph_update_snap_trace()
717 if (invalidate && p >= e) in ceph_update_snap_trace()
/linux-4.1.27/arch/unicore32/kernel/
Dhead.S133 movc p0.c5, r0, #28 @ cache invalidate all
135 movc p0.c6, r0, #6 @ TLB invalidate all
Dsleep.S171 movc p0.c6, r1, #6 @ invalidate I & D TLBs
172 movc p0.c5, r1, #28 @ invalidate I & D caches, BTB
Dhibernate_asm.S31 movc p0.c6, r5, #6 @invalidate ITLB & DTLB
/linux-4.1.27/arch/sh/include/mach-kfr2r09/mach/
Dpartner-jet-setup.txt19 LIST "invalidate instruction cache"
22 LIST "invalidate TLBs"
/linux-4.1.27/include/linux/
Dfscache.h804 void fscache_disable_cookie(struct fscache_cookie *cookie, bool invalidate) in fscache_disable_cookie() argument
807 __fscache_disable_cookie(cookie, invalidate); in fscache_disable_cookie()
/linux-4.1.27/arch/frv/lib/
Dcache.S81 # Write back and invalidate a range of dcache and icache
/linux-4.1.27/fs/fscache/
Dcookie.c511 void __fscache_disable_cookie(struct fscache_cookie *cookie, bool invalidate) in __fscache_disable_cookie() argument
516 _enter("%p,%u", cookie, invalidate); in __fscache_disable_cookie()
542 if (invalidate) in __fscache_disable_cookie()
/linux-4.1.27/fs/jffs2/
DLICENCE28 This exception does not invalidate any other reasons why a work based on
/linux-4.1.27/arch/arm/mach-tegra/
Dsleep.h113 streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
Dsleep-tegra20.S299 mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
300 mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
/linux-4.1.27/drivers/md/
Ddm-cache-target.c274 bool invalidate:1; member
324 bool invalidate:1; member
1001 if (mg->invalidate) in migration_success_post_commit()
1262 mg->invalidate = false; in promote()
1286 mg->invalidate = false; in writeback()
1312 mg->invalidate = false; in demote_then_promote()
1329 static void invalidate(struct cache *cache, struct prealloc *structs, in invalidate() function
1341 mg->invalidate = true; in invalidate()
1364 mg->invalidate = false; in discard()
1523 invalidate(cache, structs, block, lookup_result.cblock, new_ocell); in process_bio()
[all …]
/linux-4.1.27/Documentation/vm/
Dcleancache.txt48 an "invalidate_inode" will invalidate all pages associated with the specified
49 file; and, when a filesystem is unmounted, an "invalidate_fs" will invalidate
69 cleancache invalidate operations as required.
194 The invalidate is done by the cleancache backend implementation.
224 add hooks to do the equivalent cleancache "invalidate" operations
Dzswap.txt55 in the swap_map goes to 0) the swap code calls the zswap invalidate function,
Dfrontswap.txt252 frontswap rejects a store that would overwrite, it also must invalidate
/linux-4.1.27/Documentation/filesystems/
Dsysfs-tagging.txt33 namespace exits, it will call kobj_ns_exit() to invalidate any
Dnilfs2.txt163 rmcp invalidate specified checkpoint(s).
DLocking558 no truncate/invalidate races, and then return with the page locked. If
Dcoda.txt1457 invalidate cache entries when it modifies or removes objects.
Dvfs.txt727 The second case is when a request has been made to invalidate
/linux-4.1.27/net/rds/
Dib_rdma.c694 void rds_ib_free_mr(void *trans_private, int invalidate) in rds_ib_free_mr() argument
716 if (invalidate) { in rds_ib_free_mr()
Dib.h308 void rds_ib_free_mr(void *trans_private, int invalidate);
Diw_rdma.c551 void rds_iw_free_mr(void *trans_private, int invalidate) argument
568 if (invalidate) {
Diw.h318 void rds_iw_free_mr(void *trans_private, int invalidate);
Drds.h450 void (*free_mr)(void *trans_private, int invalidate);
/linux-4.1.27/Documentation/x86/
Dtlb.txt7 2. Use the invlpg instruction to invalidate a single page at a
/linux-4.1.27/arch/arm64/
DKconfig306 data cache clean-and-invalidate.
327 data cache clean-and-invalidate.
349 data cache clean-and-invalidate.
370 data cache clean-and-invalidate.
/linux-4.1.27/arch/powerpc/platforms/powernv/
Dpci-ioda.c1679 __be64 __iomem *invalidate = rm ? in pnv_pci_ioda1_tce_invalidate() local
1710 __raw_rm_writeq(cpu_to_be64(start), invalidate); in pnv_pci_ioda1_tce_invalidate()
1712 __raw_writeq(cpu_to_be64(start), invalidate); in pnv_pci_ioda1_tce_invalidate()
1727 __be64 __iomem *invalidate = rm ? in pnv_pci_ioda2_tce_invalidate() local
1747 __raw_rm_writeq(cpu_to_be64(start), invalidate); in pnv_pci_ioda2_tce_invalidate()
1749 __raw_writeq(cpu_to_be64(start), invalidate); in pnv_pci_ioda2_tce_invalidate()
/linux-4.1.27/arch/mn10300/kernel/
Dhead.S93 # invalidate and enable both of the caches
/linux-4.1.27/arch/powerpc/platforms/pseries/
Diommu.c57 u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; in tce_invalidate_pSeries_sw() local
78 out_be64(invalidate, start); in tce_invalidate_pSeries_sw()
/linux-4.1.27/security/keys/
Dkeyctl.c421 goto invalidate; in keyctl_invalidate_key()
428 invalidate: in keyctl_invalidate_key()
/linux-4.1.27/Documentation/arm/
DInterrupts10 and finally TLB v4 (with write buffer, with I TLB invalidate entry).
/linux-4.1.27/arch/ia64/include/asm/
Dpal.h948 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) in ia64_pal_cache_flush() argument
951 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); in ia64_pal_cache_flush()
/linux-4.1.27/Documentation/filesystems/caching/
Dnetfs-api.txt748 invalidate its state; allocate, read or write backing pages - though it is
755 bool invalidate);
847 There is no direct way to invalidate an index subtree. To do this, the caller
855 Sometimes it will be necessary to invalidate an object that contains data.
Dbackend-api.txt324 This is called to invalidate a data object (as pointed to by op->object).
/linux-4.1.27/arch/frv/kernel/
Dhead.S48 # invalidate and disable both of the caches and turn off the memory access checking
/linux-4.1.27/arch/arm/mach-omap2/
Dsleep34xx.S484 mov r12, #0x1 @ set up to invalidate L2
/linux-4.1.27/Documentation/scsi/
Dncr53c8xx.txt803 0x2: Set write and invalidate bit in PCI command register.
912 0x2: Set write and invalidate bit in PCI command register.
919 and PCI write and invalidate commands. These features require the
922 invalidate commands only if the corresponding bit is set to 1 in the
926 invalidate bit in the PCI configuration space of 53C8XX chips.
1059 read line, prefetch, cache line, write and invalidate,
/linux-4.1.27/drivers/dma/
Dpl330.c813 unsigned invalidate) in _emit_WFE() argument
824 if (invalidate) in _emit_WFE()
828 ev >> 3, invalidate ? ", I" : ""); in _emit_WFE()
/linux-4.1.27/fs/affs/
DChanges147 - getblock() did not invalidate the key cache
/linux-4.1.27/fs/f2fs/
Dnode.c589 goto invalidate; in truncate_node()
604 invalidate: in truncate_node()
/linux-4.1.27/arch/blackfin/
DKconfig1065 broken drivers that do not properly invalidate/flush their
1082 broken drivers that do not properly invalidate/flush their
/linux-4.1.27/Documentation/input/
Dmulti-touch-protocol.txt71 contact associated with a slot changes, the driver should invalidate that
/linux-4.1.27/fs/ext4/
Dinode.c1441 bool invalidate) in mpage_release_unused_pages() argument
1455 if (invalidate) { in mpage_release_unused_pages()
1473 if (invalidate) { in mpage_release_unused_pages()
/linux-4.1.27/Documentation/PCI/
Dpci-error-recovery.txt203 >>> segment, and thus invalidate the recovery that other devices
/linux-4.1.27/Documentation/
Ddma-buf-sharing.txt246 1. Prepare access, which invalidate any necessary caches and make the object
Dmemory-barriers.txt2838 invalidate them as well).
2845 appropriate part of the kernel must invalidate the overlapping bits of the
/linux-4.1.27/Documentation/virtual/uml/
DUserModeLinux-HOWTO.txt1933 will invalidate any COW files that are using it. The mtime and size
1985 one of them will invalidate all of the others. However, it is
/linux-4.1.27/Documentation/block/
Dbiodoc.txt756 Certain hardware conditions may dictate a need to invalidate the block tag
/linux-4.1.27/drivers/scsi/aic7xxx/
Daic7xxx.seq790 * be transferred using memory write and invalidate PCI transactions.
/linux-4.1.27/arch/arm/
DKconfig1128 tables. The workaround changes the TLB flushing routines to invalidate
/linux-4.1.27/Documentation/virtual/kvm/
Dapi.txt1628 should skip processing the bitmap and just invalidate everything. It must