Lines Matching refs:invalidate
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
255 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
291 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
351 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
359 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
365 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
368 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
402 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
403 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
416 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
419 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4